3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/clkdev.h>
23 #include <linux/init.h>
24 #include <linux/list.h>
25 #include <linux/module.h>
26 #include <linux/sched.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
32 #include "tegra_cpu_car.h"
34 /* Global data of Tegra CPU CAR ops */
35 struct tegra_cpu_car_ops *tegra_cpu_car_ops;
40 * An additional mutex, clock_list_lock, is used to protect the list of all
44 static DEFINE_MUTEX(clock_list_lock);
45 static LIST_HEAD(clocks);
47 void tegra_clk_add(struct clk *clk)
49 struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
51 mutex_lock(&clock_list_lock);
52 list_add(&c->node, &clocks);
53 mutex_unlock(&clock_list_lock);
56 struct clk *tegra_get_clock_by_name(const char *name)
59 struct clk *ret = NULL;
60 mutex_lock(&clock_list_lock);
61 list_for_each_entry(c, &clocks, node) {
62 if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
67 mutex_unlock(&clock_list_lock);
71 static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
79 c = tegra_get_clock_by_name(table->name);
82 pr_warn("Unable to initialize clock %s\n",
87 parent = clk_get_parent(c);
90 p = tegra_get_clock_by_name(table->parent);
92 pr_warn("Unable to find parent %s of clock %s\n",
93 table->parent, table->name);
98 ret = clk_set_parent(c, p);
100 pr_warn("Unable to set parent %s of clock %s: %d\n",
101 table->parent, table->name, ret);
107 if (table->rate && table->rate != clk_get_rate(c)) {
108 ret = clk_set_rate(c, table->rate);
110 pr_warn("Unable to set clock %s to rate %lu: %d\n",
111 table->name, table->rate, ret);
116 if (table->enabled) {
117 ret = clk_prepare_enable(c);
119 pr_warn("Unable to enable clock %s: %d\n",
128 void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
130 for (; table->name; table++)
131 tegra_clk_init_one_from_table(table);
134 void tegra_periph_reset_deassert(struct clk *c)
136 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
138 clk->reset(__clk_get_hw(c), false);
140 EXPORT_SYMBOL(tegra_periph_reset_deassert);
142 void tegra_periph_reset_assert(struct clk *c)
144 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
146 clk->reset(__clk_get_hw(c), true);
148 EXPORT_SYMBOL(tegra_periph_reset_assert);
150 /* Several extended clock configuration bits (e.g., clock routing, clock
151 * phase control) are included in PLL and peripheral clock source
153 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
156 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
158 if (!clk->clk_cfg_ex) {
162 ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);