Pileus Git - ~andy/linux/blob - arch/arm/mach-tegra/board-dt-tegra20.c

   1 /*
   2  * nVidia Tegra device tree board support
   3  *
   4  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
   5  * Copyright (C) 2010 Google, Inc.
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/serial_8250.h>
  22 #include <linux/clk.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/irqdomain.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_fdt.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/pda_power.h>
  31 #include <linux/io.h>
  32 #include <linux/i2c.h>
  33 #include <linux/i2c-tegra.h>
  34
  35 #include <asm/hardware/gic.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/time.h>
  39 #include <asm/setup.h>
  40
  41 #include <mach/iomap.h>
  42 #include <mach/irqs.h>
  43
  44 #include "board.h"
  45 #include "board-harmony.h"
  46 #include "clock.h"
  47 #include "devices.h"
  48
  49 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
  50         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
  51         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
  52         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
  53         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL),
  54         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
  55         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
  56         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
  57         OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
  58         OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL),
  59         OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL),
  60         OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL),
  61         OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
  62                        &tegra_ehci1_pdata),
  63         OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
  64                        &tegra_ehci2_pdata),
  65         OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
  66                        &tegra_ehci3_pdata),
  67         {}
  68 };
  69
  70 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
  71         /* name         parent          rate            enabled */
  72         { "uartd",      "pll_p",        216000000,      true },
  73         { "usbd",       "clk_m",        12000000,       false },
  74         { "usb2",       "clk_m",        12000000,       false },
  75         { "usb3",       "clk_m",        12000000,       false },
  76         { "pll_a",      "pll_p_out1",   56448000,       true },
  77         { "pll_a_out0", "pll_a",        11289600,       true },
  78         { "cdev1",      NULL,           0,              true },
  79         { "i2s1",       "pll_a_out0",   11289600,       false},
  80         { "i2s2",       "pll_a_out0",   11289600,       false},
  81         { NULL,         NULL,           0,              0},
  82 };
  83
  84 static struct of_device_id tegra_dt_match_table[] __initdata = {
  85         { .compatible = "simple-bus", },
  86         {}
  87 };
  88
  89 static void __init tegra_dt_init(void)
  90 {
  91         tegra_clk_init_from_table(tegra_dt_clk_init_table);
  92
  93         /*
  94          * Finished with the static registrations now; fill in the missing
  95          * devices
  96          */
  97         of_platform_populate(NULL, tegra_dt_match_table,
  98                                 tegra20_auxdata_lookup, NULL);
  99 }
 100
 101 #ifdef CONFIG_MACH_TRIMSLICE
 102 static void __init trimslice_init(void)
 103 {
 104         int ret;
 105
 106         ret = tegra_pcie_init(true, true);
 107         if (ret)
 108                 pr_err("tegra_pci_init() failed: %d\n", ret);
 109 }
 110 #endif
 111
 112 #ifdef CONFIG_MACH_HARMONY
 113 static void __init harmony_init(void)
 114 {
 115         int ret;
 116
 117         ret = harmony_regulator_init();
 118         if (ret) {
 119                 pr_err("harmony_regulator_init() failed: %d\n", ret);
 120                 return;
 121         }
 122
 123         ret = harmony_pcie_init();
 124         if (ret)
 125                 pr_err("harmony_pcie_init() failed: %d\n", ret);
 126 }
 127 #endif
 128
 129 #ifdef CONFIG_MACH_PAZ00
 130 static void __init paz00_init(void)
 131 {
 132         tegra_paz00_wifikill_init();
 133 }
 134 #endif
 135
 136 static struct {
 137         char *machine;
 138         void (*init)(void);
 139 } board_init_funcs[] = {
 140 #ifdef CONFIG_MACH_TRIMSLICE
 141         { "compulab,trimslice", trimslice_init },
 142 #endif
 143 #ifdef CONFIG_MACH_HARMONY
 144         { "nvidia,harmony", harmony_init },
 145 #endif
 146 #ifdef CONFIG_MACH_PAZ00
 147         { "compal,paz00", paz00_init },
 148 #endif
 149 };
 150
 151 static void __init tegra_dt_init_late(void)
 152 {
 153         int i;
 154
 155         tegra_init_late();
 156
 157         for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
 158                 if (of_machine_is_compatible(board_init_funcs[i].machine)) {
 159                         board_init_funcs[i].init();
 160                         break;
 161                 }
 162         }
 163 }
 164
 165 static const char *tegra20_dt_board_compat[] = {
 166         "nvidia,tegra20",
 167         NULL
 168 };
 169
 170 DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
 171         .map_io         = tegra_map_common_io,
 172         .init_early     = tegra20_init_early,
 173         .init_irq       = tegra_dt_init_irq,
 174         .handle_irq     = gic_handle_irq,
 175         .timer          = &tegra_timer,
 176         .init_machine   = tegra_dt_init,
 177         .init_late      = tegra_dt_init_late,
 178         .restart        = tegra_assert_system_reset,
 179         .dt_compat      = tegra20_dt_board_compat,
 180 MACHINE_END