Pileus Git - ~andy/linux/blob - arch/arm/mach-stmp378x/stmp378x.c

   1 /*
   2  * Freescale STMP378X platform support
   3  *
   4  * Embedded Alley Solutions, Inc <source@embeddedalley.com>
   5  *
   6  * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   8  */
   9
  10 /*
  11  * The code contained herein is licensed under the GNU General Public
  12  * License. You may obtain a copy of the GNU General Public License
  13  * Version 2 or later at the following locations:
  14  *
  15  * http://www.opensource.org/licenses/gpl-license.html
  16  * http://www.gnu.org/copyleft/gpl.html
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/irq.h>
  22
  23 #include <asm/dma.h>
  24 #include <asm/setup.h>
  25 #include <asm/mach-types.h>
  26
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/irq.h>
  29 #include <asm/mach/map.h>
  30 #include <asm/mach/time.h>
  31
  32 #include <mach/pins.h>
  33 #include <mach/pinmux.h>
  34 #include <mach/dma.h>
  35 #include <mach/hardware.h>
  36 #include <mach/system.h>
  37 #include <mach/platform.h>
  38 #include <mach/stmp3xxx.h>
  39 #include <mach/regs-icoll.h>
  40 #include <mach/regs-apbh.h>
  41 #include <mach/regs-apbx.h>
  42
  43 #include "stmp378x.h"
  44 /*
  45  * IRQ handling
  46  */
  47 static void stmp378x_ack_irq(unsigned int irq)
  48 {
  49         /* Tell ICOLL to release IRQ line */
  50         HW_ICOLL_VECTOR_WR(0x0);
  51
  52         /* ACK current interrupt */
  53         HW_ICOLL_LEVELACK_WR(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0);
  54
  55         /* Barrier */
  56         (void) HW_ICOLL_STAT_RD();
  57 }
  58
  59 static void stmp378x_mask_irq(unsigned int irq)
  60 {
  61         /* IRQ disable */
  62         HW_ICOLL_INTERRUPTn_CLR(irq, BM_ICOLL_INTERRUPTn_ENABLE);
  63 }
  64
  65 static void stmp378x_unmask_irq(unsigned int irq)
  66 {
  67         /* IRQ enable */
  68         HW_ICOLL_INTERRUPTn_SET(irq, BM_ICOLL_INTERRUPTn_ENABLE);
  69 }
  70
  71 static struct irq_chip stmp378x_chip = {
  72         .ack    = stmp378x_ack_irq,
  73         .mask   = stmp378x_mask_irq,
  74         .unmask = stmp378x_unmask_irq,
  75 };
  76
  77 void __init stmp378x_init_irq(void)
  78 {
  79         stmp3xxx_init_irq(&stmp378x_chip);
  80 }
  81
  82 /*
  83  * DMA interrupt handling
  84  */
  85 void stmp3xxx_arch_dma_enable_interrupt(int channel)
  86 {
  87         int dmabus = channel / 16;
  88
  89         switch (dmabus) {
  90         case STMP3XXX_BUS_APBH:
  91                 HW_APBH_CTRL1_SET(1 << (16 + (channel % 16)));
  92                 HW_APBH_CTRL2_SET(1 << (16 + (channel % 16)));
  93                 break;
  94
  95         case STMP3XXX_BUS_APBX:
  96                 HW_APBX_CTRL1_SET(1 << (16 + (channel % 16)));
  97                 HW_APBX_CTRL2_SET(1 << (16 + (channel % 16)));
  98                 break;
  99         }
 100 }
 101 EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
 102
 103 void stmp3xxx_arch_dma_clear_interrupt(int channel)
 104 {
 105         int dmabus = channel / 16;
 106
 107         switch (dmabus) {
 108         case STMP3XXX_BUS_APBH:
 109                 HW_APBH_CTRL1_CLR(1 << (channel % 16));
 110                 HW_APBH_CTRL2_CLR(1 << (channel % 16));
 111                 break;
 112
 113         case STMP3XXX_BUS_APBX:
 114                 HW_APBX_CTRL1_CLR(1 << (channel % 16));
 115                 HW_APBX_CTRL2_CLR(1 << (channel % 16));
 116                 break;
 117         }
 118 }
 119 EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
 120
 121 int stmp3xxx_arch_dma_is_interrupt(int channel)
 122 {
 123         int dmabus = channel / 16;
 124         int r = 0;
 125
 126         switch (dmabus) {
 127         case STMP3XXX_BUS_APBH:
 128                 r = HW_APBH_CTRL1_RD() & (1 << (channel % 16));
 129                 break;
 130
 131         case STMP3XXX_BUS_APBX:
 132                 r = HW_APBX_CTRL1_RD() & (1 << (channel % 16));
 133                 break;
 134         }
 135         return r;
 136 }
 137 EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
 138
 139 void stmp3xxx_arch_dma_reset_channel(int channel)
 140 {
 141         int dmabus = channel / 16;
 142         unsigned chbit = 1 << (channel % 16);
 143
 144         switch (dmabus) {
 145         case STMP3XXX_BUS_APBH:
 146                 /* Reset channel and wait for it to complete */
 147                 HW_APBH_CTRL0_SET(chbit <<
 148                                  BP_APBH_CTRL0_RESET_CHANNEL);
 149                 while (HW_APBH_CTRL0_RD() &
 150                        (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
 151                         continue;
 152                 break;
 153
 154         case STMP3XXX_BUS_APBX:
 155                 /* Reset channel and wait for it to complete */
 156                 HW_APBX_CHANNEL_CTRL_SET(
 157                         BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit));
 158                 while (HW_APBX_CHANNEL_CTRL_RD() &
 159                         BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit))
 160                         continue;
 161                 break;
 162         }
 163 }
 164 EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
 165
 166 void stmp3xxx_arch_dma_freeze(int channel)
 167 {
 168         int dmabus = channel / 16;
 169         unsigned chbit = 1 << (channel % 16);
 170
 171         switch (dmabus) {
 172         case STMP3XXX_BUS_APBH:
 173                 HW_APBH_CTRL0_SET(1<<chbit);
 174                 break;
 175         case STMP3XXX_BUS_APBX:
 176                 HW_APBX_CHANNEL_CTRL_SET(1<<chbit);
 177                 break;
 178         }
 179 }
 180 EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
 181
 182 void stmp3xxx_arch_dma_unfreeze(int channel)
 183 {
 184         int dmabus = channel / 16;
 185         unsigned chbit = 1 << (channel % 16);
 186
 187         switch (dmabus) {
 188         case STMP3XXX_BUS_APBH:
 189                 HW_APBH_CTRL0_CLR(1<<chbit);
 190                 break;
 191         case STMP3XXX_BUS_APBX:
 192                 HW_APBX_CHANNEL_CTRL_CLR(1<<chbit);
 193                 break;
 194         }
 195 }
 196 EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
 197
 198 /*
 199  * The registers are all very closely mapped, so we might as well map them all
 200  * with a single mapping
 201  *
 202  * Logical      Physical
 203  * f0000000     80000000        On-chip registers
 204  * f1000000     00000000        256k on-chip SRAM
 205  */
 206
 207 static struct map_desc stmp378x_io_desc[] __initdata = {
 208         {
 209                 .virtual        = (u32)STMP3XXX_REGS_BASE,
 210                 .pfn            = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
 211                 .length         = STMP3XXX_REGS_SIZE,
 212                 .type           = MT_DEVICE,
 213         },
 214         {
 215                 .virtual        = (u32)STMP3XXX_OCRAM_BASE,
 216                 .pfn            = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
 217                 .length         = STMP3XXX_OCRAM_SIZE,
 218                 .type           = MT_DEVICE,
 219         },
 220 };
 221
 222 void __init stmp378x_map_io(void)
 223 {
 224         iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
 225 }