Pileus Git - ~andy/linux/blob - arch/arm/mach-stmp378x/include/mach/regs-timrot.h

   1 /*
   2  * STMP TIMROT Register Definitions
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor
   5  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21
  22 #ifndef __ARCH_ARM___TIMROT_H
  23 #define __ARCH_ARM___TIMROT_H  1
  24
  25 #include <mach/stmp3xxx_regs.h>
  26
  27 #define REGS_TIMROT_BASE (REGS_BASE + 0x68000)
  28 #define REGS_TIMROT_BASE_PHYS (0x80068000)
  29 #define REGS_TIMROT_SIZE 0x00002000
  30 HW_REGISTER(HW_TIMROT_ROTCTRL, REGS_TIMROT_BASE, 0x00000000)
  31 #define HW_TIMROT_ROTCTRL_ADDR (REGS_TIMROT_BASE + 0x00000000)
  32 #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
  33 #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
  34 #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
  35 #define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000
  36 #define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000
  37 #define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000
  38 #define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000
  39 #define BP_TIMROT_ROTCTRL_STATE      22
  40 #define BM_TIMROT_ROTCTRL_STATE 0x01C00000
  41 #define BF_TIMROT_ROTCTRL_STATE(v)  \
  42         (((v) << 22) & BM_TIMROT_ROTCTRL_STATE)
  43 #define BP_TIMROT_ROTCTRL_DIVIDER      16
  44 #define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
  45 #define BF_TIMROT_ROTCTRL_DIVIDER(v)  \
  46         (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER)
  47 #define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
  48 #define BP_TIMROT_ROTCTRL_OVERSAMPLE      10
  49 #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
  50 #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)  \
  51         (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE)
  52 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0
  53 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1
  54 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2
  55 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3
  56 #define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
  57 #define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
  58 #define BP_TIMROT_ROTCTRL_SELECT_B      4
  59 #define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
  60 #define BF_TIMROT_ROTCTRL_SELECT_B(v)  \
  61         (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B)
  62 #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0
  63 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0       0x1
  64 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1       0x2
  65 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2       0x3
  66 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3       0x4
  67 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4       0x5
  68 #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA    0x6
  69 #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB    0x7
  70 #define BP_TIMROT_ROTCTRL_SELECT_A      0
  71 #define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
  72 #define BF_TIMROT_ROTCTRL_SELECT_A(v)  \
  73         (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A)
  74 #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0
  75 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0       0x1
  76 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1       0x2
  77 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2       0x3
  78 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3       0x4
  79 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4       0x5
  80 #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA    0x6
  81 #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB    0x7
  82 HW_REGISTER_0(HW_TIMROT_ROTCOUNT, REGS_TIMROT_BASE, 0x00000010)
  83 #define HW_TIMROT_ROTCOUNT_ADDR (REGS_TIMROT_BASE + 0x00000010)
  84 #define BP_TIMROT_ROTCOUNT_UPDOWN      0
  85 #define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
  86 #define BF_TIMROT_ROTCOUNT_UPDOWN(v)  \
  87         (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN)
  88 /*
  89  *  multi-register-define name HW_TIMROT_TIMCTRLn
  90  *            base 0x00000020
  91  *            count 3
  92  *            offset 0x20
  93  */
  94 HW_REGISTER_INDEXED(HW_TIMROT_TIMCTRLn, REGS_TIMROT_BASE, 0x00000020, 0x20)
  95 #define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
  96 #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
  97 #define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100
  98 #define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
  99 #define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
 100 #define BP_TIMROT_TIMCTRLn_PRESCALE      4
 101 #define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
 102 #define BF_TIMROT_TIMCTRLn_PRESCALE(v)  \
 103         (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE)
 104 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0
 105 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1
 106 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2
 107 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3
 108 #define BP_TIMROT_TIMCTRLn_SELECT      0
 109 #define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
 110 #define BF_TIMROT_TIMCTRLn_SELECT(v)  \
 111         (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT)
 112 #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK  0x0
 113 #define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1
 114 #define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2
 115 #define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3
 116 #define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4
 117 #define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5
 118 #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA     0x6
 119 #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB     0x7
 120 #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL  0x8
 121 #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL   0x9
 122 #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL   0xA
 123 #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL   0xB
 124 #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xC
 125 /*
 126  *  multi-register-define name HW_TIMROT_TIMCOUNTn
 127  *            base 0x00000030
 128  *            count 3
 129  *            offset 0x20
 130  */
 131 HW_REGISTER_0_INDEXED(HW_TIMROT_TIMCOUNTn, REGS_TIMROT_BASE, 0x00000030,
 132                        0x20)
 133 #define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT      16
 134 #define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xFFFF0000
 135 #define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) \
 136         (((v) << 16) & BM_TIMROT_TIMCOUNTn_RUNNING_COUNT)
 137 #define BP_TIMROT_TIMCOUNTn_FIXED_COUNT      0
 138 #define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0x0000FFFF
 139 #define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)  \
 140         (((v) << 0) & BM_TIMROT_TIMCOUNTn_FIXED_COUNT)
 141 HW_REGISTER(HW_TIMROT_TIMCTRL3, REGS_TIMROT_BASE, 0x00000080)
 142 #define HW_TIMROT_TIMCTRL3_ADDR (REGS_TIMROT_BASE + 0x00000080)
 143 #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL      16
 144 #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000
 145 #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)  \
 146         (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL)
 147 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
 148 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0    0x1
 149 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1    0x2
 150 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2    0x3
 151 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3    0x4
 152 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4    0x5
 153 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
 154 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
 155 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
 156 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
 157 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xA
 158 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xB
 159 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xC
 160 #define BM_TIMROT_TIMCTRL3_IRQ 0x00008000
 161 #define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000
 162 #define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400
 163 #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200
 164 #define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100
 165 #define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080
 166 #define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040
 167 #define BP_TIMROT_TIMCTRL3_PRESCALE      4
 168 #define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030
 169 #define BF_TIMROT_TIMCTRL3_PRESCALE(v)  \
 170         (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE)
 171 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0
 172 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1
 173 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2
 174 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3
 175 #define BP_TIMROT_TIMCTRL3_SELECT      0
 176 #define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F
 177 #define BF_TIMROT_TIMCTRL3_SELECT(v)  \
 178         (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT)
 179 #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK  0x0
 180 #define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1
 181 #define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2
 182 #define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3
 183 #define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4
 184 #define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5
 185 #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA     0x6
 186 #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB     0x7
 187 #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL  0x8
 188 #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL   0x9
 189 #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL   0xA
 190 #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL   0xB
 191 #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xC
 192 HW_REGISTER_0(HW_TIMROT_TIMCOUNT3, REGS_TIMROT_BASE, 0x00000090)
 193 #define HW_TIMROT_TIMCOUNT3_ADDR (REGS_TIMROT_BASE + 0x00000090)
 194 #define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT      16
 195 #define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xFFFF0000
 196 #define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) \
 197         (((v) << 16) & BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT)
 198 #define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT      0
 199 #define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0x0000FFFF
 200 #define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)  \
 201         (((v) << 0) & BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT)
 202 HW_REGISTER_0(HW_TIMROT_VERSION, REGS_TIMROT_BASE, 0x000000a0)
 203 #define HW_TIMROT_VERSION_ADDR (REGS_TIMROT_BASE + 0x000000a0)
 204 #define BP_TIMROT_VERSION_MAJOR      24
 205 #define BM_TIMROT_VERSION_MAJOR 0xFF000000
 206 #define BF_TIMROT_VERSION_MAJOR(v) \
 207         (((v) << 24) & BM_TIMROT_VERSION_MAJOR)
 208 #define BP_TIMROT_VERSION_MINOR      16
 209 #define BM_TIMROT_VERSION_MINOR 0x00FF0000
 210 #define BF_TIMROT_VERSION_MINOR(v)  \
 211         (((v) << 16) & BM_TIMROT_VERSION_MINOR)
 212 #define BP_TIMROT_VERSION_STEP      0
 213 #define BM_TIMROT_VERSION_STEP 0x0000FFFF
 214 #define BF_TIMROT_VERSION_STEP(v)  \
 215         (((v) << 0) & BM_TIMROT_VERSION_STEP)
 216 #endif /* __ARCH_ARM___TIMROT_H */