Pileus Git - ~andy/linux/blob - arch/arm/mach-stmp378x/include/mach/regs-icoll.h

   1 /*
   2  * STMP ICOLL Register Definitions
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor
   5  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21
  22 #ifndef __ARCH_ARM___ICOLL_H
  23 #define __ARCH_ARM___ICOLL_H  1
  24
  25 #include <mach/stmp3xxx_regs.h>
  26
  27 #define REGS_ICOLL_BASE (REGS_BASE + 0x0)
  28 #define REGS_ICOLL_BASE_PHYS (0x80000000)
  29 #define REGS_ICOLL_SIZE 0x00002000
  30 HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00000000)
  31 #define HW_ICOLL_VECTOR_ADDR (REGS_ICOLL_BASE + 0x00000000)
  32 #define BP_ICOLL_VECTOR_IRQVECTOR      2
  33 #define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC
  34 #define BF_ICOLL_VECTOR_IRQVECTOR(v) \
  35         (((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR)
  36 HW_REGISTER_0(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x00000010)
  37 #define HW_ICOLL_LEVELACK_ADDR (REGS_ICOLL_BASE + 0x00000010)
  38 #define BP_ICOLL_LEVELACK_IRQLEVELACK      0
  39 #define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
  40 #define BF_ICOLL_LEVELACK_IRQLEVELACK(v)  \
  41         (((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK)
  42 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
  43 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2
  44 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4
  45 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8
  46 HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x00000020)
  47 #define HW_ICOLL_CTRL_ADDR (REGS_ICOLL_BASE + 0x00000020)
  48 #define BM_ICOLL_CTRL_SFTRST 0x80000000
  49 #define BV_ICOLL_CTRL_SFTRST__RUN      0x0
  50 #define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1
  51 #define BM_ICOLL_CTRL_CLKGATE 0x40000000
  52 #define BV_ICOLL_CTRL_CLKGATE__RUN       0x0
  53 #define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1
  54 #define BP_ICOLL_CTRL_VECTOR_PITCH      21
  55 #define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000
  56 #define BF_ICOLL_CTRL_VECTOR_PITCH(v)  \
  57         (((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH)
  58 #define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0
  59 #define BV_ICOLL_CTRL_VECTOR_PITCH__BY4  0x1
  60 #define BV_ICOLL_CTRL_VECTOR_PITCH__BY8  0x2
  61 #define BV_ICOLL_CTRL_VECTOR_PITCH__BY12        0x3
  62 #define BV_ICOLL_CTRL_VECTOR_PITCH__BY16        0x4
  63 #define BV_ICOLL_CTRL_VECTOR_PITCH__BY20        0x5
  64 #define BV_ICOLL_CTRL_VECTOR_PITCH__BY24        0x6
  65 #define BV_ICOLL_CTRL_VECTOR_PITCH__BY28        0x7
  66 #define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000
  67 #define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0
  68 #define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1
  69 #define BM_ICOLL_CTRL_NO_NESTING 0x00080000
  70 #define BV_ICOLL_CTRL_NO_NESTING__NORMAL  0x0
  71 #define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1
  72 #define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000
  73 #define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000
  74 #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0
  75 #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE  0x1
  76 #define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000
  77 #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0
  78 #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE  0x1
  79 HW_REGISTER(HW_ICOLL_VBASE, REGS_ICOLL_BASE, 0x00000040)
  80 #define HW_ICOLL_VBASE_ADDR (REGS_ICOLL_BASE + 0x00000040)
  81 #define BP_ICOLL_VBASE_TABLE_ADDRESS      2
  82 #define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC
  83 #define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \
  84         (((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS)
  85 HW_REGISTER_0(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x00000070)
  86 #define HW_ICOLL_STAT_ADDR (REGS_ICOLL_BASE + 0x00000070)
  87 #define BP_ICOLL_STAT_VECTOR_NUMBER      0
  88 #define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F
  89 #define BF_ICOLL_STAT_VECTOR_NUMBER(v)  \
  90         (((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER)
  91 /*
  92  *  multi-register-define name HW_ICOLL_RAWn
  93  *            base 0x000000A0
  94  *            count 4
  95  *            offset 0x10
  96  */
  97 HW_REGISTER_0_INDEXED(HW_ICOLL_RAWn, REGS_ICOLL_BASE, 0x000000a0, 0x10)
  98 #define BP_ICOLL_RAWn_RAW_IRQS      0
  99 #define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF
 100 #define BF_ICOLL_RAWn_RAW_IRQS(v)   (v)
 101 /*
 102  *  multi-register-define name HW_ICOLL_INTERRUPTn
 103  *            base 0x00000120
 104  *            count 128
 105  *            offset 0x10
 106  */
 107 HW_REGISTER_INDEXED(HW_ICOLL_INTERRUPTn, REGS_ICOLL_BASE, 0x00000120, 0x10)
 108 #define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010
 109 #define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0
 110 #define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE  0x1
 111 #define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008
 112 #define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT    0x0
 113 #define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1
 114 #define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
 115 #define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0
 116 #define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE  0x1
 117 #define BP_ICOLL_INTERRUPTn_PRIORITY      0
 118 #define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003
 119 #define BF_ICOLL_INTERRUPTn_PRIORITY(v)  \
 120         (((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY)
 121 #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0
 122 #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1
 123 #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2
 124 #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3
 125 HW_REGISTER(HW_ICOLL_DEBUG, REGS_ICOLL_BASE, 0x00001120)
 126 #define HW_ICOLL_DEBUG_ADDR (REGS_ICOLL_BASE + 0x00001120)
 127 #define BP_ICOLL_DEBUG_INSERVICE      28
 128 #define BM_ICOLL_DEBUG_INSERVICE 0xF0000000
 129 #define BF_ICOLL_DEBUG_INSERVICE(v) \
 130         (((v) << 28) & BM_ICOLL_DEBUG_INSERVICE)
 131 #define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1
 132 #define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2
 133 #define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4
 134 #define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8
 135 #define BP_ICOLL_DEBUG_LEVEL_REQUESTS      24
 136 #define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000
 137 #define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)  \
 138         (((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS)
 139 #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1
 140 #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2
 141 #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4
 142 #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8
 143 #define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL      20
 144 #define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000
 145 #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)  \
 146         (((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL)
 147 #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1
 148 #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2
 149 #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4
 150 #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8
 151 #define BM_ICOLL_DEBUG_FIQ 0x00020000
 152 #define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0
 153 #define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED    0x1
 154 #define BM_ICOLL_DEBUG_IRQ 0x00010000
 155 #define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0
 156 #define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED    0x1
 157 #define BP_ICOLL_DEBUG_VECTOR_FSM      0
 158 #define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF
 159 #define BF_ICOLL_DEBUG_VECTOR_FSM(v)  \
 160         (((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM)
 161 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE      0x000
 162 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x001
 163 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x002
 164 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x004
 165 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x008
 166 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x010
 167 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020
 168 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040
 169 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080
 170 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
 171 #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
 172 HW_REGISTER(HW_ICOLL_DBGREAD0, REGS_ICOLL_BASE, 0x00001130)
 173 #define HW_ICOLL_DBGREAD0_ADDR (REGS_ICOLL_BASE + 0x00001130)
 174 #define BP_ICOLL_DBGREAD0_VALUE      0
 175 #define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF
 176 #define BF_ICOLL_DBGREAD0_VALUE(v)   (v)
 177 HW_REGISTER(HW_ICOLL_DBGREAD1, REGS_ICOLL_BASE, 0x00001140)
 178 #define HW_ICOLL_DBGREAD1_ADDR (REGS_ICOLL_BASE + 0x00001140)
 179 #define BP_ICOLL_DBGREAD1_VALUE      0
 180 #define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF
 181 #define BF_ICOLL_DBGREAD1_VALUE(v)   (v)
 182 HW_REGISTER(HW_ICOLL_DBGFLAG, REGS_ICOLL_BASE, 0x00001150)
 183 #define HW_ICOLL_DBGFLAG_ADDR (REGS_ICOLL_BASE + 0x00001150)
 184 #define BP_ICOLL_DBGFLAG_FLAG      0
 185 #define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF
 186 #define BF_ICOLL_DBGFLAG_FLAG(v)  \
 187         (((v) << 0) & BM_ICOLL_DBGFLAG_FLAG)
 188 /*
 189  *  multi-register-define name HW_ICOLL_DBGREQUESTn
 190  *            base 0x00001160
 191  *            count 4
 192  *            offset 0x10
 193  */
 194 HW_REGISTER_0_INDEXED(HW_ICOLL_DBGREQUESTn, REGS_ICOLL_BASE, 0x00001160,
 195                        0x10)
 196 #define BP_ICOLL_DBGREQUESTn_BITS      0
 197 #define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF
 198 #define BF_ICOLL_DBGREQUESTn_BITS(v)   (v)
 199 HW_REGISTER_0(HW_ICOLL_VERSION, REGS_ICOLL_BASE, 0x000011e0)
 200 #define HW_ICOLL_VERSION_ADDR (REGS_ICOLL_BASE + 0x000011e0)
 201 #define BP_ICOLL_VERSION_MAJOR      24
 202 #define BM_ICOLL_VERSION_MAJOR 0xFF000000
 203 #define BF_ICOLL_VERSION_MAJOR(v) \
 204         (((v) << 24) & BM_ICOLL_VERSION_MAJOR)
 205 #define BP_ICOLL_VERSION_MINOR      16
 206 #define BM_ICOLL_VERSION_MINOR 0x00FF0000
 207 #define BF_ICOLL_VERSION_MINOR(v)  \
 208         (((v) << 16) & BM_ICOLL_VERSION_MINOR)
 209 #define BP_ICOLL_VERSION_STEP      0
 210 #define BM_ICOLL_VERSION_STEP 0x0000FFFF
 211 #define BF_ICOLL_VERSION_STEP(v)  \
 212         (((v) << 0) & BM_ICOLL_VERSION_STEP)
 213 #endif /* __ARCH_ARM___ICOLL_H */