Pileus Git - ~andy/linux/blob - arch/arm/mach-spear3xx/spear310.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear310.c
   3  *
   4  * SPEAr310 machine source file
   5  *
   6  * Copyright (C) 2009-2012 ST Microelectronics
   7  * Viresh Kumar <viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr310: " fmt
  15
  16 #include <linux/amba/pl08x.h>
  17 #include <linux/amba/serial.h>
  18 #include <linux/of_platform.h>
  19 #include <asm/hardware/vic.h>
  20 #include <asm/mach/arch.h>
  21 #include <plat/shirq.h>
  22 #include <mach/generic.h>
  23 #include <mach/hardware.h>
  24
  25 /* spear3xx shared irq */
  26 static struct shirq_dev_config shirq_ras1_config[] = {
  27         {
  28                 .virq = SPEAR310_VIRQ_SMII0,
  29                 .status_mask = SPEAR310_SMII0_IRQ_MASK,
  30         }, {
  31                 .virq = SPEAR310_VIRQ_SMII1,
  32                 .status_mask = SPEAR310_SMII1_IRQ_MASK,
  33         }, {
  34                 .virq = SPEAR310_VIRQ_SMII2,
  35                 .status_mask = SPEAR310_SMII2_IRQ_MASK,
  36         }, {
  37                 .virq = SPEAR310_VIRQ_SMII3,
  38                 .status_mask = SPEAR310_SMII3_IRQ_MASK,
  39         }, {
  40                 .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
  41                 .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
  42         }, {
  43                 .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
  44                 .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
  45         }, {
  46                 .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
  47                 .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
  48         }, {
  49                 .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
  50                 .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
  51         },
  52 };
  53
  54 static struct spear_shirq shirq_ras1 = {
  55         .irq = SPEAR3XX_IRQ_GEN_RAS_1,
  56         .dev_config = shirq_ras1_config,
  57         .dev_count = ARRAY_SIZE(shirq_ras1_config),
  58         .regs = {
  59                 .enb_reg = -1,
  60                 .status_reg = SPEAR310_INT_STS_MASK_REG,
  61                 .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
  62                 .clear_reg = -1,
  63         },
  64 };
  65
  66 static struct shirq_dev_config shirq_ras2_config[] = {
  67         {
  68                 .virq = SPEAR310_VIRQ_UART1,
  69                 .status_mask = SPEAR310_UART1_IRQ_MASK,
  70         }, {
  71                 .virq = SPEAR310_VIRQ_UART2,
  72                 .status_mask = SPEAR310_UART2_IRQ_MASK,
  73         }, {
  74                 .virq = SPEAR310_VIRQ_UART3,
  75                 .status_mask = SPEAR310_UART3_IRQ_MASK,
  76         }, {
  77                 .virq = SPEAR310_VIRQ_UART4,
  78                 .status_mask = SPEAR310_UART4_IRQ_MASK,
  79         }, {
  80                 .virq = SPEAR310_VIRQ_UART5,
  81                 .status_mask = SPEAR310_UART5_IRQ_MASK,
  82         },
  83 };
  84
  85 static struct spear_shirq shirq_ras2 = {
  86         .irq = SPEAR3XX_IRQ_GEN_RAS_2,
  87         .dev_config = shirq_ras2_config,
  88         .dev_count = ARRAY_SIZE(shirq_ras2_config),
  89         .regs = {
  90                 .enb_reg = -1,
  91                 .status_reg = SPEAR310_INT_STS_MASK_REG,
  92                 .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
  93                 .clear_reg = -1,
  94         },
  95 };
  96
  97 static struct shirq_dev_config shirq_ras3_config[] = {
  98         {
  99                 .virq = SPEAR310_VIRQ_EMI,
 100                 .status_mask = SPEAR310_EMI_IRQ_MASK,
 101         },
 102 };
 103
 104 static struct spear_shirq shirq_ras3 = {
 105         .irq = SPEAR3XX_IRQ_GEN_RAS_3,
 106         .dev_config = shirq_ras3_config,
 107         .dev_count = ARRAY_SIZE(shirq_ras3_config),
 108         .regs = {
 109                 .enb_reg = -1,
 110                 .status_reg = SPEAR310_INT_STS_MASK_REG,
 111                 .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
 112                 .clear_reg = -1,
 113         },
 114 };
 115
 116 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 117         {
 118                 .virq = SPEAR310_VIRQ_TDM_HDLC,
 119                 .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
 120         }, {
 121                 .virq = SPEAR310_VIRQ_RS485_0,
 122                 .status_mask = SPEAR310_RS485_0_IRQ_MASK,
 123         }, {
 124                 .virq = SPEAR310_VIRQ_RS485_1,
 125                 .status_mask = SPEAR310_RS485_1_IRQ_MASK,
 126         },
 127 };
 128
 129 static struct spear_shirq shirq_intrcomm_ras = {
 130         .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
 131         .dev_config = shirq_intrcomm_ras_config,
 132         .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 133         .regs = {
 134                 .enb_reg = -1,
 135                 .status_reg = SPEAR310_INT_STS_MASK_REG,
 136                 .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
 137                 .clear_reg = -1,
 138         },
 139 };
 140
 141 /* DMAC platform data's slave info */
 142 struct pl08x_channel_data spear310_dma_info[] = {
 143         {
 144                 .bus_id = "uart0_rx",
 145                 .min_signal = 2,
 146                 .max_signal = 2,
 147                 .muxval = 0,
 148                 .cctl = 0,
 149                 .periph_buses = PL08X_AHB1,
 150         }, {
 151                 .bus_id = "uart0_tx",
 152                 .min_signal = 3,
 153                 .max_signal = 3,
 154                 .muxval = 0,
 155                 .cctl = 0,
 156                 .periph_buses = PL08X_AHB1,
 157         }, {
 158                 .bus_id = "ssp0_rx",
 159                 .min_signal = 8,
 160                 .max_signal = 8,
 161                 .muxval = 0,
 162                 .cctl = 0,
 163                 .periph_buses = PL08X_AHB1,
 164         }, {
 165                 .bus_id = "ssp0_tx",
 166                 .min_signal = 9,
 167                 .max_signal = 9,
 168                 .muxval = 0,
 169                 .cctl = 0,
 170                 .periph_buses = PL08X_AHB1,
 171         }, {
 172                 .bus_id = "i2c_rx",
 173                 .min_signal = 10,
 174                 .max_signal = 10,
 175                 .muxval = 0,
 176                 .cctl = 0,
 177                 .periph_buses = PL08X_AHB1,
 178         }, {
 179                 .bus_id = "i2c_tx",
 180                 .min_signal = 11,
 181                 .max_signal = 11,
 182                 .muxval = 0,
 183                 .cctl = 0,
 184                 .periph_buses = PL08X_AHB1,
 185         }, {
 186                 .bus_id = "irda",
 187                 .min_signal = 12,
 188                 .max_signal = 12,
 189                 .muxval = 0,
 190                 .cctl = 0,
 191                 .periph_buses = PL08X_AHB1,
 192         }, {
 193                 .bus_id = "adc",
 194                 .min_signal = 13,
 195                 .max_signal = 13,
 196                 .muxval = 0,
 197                 .cctl = 0,
 198                 .periph_buses = PL08X_AHB1,
 199         }, {
 200                 .bus_id = "to_jpeg",
 201                 .min_signal = 14,
 202                 .max_signal = 14,
 203                 .muxval = 0,
 204                 .cctl = 0,
 205                 .periph_buses = PL08X_AHB1,
 206         }, {
 207                 .bus_id = "from_jpeg",
 208                 .min_signal = 15,
 209                 .max_signal = 15,
 210                 .muxval = 0,
 211                 .cctl = 0,
 212                 .periph_buses = PL08X_AHB1,
 213         }, {
 214                 .bus_id = "uart1_rx",
 215                 .min_signal = 0,
 216                 .max_signal = 0,
 217                 .muxval = 1,
 218                 .cctl = 0,
 219                 .periph_buses = PL08X_AHB1,
 220         }, {
 221                 .bus_id = "uart1_tx",
 222                 .min_signal = 1,
 223                 .max_signal = 1,
 224                 .muxval = 1,
 225                 .cctl = 0,
 226                 .periph_buses = PL08X_AHB1,
 227         }, {
 228                 .bus_id = "uart2_rx",
 229                 .min_signal = 2,
 230                 .max_signal = 2,
 231                 .muxval = 1,
 232                 .cctl = 0,
 233                 .periph_buses = PL08X_AHB1,
 234         }, {
 235                 .bus_id = "uart2_tx",
 236                 .min_signal = 3,
 237                 .max_signal = 3,
 238                 .muxval = 1,
 239                 .cctl = 0,
 240                 .periph_buses = PL08X_AHB1,
 241         }, {
 242                 .bus_id = "uart3_rx",
 243                 .min_signal = 4,
 244                 .max_signal = 4,
 245                 .muxval = 1,
 246                 .cctl = 0,
 247                 .periph_buses = PL08X_AHB1,
 248         }, {
 249                 .bus_id = "uart3_tx",
 250                 .min_signal = 5,
 251                 .max_signal = 5,
 252                 .muxval = 1,
 253                 .cctl = 0,
 254                 .periph_buses = PL08X_AHB1,
 255         }, {
 256                 .bus_id = "uart4_rx",
 257                 .min_signal = 6,
 258                 .max_signal = 6,
 259                 .muxval = 1,
 260                 .cctl = 0,
 261                 .periph_buses = PL08X_AHB1,
 262         }, {
 263                 .bus_id = "uart4_tx",
 264                 .min_signal = 7,
 265                 .max_signal = 7,
 266                 .muxval = 1,
 267                 .cctl = 0,
 268                 .periph_buses = PL08X_AHB1,
 269         }, {
 270                 .bus_id = "uart5_rx",
 271                 .min_signal = 8,
 272                 .max_signal = 8,
 273                 .muxval = 1,
 274                 .cctl = 0,
 275                 .periph_buses = PL08X_AHB1,
 276         }, {
 277                 .bus_id = "uart5_tx",
 278                 .min_signal = 9,
 279                 .max_signal = 9,
 280                 .muxval = 1,
 281                 .cctl = 0,
 282                 .periph_buses = PL08X_AHB1,
 283         }, {
 284                 .bus_id = "ras5_rx",
 285                 .min_signal = 10,
 286                 .max_signal = 10,
 287                 .muxval = 1,
 288                 .cctl = 0,
 289                 .periph_buses = PL08X_AHB1,
 290         }, {
 291                 .bus_id = "ras5_tx",
 292                 .min_signal = 11,
 293                 .max_signal = 11,
 294                 .muxval = 1,
 295                 .cctl = 0,
 296                 .periph_buses = PL08X_AHB1,
 297         }, {
 298                 .bus_id = "ras6_rx",
 299                 .min_signal = 12,
 300                 .max_signal = 12,
 301                 .muxval = 1,
 302                 .cctl = 0,
 303                 .periph_buses = PL08X_AHB1,
 304         }, {
 305                 .bus_id = "ras6_tx",
 306                 .min_signal = 13,
 307                 .max_signal = 13,
 308                 .muxval = 1,
 309                 .cctl = 0,
 310                 .periph_buses = PL08X_AHB1,
 311         }, {
 312                 .bus_id = "ras7_rx",
 313                 .min_signal = 14,
 314                 .max_signal = 14,
 315                 .muxval = 1,
 316                 .cctl = 0,
 317                 .periph_buses = PL08X_AHB1,
 318         }, {
 319                 .bus_id = "ras7_tx",
 320                 .min_signal = 15,
 321                 .max_signal = 15,
 322                 .muxval = 1,
 323                 .cctl = 0,
 324                 .periph_buses = PL08X_AHB1,
 325         },
 326 };
 327
 328 /* uart devices plat data */
 329 static struct amba_pl011_data spear310_uart_data[] = {
 330         {
 331                 .dma_filter = pl08x_filter_id,
 332                 .dma_tx_param = "uart1_tx",
 333                 .dma_rx_param = "uart1_rx",
 334         }, {
 335                 .dma_filter = pl08x_filter_id,
 336                 .dma_tx_param = "uart2_tx",
 337                 .dma_rx_param = "uart2_rx",
 338         }, {
 339                 .dma_filter = pl08x_filter_id,
 340                 .dma_tx_param = "uart3_tx",
 341                 .dma_rx_param = "uart3_rx",
 342         }, {
 343                 .dma_filter = pl08x_filter_id,
 344                 .dma_tx_param = "uart4_tx",
 345                 .dma_rx_param = "uart4_rx",
 346         }, {
 347                 .dma_filter = pl08x_filter_id,
 348                 .dma_tx_param = "uart5_tx",
 349                 .dma_rx_param = "uart5_rx",
 350         },
 351 };
 352
 353 /* Add SPEAr310 auxdata to pass platform data */
 354 static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
 355         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
 356                         &pl022_plat_data),
 357         OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
 358                         &pl080_plat_data),
 359         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
 360                         &spear310_uart_data[0]),
 361         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
 362                         &spear310_uart_data[1]),
 363         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
 364                         &spear310_uart_data[2]),
 365         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
 366                         &spear310_uart_data[3]),
 367         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
 368                         &spear310_uart_data[4]),
 369         {}
 370 };
 371
 372 static void __init spear310_dt_init(void)
 373 {
 374         void __iomem *base;
 375         int ret;
 376
 377         pl080_plat_data.slave_channels = spear310_dma_info;
 378         pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
 379
 380         of_platform_populate(NULL, of_default_bus_match_table,
 381                         spear310_auxdata_lookup, NULL);
 382
 383         /* shared irq registration */
 384         base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
 385         if (base) {
 386                 /* shirq 1 */
 387                 shirq_ras1.regs.base = base;
 388                 ret = spear_shirq_register(&shirq_ras1);
 389                 if (ret)
 390                         pr_err("Error registering Shared IRQ 1\n");
 391
 392                 /* shirq 2 */
 393                 shirq_ras2.regs.base = base;
 394                 ret = spear_shirq_register(&shirq_ras2);
 395                 if (ret)
 396                         pr_err("Error registering Shared IRQ 2\n");
 397
 398                 /* shirq 3 */
 399                 shirq_ras3.regs.base = base;
 400                 ret = spear_shirq_register(&shirq_ras3);
 401                 if (ret)
 402                         pr_err("Error registering Shared IRQ 3\n");
 403
 404                 /* shirq 4 */
 405                 shirq_intrcomm_ras.regs.base = base;
 406                 ret = spear_shirq_register(&shirq_intrcomm_ras);
 407                 if (ret)
 408                         pr_err("Error registering Shared IRQ 4\n");
 409         }
 410 }
 411
 412 static const char * const spear310_dt_board_compat[] = {
 413         "st,spear310",
 414         "st,spear310-evb",
 415         NULL,
 416 };
 417
 418 static void __init spear310_map_io(void)
 419 {
 420         spear3xx_map_io();
 421         spear310_clk_init();
 422 }
 423
 424 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
 425         .map_io         =       spear310_map_io,
 426         .init_irq       =       spear3xx_dt_init_irq,
 427         .handle_irq     =       vic_handle_irq,
 428         .timer          =       &spear3xx_timer,
 429         .init_machine   =       spear310_dt_init,
 430         .restart        =       spear_restart,
 431         .dt_compat      =       spear310_dt_board_compat,
 432 MACHINE_END