Pileus Git - ~andy/linux/blob - arch/arm/mach-spear3xx/spear300.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear300.c
   3  *
   4  * SPEAr300 machine source file
   5  *
   6  * Copyright (C) 2009-2012 ST Microelectronics
   7  * Viresh Kumar <viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr300: " fmt
  15
  16 #include <linux/amba/pl08x.h>
  17 #include <linux/of_platform.h>
  18 #include <asm/hardware/vic.h>
  19 #include <asm/mach/arch.h>
  20 #include <plat/shirq.h>
  21 #include <mach/generic.h>
  22 #include <mach/spear.h>
  23
  24 /* Base address of various IPs */
  25 #define SPEAR300_TELECOM_BASE           UL(0x50000000)
  26
  27 /* Interrupt registers offsets and masks */
  28 #define SPEAR300_INT_ENB_MASK_REG       0x54
  29 #define SPEAR300_INT_STS_MASK_REG       0x58
  30 #define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
  31 #define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
  32 #define SPEAR300_I2S_IRQ_MASK           (1 << 2)
  33 #define SPEAR300_TDM_IRQ_MASK           (1 << 3)
  34 #define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
  35 #define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
  36 #define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
  37 #define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
  38 #define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
  39
  40 #define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
  41
  42 #define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
  43
  44
  45 /* SPEAr300 Virtual irq definitions */
  46 /* IRQs sharing IRQ_GEN_RAS_1 */
  47 #define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
  48 #define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
  49 #define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
  50 #define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
  51 #define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
  52 #define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
  53 #define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
  54 #define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
  55 #define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
  56
  57 /* IRQs sharing IRQ_GEN_RAS_3 */
  58 #define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
  59
  60 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
  61 #define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
  62
  63 /* pad multiplexing support */
  64 /* muxing registers */
  65 #define PAD_MUX_CONFIG_REG      0x00
  66 #define MODE_CONFIG_REG         0x04
  67
  68 /* modes */
  69 #define NAND_MODE                       (1 << 0)
  70 #define NOR_MODE                        (1 << 1)
  71 #define PHOTO_FRAME_MODE                (1 << 2)
  72 #define LEND_IP_PHONE_MODE              (1 << 3)
  73 #define HEND_IP_PHONE_MODE              (1 << 4)
  74 #define LEND_WIFI_PHONE_MODE            (1 << 5)
  75 #define HEND_WIFI_PHONE_MODE            (1 << 6)
  76 #define ATA_PABX_WI2S_MODE              (1 << 7)
  77 #define ATA_PABX_I2S_MODE               (1 << 8)
  78 #define CAML_LCDW_MODE                  (1 << 9)
  79 #define CAMU_LCD_MODE                   (1 << 10)
  80 #define CAMU_WLCD_MODE                  (1 << 11)
  81 #define CAML_LCD_MODE                   (1 << 12)
  82 #define ALL_MODES                       0x1FFF
  83
  84 struct pmx_mode spear300_nand_mode = {
  85         .id = NAND_MODE,
  86         .name = "nand mode",
  87         .mask = 0x00,
  88 };
  89
  90 struct pmx_mode spear300_nor_mode = {
  91         .id = NOR_MODE,
  92         .name = "nor mode",
  93         .mask = 0x01,
  94 };
  95
  96 struct pmx_mode spear300_photo_frame_mode = {
  97         .id = PHOTO_FRAME_MODE,
  98         .name = "photo frame mode",
  99         .mask = 0x02,
 100 };
 101
 102 struct pmx_mode spear300_lend_ip_phone_mode = {
 103         .id = LEND_IP_PHONE_MODE,
 104         .name = "lend ip phone mode",
 105         .mask = 0x03,
 106 };
 107
 108 struct pmx_mode spear300_hend_ip_phone_mode = {
 109         .id = HEND_IP_PHONE_MODE,
 110         .name = "hend ip phone mode",
 111         .mask = 0x04,
 112 };
 113
 114 struct pmx_mode spear300_lend_wifi_phone_mode = {
 115         .id = LEND_WIFI_PHONE_MODE,
 116         .name = "lend wifi phone mode",
 117         .mask = 0x05,
 118 };
 119
 120 struct pmx_mode spear300_hend_wifi_phone_mode = {
 121         .id = HEND_WIFI_PHONE_MODE,
 122         .name = "hend wifi phone mode",
 123         .mask = 0x06,
 124 };
 125
 126 struct pmx_mode spear300_ata_pabx_wi2s_mode = {
 127         .id = ATA_PABX_WI2S_MODE,
 128         .name = "ata pabx wi2s mode",
 129         .mask = 0x07,
 130 };
 131
 132 struct pmx_mode spear300_ata_pabx_i2s_mode = {
 133         .id = ATA_PABX_I2S_MODE,
 134         .name = "ata pabx i2s mode",
 135         .mask = 0x08,
 136 };
 137
 138 struct pmx_mode spear300_caml_lcdw_mode = {
 139         .id = CAML_LCDW_MODE,
 140         .name = "caml lcdw mode",
 141         .mask = 0x0C,
 142 };
 143
 144 struct pmx_mode spear300_camu_lcd_mode = {
 145         .id = CAMU_LCD_MODE,
 146         .name = "camu lcd mode",
 147         .mask = 0x0D,
 148 };
 149
 150 struct pmx_mode spear300_camu_wlcd_mode = {
 151         .id = CAMU_WLCD_MODE,
 152         .name = "camu wlcd mode",
 153         .mask = 0x0E,
 154 };
 155
 156 struct pmx_mode spear300_caml_lcd_mode = {
 157         .id = CAML_LCD_MODE,
 158         .name = "caml lcd mode",
 159         .mask = 0x0F,
 160 };
 161
 162 /* devices */
 163 static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
 164         {
 165                 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
 166                         ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
 167                 .mask = PMX_FIRDA_MASK,
 168         },
 169 };
 170
 171 struct pmx_dev spear300_pmx_fsmc_2_chips = {
 172         .name = "fsmc_2_chips",
 173         .modes = pmx_fsmc_2_chips_modes,
 174         .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
 175         .enb_on_reset = 1,
 176 };
 177
 178 static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
 179         {
 180                 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
 181                         ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
 182                 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
 183         },
 184 };
 185
 186 struct pmx_dev spear300_pmx_fsmc_4_chips = {
 187         .name = "fsmc_4_chips",
 188         .modes = pmx_fsmc_4_chips_modes,
 189         .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
 190         .enb_on_reset = 1,
 191 };
 192
 193 static struct pmx_dev_mode pmx_keyboard_modes[] = {
 194         {
 195                 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
 196                         LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
 197                         CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
 198                         CAML_LCD_MODE,
 199                 .mask = 0x0,
 200         },
 201 };
 202
 203 struct pmx_dev spear300_pmx_keyboard = {
 204         .name = "keyboard",
 205         .modes = pmx_keyboard_modes,
 206         .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
 207         .enb_on_reset = 1,
 208 };
 209
 210 static struct pmx_dev_mode pmx_clcd_modes[] = {
 211         {
 212                 .ids = PHOTO_FRAME_MODE,
 213                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
 214         }, {
 215                 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
 216                         CAMU_LCD_MODE | CAML_LCD_MODE,
 217                 .mask = PMX_TIMER_3_4_MASK,
 218         },
 219 };
 220
 221 struct pmx_dev spear300_pmx_clcd = {
 222         .name = "clcd",
 223         .modes = pmx_clcd_modes,
 224         .mode_count = ARRAY_SIZE(pmx_clcd_modes),
 225         .enb_on_reset = 1,
 226 };
 227
 228 static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
 229         {
 230                 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
 231                 .mask = PMX_MII_MASK,
 232         }, {
 233                 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
 234                 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
 235         }, {
 236                 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
 237                 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
 238         }, {
 239                 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
 240                 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
 241         }, {
 242                 .ids = ATA_PABX_WI2S_MODE,
 243                 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
 244                         | PMX_UART0_MODEM_MASK,
 245         },
 246 };
 247
 248 struct pmx_dev spear300_pmx_telecom_gpio = {
 249         .name = "telecom_gpio",
 250         .modes = pmx_telecom_gpio_modes,
 251         .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
 252         .enb_on_reset = 1,
 253 };
 254
 255 static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
 256         {
 257                 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
 258                         HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
 259                         | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
 260                         | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
 261                         | CAMU_WLCD_MODE | CAML_LCD_MODE,
 262                 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
 263         },
 264 };
 265
 266 struct pmx_dev spear300_pmx_telecom_tdm = {
 267         .name = "telecom_tdm",
 268         .modes = pmx_telecom_tdm_modes,
 269         .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
 270         .enb_on_reset = 1,
 271 };
 272
 273 static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
 274         {
 275                 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
 276                         LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
 277                         | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
 278                         CAML_LCDW_MODE | CAML_LCD_MODE,
 279                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
 280         },
 281 };
 282
 283 struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
 284         .name = "telecom_spi_cs_i2c_clk",
 285         .modes = pmx_telecom_spi_cs_i2c_clk_modes,
 286         .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
 287         .enb_on_reset = 1,
 288 };
 289
 290 static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
 291         {
 292                 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
 293                 .mask = PMX_MII_MASK,
 294         }, {
 295                 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
 296                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
 297         },
 298 };
 299
 300 struct pmx_dev spear300_pmx_telecom_camera = {
 301         .name = "telecom_camera",
 302         .modes = pmx_telecom_camera_modes,
 303         .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
 304         .enb_on_reset = 1,
 305 };
 306
 307 static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
 308         {
 309                 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
 310                         | CAMU_WLCD_MODE | CAML_LCD_MODE,
 311                 .mask = PMX_TIMER_1_2_MASK,
 312         },
 313 };
 314
 315 struct pmx_dev spear300_pmx_telecom_dac = {
 316         .name = "telecom_dac",
 317         .modes = pmx_telecom_dac_modes,
 318         .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
 319         .enb_on_reset = 1,
 320 };
 321
 322 static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
 323         {
 324                 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
 325                         | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
 326                         ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
 327                         | CAMU_WLCD_MODE | CAML_LCD_MODE,
 328                 .mask = PMX_UART0_MODEM_MASK,
 329         },
 330 };
 331
 332 struct pmx_dev spear300_pmx_telecom_i2s = {
 333         .name = "telecom_i2s",
 334         .modes = pmx_telecom_i2s_modes,
 335         .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
 336         .enb_on_reset = 1,
 337 };
 338
 339 static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
 340         {
 341                 .ids = NAND_MODE | NOR_MODE,
 342                 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
 343                         PMX_TIMER_3_4_MASK,
 344         },
 345 };
 346
 347 struct pmx_dev spear300_pmx_telecom_boot_pins = {
 348         .name = "telecom_boot_pins",
 349         .modes = pmx_telecom_boot_pins_modes,
 350         .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
 351         .enb_on_reset = 1,
 352 };
 353
 354 static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
 355         {
 356                 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
 357                         HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
 358                         HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
 359                         CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
 360                         ATA_PABX_I2S_MODE,
 361                 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
 362                         PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
 363                         PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
 364         },
 365 };
 366
 367 struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
 368         .name = "telecom_sdhci_4bit",
 369         .modes = pmx_telecom_sdhci_4bit_modes,
 370         .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
 371         .enb_on_reset = 1,
 372 };
 373
 374 static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
 375         {
 376                 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
 377                         HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
 378                         HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
 379                         CAMU_WLCD_MODE | CAML_LCD_MODE,
 380                 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
 381                         PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
 382                         PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
 383         },
 384 };
 385
 386 struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
 387         .name = "telecom_sdhci_8bit",
 388         .modes = pmx_telecom_sdhci_8bit_modes,
 389         .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
 390         .enb_on_reset = 1,
 391 };
 392
 393 static struct pmx_dev_mode pmx_gpio1_modes[] = {
 394         {
 395                 .ids = PHOTO_FRAME_MODE,
 396                 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
 397                         PMX_TIMER_3_4_MASK,
 398         },
 399 };
 400
 401 struct pmx_dev spear300_pmx_gpio1 = {
 402         .name = "arm gpio1",
 403         .modes = pmx_gpio1_modes,
 404         .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
 405         .enb_on_reset = 1,
 406 };
 407
 408 /* pmx driver structure */
 409 static struct pmx_driver pmx_driver = {
 410         .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
 411         .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 412 };
 413
 414 /* spear3xx shared irq */
 415 static struct shirq_dev_config shirq_ras1_config[] = {
 416         {
 417                 .virq = SPEAR300_VIRQ_IT_PERS_S,
 418                 .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
 419                 .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
 420         }, {
 421                 .virq = SPEAR300_VIRQ_IT_CHANGE_S,
 422                 .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
 423                 .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
 424         }, {
 425                 .virq = SPEAR300_VIRQ_I2S,
 426                 .enb_mask = SPEAR300_I2S_IRQ_MASK,
 427                 .status_mask = SPEAR300_I2S_IRQ_MASK,
 428         }, {
 429                 .virq = SPEAR300_VIRQ_TDM,
 430                 .enb_mask = SPEAR300_TDM_IRQ_MASK,
 431                 .status_mask = SPEAR300_TDM_IRQ_MASK,
 432         }, {
 433                 .virq = SPEAR300_VIRQ_CAMERA_L,
 434                 .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
 435                 .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
 436         }, {
 437                 .virq = SPEAR300_VIRQ_CAMERA_F,
 438                 .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
 439                 .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
 440         }, {
 441                 .virq = SPEAR300_VIRQ_CAMERA_V,
 442                 .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
 443                 .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
 444         }, {
 445                 .virq = SPEAR300_VIRQ_KEYBOARD,
 446                 .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
 447                 .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
 448         }, {
 449                 .virq = SPEAR300_VIRQ_GPIO1,
 450                 .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
 451                 .status_mask = SPEAR300_GPIO1_IRQ_MASK,
 452         },
 453 };
 454
 455 static struct spear_shirq shirq_ras1 = {
 456         .irq = SPEAR3XX_IRQ_GEN_RAS_1,
 457         .dev_config = shirq_ras1_config,
 458         .dev_count = ARRAY_SIZE(shirq_ras1_config),
 459         .regs = {
 460                 .enb_reg = SPEAR300_INT_ENB_MASK_REG,
 461                 .status_reg = SPEAR300_INT_STS_MASK_REG,
 462                 .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
 463                 .clear_reg = -1,
 464         },
 465 };
 466
 467 /* padmux devices to enable */
 468 static struct pmx_dev *spear300_evb_pmx_devs[] = {
 469         /* spear3xx specific devices */
 470         &spear3xx_pmx_i2c,
 471         &spear3xx_pmx_ssp_cs,
 472         &spear3xx_pmx_ssp,
 473         &spear3xx_pmx_mii,
 474         &spear3xx_pmx_uart0,
 475
 476         /* spear300 specific devices */
 477         &spear300_pmx_fsmc_2_chips,
 478         &spear300_pmx_clcd,
 479         &spear300_pmx_telecom_sdhci_4bit,
 480         &spear300_pmx_gpio1,
 481 };
 482
 483 /* DMAC platform data's slave info */
 484 struct pl08x_channel_data spear300_dma_info[] = {
 485         {
 486                 .bus_id = "uart0_rx",
 487                 .min_signal = 2,
 488                 .max_signal = 2,
 489                 .muxval = 0,
 490                 .cctl = 0,
 491                 .periph_buses = PL08X_AHB1,
 492         }, {
 493                 .bus_id = "uart0_tx",
 494                 .min_signal = 3,
 495                 .max_signal = 3,
 496                 .muxval = 0,
 497                 .cctl = 0,
 498                 .periph_buses = PL08X_AHB1,
 499         }, {
 500                 .bus_id = "ssp0_rx",
 501                 .min_signal = 8,
 502                 .max_signal = 8,
 503                 .muxval = 0,
 504                 .cctl = 0,
 505                 .periph_buses = PL08X_AHB1,
 506         }, {
 507                 .bus_id = "ssp0_tx",
 508                 .min_signal = 9,
 509                 .max_signal = 9,
 510                 .muxval = 0,
 511                 .cctl = 0,
 512                 .periph_buses = PL08X_AHB1,
 513         }, {
 514                 .bus_id = "i2c_rx",
 515                 .min_signal = 10,
 516                 .max_signal = 10,
 517                 .muxval = 0,
 518                 .cctl = 0,
 519                 .periph_buses = PL08X_AHB1,
 520         }, {
 521                 .bus_id = "i2c_tx",
 522                 .min_signal = 11,
 523                 .max_signal = 11,
 524                 .muxval = 0,
 525                 .cctl = 0,
 526                 .periph_buses = PL08X_AHB1,
 527         }, {
 528                 .bus_id = "irda",
 529                 .min_signal = 12,
 530                 .max_signal = 12,
 531                 .muxval = 0,
 532                 .cctl = 0,
 533                 .periph_buses = PL08X_AHB1,
 534         }, {
 535                 .bus_id = "adc",
 536                 .min_signal = 13,
 537                 .max_signal = 13,
 538                 .muxval = 0,
 539                 .cctl = 0,
 540                 .periph_buses = PL08X_AHB1,
 541         }, {
 542                 .bus_id = "to_jpeg",
 543                 .min_signal = 14,
 544                 .max_signal = 14,
 545                 .muxval = 0,
 546                 .cctl = 0,
 547                 .periph_buses = PL08X_AHB1,
 548         }, {
 549                 .bus_id = "from_jpeg",
 550                 .min_signal = 15,
 551                 .max_signal = 15,
 552                 .muxval = 0,
 553                 .cctl = 0,
 554                 .periph_buses = PL08X_AHB1,
 555         }, {
 556                 .bus_id = "ras0_rx",
 557                 .min_signal = 0,
 558                 .max_signal = 0,
 559                 .muxval = 1,
 560                 .cctl = 0,
 561                 .periph_buses = PL08X_AHB1,
 562         }, {
 563                 .bus_id = "ras0_tx",
 564                 .min_signal = 1,
 565                 .max_signal = 1,
 566                 .muxval = 1,
 567                 .cctl = 0,
 568                 .periph_buses = PL08X_AHB1,
 569         }, {
 570                 .bus_id = "ras1_rx",
 571                 .min_signal = 2,
 572                 .max_signal = 2,
 573                 .muxval = 1,
 574                 .cctl = 0,
 575                 .periph_buses = PL08X_AHB1,
 576         }, {
 577                 .bus_id = "ras1_tx",
 578                 .min_signal = 3,
 579                 .max_signal = 3,
 580                 .muxval = 1,
 581                 .cctl = 0,
 582                 .periph_buses = PL08X_AHB1,
 583         }, {
 584                 .bus_id = "ras2_rx",
 585                 .min_signal = 4,
 586                 .max_signal = 4,
 587                 .muxval = 1,
 588                 .cctl = 0,
 589                 .periph_buses = PL08X_AHB1,
 590         }, {
 591                 .bus_id = "ras2_tx",
 592                 .min_signal = 5,
 593                 .max_signal = 5,
 594                 .muxval = 1,
 595                 .cctl = 0,
 596                 .periph_buses = PL08X_AHB1,
 597         }, {
 598                 .bus_id = "ras3_rx",
 599                 .min_signal = 6,
 600                 .max_signal = 6,
 601                 .muxval = 1,
 602                 .cctl = 0,
 603                 .periph_buses = PL08X_AHB1,
 604         }, {
 605                 .bus_id = "ras3_tx",
 606                 .min_signal = 7,
 607                 .max_signal = 7,
 608                 .muxval = 1,
 609                 .cctl = 0,
 610                 .periph_buses = PL08X_AHB1,
 611         }, {
 612                 .bus_id = "ras4_rx",
 613                 .min_signal = 8,
 614                 .max_signal = 8,
 615                 .muxval = 1,
 616                 .cctl = 0,
 617                 .periph_buses = PL08X_AHB1,
 618         }, {
 619                 .bus_id = "ras4_tx",
 620                 .min_signal = 9,
 621                 .max_signal = 9,
 622                 .muxval = 1,
 623                 .cctl = 0,
 624                 .periph_buses = PL08X_AHB1,
 625         }, {
 626                 .bus_id = "ras5_rx",
 627                 .min_signal = 10,
 628                 .max_signal = 10,
 629                 .muxval = 1,
 630                 .cctl = 0,
 631                 .periph_buses = PL08X_AHB1,
 632         }, {
 633                 .bus_id = "ras5_tx",
 634                 .min_signal = 11,
 635                 .max_signal = 11,
 636                 .muxval = 1,
 637                 .cctl = 0,
 638                 .periph_buses = PL08X_AHB1,
 639         }, {
 640                 .bus_id = "ras6_rx",
 641                 .min_signal = 12,
 642                 .max_signal = 12,
 643                 .muxval = 1,
 644                 .cctl = 0,
 645                 .periph_buses = PL08X_AHB1,
 646         }, {
 647                 .bus_id = "ras6_tx",
 648                 .min_signal = 13,
 649                 .max_signal = 13,
 650                 .muxval = 1,
 651                 .cctl = 0,
 652                 .periph_buses = PL08X_AHB1,
 653         }, {
 654                 .bus_id = "ras7_rx",
 655                 .min_signal = 14,
 656                 .max_signal = 14,
 657                 .muxval = 1,
 658                 .cctl = 0,
 659                 .periph_buses = PL08X_AHB1,
 660         }, {
 661                 .bus_id = "ras7_tx",
 662                 .min_signal = 15,
 663                 .max_signal = 15,
 664                 .muxval = 1,
 665                 .cctl = 0,
 666                 .periph_buses = PL08X_AHB1,
 667         },
 668 };
 669
 670 /* Add SPEAr300 auxdata to pass platform data */
 671 static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
 672         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
 673                         &pl022_plat_data),
 674         OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
 675                         &pl080_plat_data),
 676         {}
 677 };
 678
 679 static void __init spear300_dt_init(void)
 680 {
 681         int ret = -EINVAL;
 682
 683         pl080_plat_data.slave_channels = spear300_dma_info;
 684         pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
 685
 686         of_platform_populate(NULL, of_default_bus_match_table,
 687                         spear300_auxdata_lookup, NULL);
 688
 689         /* shared irq registration */
 690         shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
 691         if (shirq_ras1.regs.base) {
 692                 ret = spear_shirq_register(&shirq_ras1);
 693                 if (ret)
 694                         pr_err("Error registering Shared IRQ\n");
 695         }
 696
 697         if (of_machine_is_compatible("st,spear300-evb")) {
 698                 /* pmx initialization */
 699                 pmx_driver.mode = &spear300_photo_frame_mode;
 700                 pmx_driver.devs = spear300_evb_pmx_devs;
 701                 pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
 702
 703                 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
 704                 if (pmx_driver.base) {
 705                         ret = pmx_register(&pmx_driver);
 706                         if (ret)
 707                                 pr_err("padmux: registration failed. err no: %d\n",
 708                                                 ret);
 709                         /* Free Mapping, device selection already done */
 710                         iounmap(pmx_driver.base);
 711                 }
 712
 713                 if (ret)
 714                         pr_err("Initialization Failed");
 715         }
 716 }
 717
 718 static const char * const spear300_dt_board_compat[] = {
 719         "st,spear300",
 720         "st,spear300-evb",
 721         NULL,
 722 };
 723
 724 static void __init spear300_map_io(void)
 725 {
 726         spear3xx_map_io();
 727         spear300_clk_init();
 728 }
 729
 730 DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
 731         .map_io         =       spear300_map_io,
 732         .init_irq       =       spear3xx_dt_init_irq,
 733         .handle_irq     =       vic_handle_irq,
 734         .timer          =       &spear3xx_timer,
 735         .init_machine   =       spear300_dt_init,
 736         .restart        =       spear_restart,
 737         .dt_compat      =       spear300_dt_board_compat,
 738 MACHINE_END