Pileus Git - ~andy/linux/blob - arch/arm/mach-spear13xx/spear13xx.c

   1 /*
   2  * arch/arm/mach-spear13xx/spear13xx.c
   3  *
   4  * SPEAr13XX machines common source file
   5  *
   6  * Copyright (C) 2012 ST Microelectronics
   7  * Viresh Kumar <viresh.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr13xx: " fmt
  15
  16 #include <linux/amba/pl022.h>
  17 #include <linux/clk.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/dw_dmac.h>
  20 #include <linux/err.h>
  21 #include <linux/of.h>
  22 #include <asm/hardware/cache-l2x0.h>
  23 #include <asm/mach/map.h>
  24 #include <mach/dma.h>
  25 #include <mach/generic.h>
  26 #include <mach/spear.h>
  27
  28 /* common dw_dma filter routine to be used by peripherals */
  29 bool dw_dma_filter(struct dma_chan *chan, void *slave)
  30 {
  31         struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
  32
  33         if (chan->device->dev == dws->dma_dev) {
  34                 chan->private = slave;
  35                 return true;
  36         } else {
  37                 return false;
  38         }
  39 }
  40
  41 /* ssp device registration */
  42 static struct dw_dma_slave ssp_dma_param[] = {
  43         {
  44                 /* Tx */
  45                 .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
  46                 .cfg_lo = 0,
  47                 .src_master = DMA_MASTER_MEMORY,
  48                 .dst_master = DMA_MASTER_SSP0,
  49         }, {
  50                 /* Rx */
  51                 .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
  52                 .cfg_lo = 0,
  53                 .src_master = DMA_MASTER_SSP0,
  54                 .dst_master = DMA_MASTER_MEMORY,
  55         }
  56 };
  57
  58 struct pl022_ssp_controller pl022_plat_data = {
  59         .enable_dma = 1,
  60         .dma_filter = dw_dma_filter,
  61         .dma_rx_param = &ssp_dma_param[1],
  62         .dma_tx_param = &ssp_dma_param[0],
  63 };
  64
  65 /* CF device registration */
  66 struct dw_dma_slave cf_dma_priv = {
  67         .cfg_hi = 0,
  68         .cfg_lo = 0,
  69         .src_master = 0,
  70         .dst_master = 0,
  71 };
  72
  73 /* dmac device registeration */
  74 struct dw_dma_platform_data dmac_plat_data = {
  75         .nr_channels = 8,
  76         .chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
  77         .chan_priority = CHAN_PRIORITY_DESCENDING,
  78         .block_size = 4095U,
  79         .nr_masters = 2,
  80         .data_width = { 3, 3, 0, 0 },
  81 };
  82
  83 void __init spear13xx_l2x0_init(void)
  84 {
  85         /*
  86          * 512KB (64KB/way), 8-way associativity, parity supported
  87          *
  88          * FIXME: 9th bit, of Auxillary Controller register must be set
  89          * for some spear13xx devices for stable L2 operation.
  90          *
  91          * Enable Early BRESP, L2 prefetch for Instruction and Data,
  92          * write alloc and 'Full line of zero' options
  93          *
  94          */
  95
  96         writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
  97
  98         /*
  99          * Program following latencies in order to make
 100          * SPEAr1340 work at 600 MHz
 101          */
 102         writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
 103         writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
 104         l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
 105 }
 106
 107 /*
 108  * Following will create 16MB static virtual/physical mappings
 109  * PHYSICAL             VIRTUAL
 110  * 0xB3000000           0xFE000000
 111  * 0xE0000000           0xFD000000
 112  * 0xEC000000           0xFC000000
 113  * 0xED000000           0xFB000000
 114  */
 115 struct map_desc spear13xx_io_desc[] __initdata = {
 116         {
 117                 .virtual        = (unsigned long)VA_PERIP_GRP2_BASE,
 118                 .pfn            = __phys_to_pfn(PERIP_GRP2_BASE),
 119                 .length         = SZ_16M,
 120                 .type           = MT_DEVICE
 121         }, {
 122                 .virtual        = (unsigned long)VA_PERIP_GRP1_BASE,
 123                 .pfn            = __phys_to_pfn(PERIP_GRP1_BASE),
 124                 .length         = SZ_16M,
 125                 .type           = MT_DEVICE
 126         }, {
 127                 .virtual        = (unsigned long)VA_A9SM_AND_MPMC_BASE,
 128                 .pfn            = __phys_to_pfn(A9SM_AND_MPMC_BASE),
 129                 .length         = SZ_16M,
 130                 .type           = MT_DEVICE
 131         }, {
 132                 .virtual        = (unsigned long)VA_L2CC_BASE,
 133                 .pfn            = __phys_to_pfn(L2CC_BASE),
 134                 .length         = SZ_4K,
 135                 .type           = MT_DEVICE
 136         },
 137 };
 138
 139 /* This will create static memory mapping for selected devices */
 140 void __init spear13xx_map_io(void)
 141 {
 142         iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
 143 }
 144
 145 static void __init spear13xx_clk_init(void)
 146 {
 147         if (of_machine_is_compatible("st,spear1310"))
 148                 spear1310_clk_init();
 149         else if (of_machine_is_compatible("st,spear1340"))
 150                 spear1340_clk_init();
 151         else
 152                 pr_err("%s: Unknown machine\n", __func__);
 153 }
 154
 155 void __init spear13xx_timer_init(void)
 156 {
 157         char pclk_name[] = "osc_24m_clk";
 158         struct clk *gpt_clk, *pclk;
 159
 160         spear13xx_clk_init();
 161
 162         /* get the system timer clock */
 163         gpt_clk = clk_get_sys("gpt0", NULL);
 164         if (IS_ERR(gpt_clk)) {
 165                 pr_err("%s:couldn't get clk for gpt\n", __func__);
 166                 BUG();
 167         }
 168
 169         /* get the suitable parent clock for timer*/
 170         pclk = clk_get(NULL, pclk_name);
 171         if (IS_ERR(pclk)) {
 172                 pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
 173                                 pclk_name);
 174                 BUG();
 175         }
 176
 177         clk_set_parent(gpt_clk, pclk);
 178         clk_put(gpt_clk);
 179         clk_put(pclk);
 180
 181         spear_setup_of_timer();
 182         clocksource_of_init();
 183 }