2 * SMP support for R-Mobile / SH-Mobile - sh73a0 portion
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Takashi Yoshii
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/smp.h>
23 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <mach/common.h>
28 #include <asm/cacheflush.h>
29 #include <asm/smp_plat.h>
30 #include <mach/sh73a0.h>
31 #include <asm/smp_scu.h>
32 #include <asm/smp_twd.h>
34 #define WUPCR IOMEM(0xe6151010)
35 #define SRESCR IOMEM(0xe6151018)
36 #define PSTR IOMEM(0xe6151040)
37 #define SBAR IOMEM(0xe6180020)
38 #define APARMBAREA IOMEM(0xe6f10020)
40 #define PSTR_SHUTDOWN_MODE 3
42 #define SH73A0_SCU_BASE 0xf0000000
44 #ifdef CONFIG_HAVE_ARM_TWD
45 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
46 void __init sh73a0_register_twd(void)
48 twd_local_timer_register(&twd_local_timer);
52 static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
54 gic_secondary_init(0);
57 static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
59 cpu = cpu_logical_map(cpu);
61 if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
62 __raw_writel(1 << cpu, WUPCR); /* wake up */
64 __raw_writel(1 << cpu, SRESCR); /* reset */
69 static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
71 scu_enable(shmobile_scu_base);
73 /* Map the reset vector (in headsmp-scu.S) */
74 __raw_writel(0, APARMBAREA); /* 4k */
75 __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
77 /* enable cache coherency on booting CPU */
78 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
81 static void __init sh73a0_smp_init_cpus(void)
83 /* setup sh73a0 specific SCU base */
84 shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
86 shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
89 #ifdef CONFIG_HOTPLUG_CPU
90 static int sh73a0_cpu_kill(unsigned int cpu)
97 * wait until the power status register confirms the shutdown of the
100 for (k = 0; k < 1000; k++) {
101 pstr = (__raw_readl(PSTR) >> (4 * cpu)) & 3;
102 if (pstr == PSTR_SHUTDOWN_MODE)
111 static void sh73a0_cpu_die(unsigned int cpu)
114 * The ARM MPcore does not issue a cache coherency request for the L1
115 * cache when powering off single CPUs. We must take care of this and
121 /* Set power off mode. This takes the CPU out of the MP cluster */
122 scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
124 /* Enter shutdown mode */
128 static int sh73a0_cpu_disable(unsigned int cpu)
130 return 0; /* CPU0 and CPU1 supported */
132 #endif /* CONFIG_HOTPLUG_CPU */
134 struct smp_operations sh73a0_smp_ops __initdata = {
135 .smp_init_cpus = sh73a0_smp_init_cpus,
136 .smp_prepare_cpus = sh73a0_smp_prepare_cpus,
137 .smp_secondary_init = sh73a0_secondary_init,
138 .smp_boot_secondary = sh73a0_boot_secondary,
139 #ifdef CONFIG_HOTPLUG_CPU
140 .cpu_kill = sh73a0_cpu_kill,
141 .cpu_die = sh73a0_cpu_die,
142 .cpu_disable = sh73a0_cpu_disable,