Pileus Git - ~andy/linux/blob - arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uio_driver.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/pm_domain.h>
  34 #include <linux/dma-mapping.h>
  35 #include <mach/hardware.h>
  36 #include <mach/irqs.h>
  37 #include <mach/sh7372.h>
  38 #include <mach/common.h>
  39 #include <asm/mach/map.h>
  40 #include <asm/mach-types.h>
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/time.h>
  43
  44 static struct map_desc sh7372_io_desc[] __initdata = {
  45         /* create a 1:1 entity map for 0xe6xxxxxx
  46          * used by CPGA, INTC and PFC.
  47          */
  48         {
  49                 .virtual        = 0xe6000000,
  50                 .pfn            = __phys_to_pfn(0xe6000000),
  51                 .length         = 256 << 20,
  52                 .type           = MT_DEVICE_NONSHARED
  53         },
  54 };
  55
  56 void __init sh7372_map_io(void)
  57 {
  58         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  59
  60         /*
  61          * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
  62          * enough to allocate the frame buffer memory.
  63          */
  64         init_consistent_dma_size(12 << 20);
  65 }
  66
  67 /* SCIFA0 */
  68 static struct plat_sci_port scif0_platform_data = {
  69         .mapbase        = 0xe6c40000,
  70         .flags          = UPF_BOOT_AUTOCONF,
  71         .scscr          = SCSCR_RE | SCSCR_TE,
  72         .scbrr_algo_id  = SCBRR_ALGO_4,
  73         .type           = PORT_SCIFA,
  74         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  75                             evt2irq(0x0c00), evt2irq(0x0c00) },
  76 };
  77
  78 static struct platform_device scif0_device = {
  79         .name           = "sh-sci",
  80         .id             = 0,
  81         .dev            = {
  82                 .platform_data  = &scif0_platform_data,
  83         },
  84 };
  85
  86 /* SCIFA1 */
  87 static struct plat_sci_port scif1_platform_data = {
  88         .mapbase        = 0xe6c50000,
  89         .flags          = UPF_BOOT_AUTOCONF,
  90         .scscr          = SCSCR_RE | SCSCR_TE,
  91         .scbrr_algo_id  = SCBRR_ALGO_4,
  92         .type           = PORT_SCIFA,
  93         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  94                             evt2irq(0x0c20), evt2irq(0x0c20) },
  95 };
  96
  97 static struct platform_device scif1_device = {
  98         .name           = "sh-sci",
  99         .id             = 1,
 100         .dev            = {
 101                 .platform_data  = &scif1_platform_data,
 102         },
 103 };
 104
 105 /* SCIFA2 */
 106 static struct plat_sci_port scif2_platform_data = {
 107         .mapbase        = 0xe6c60000,
 108         .flags          = UPF_BOOT_AUTOCONF,
 109         .scscr          = SCSCR_RE | SCSCR_TE,
 110         .scbrr_algo_id  = SCBRR_ALGO_4,
 111         .type           = PORT_SCIFA,
 112         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
 113                             evt2irq(0x0c40), evt2irq(0x0c40) },
 114 };
 115
 116 static struct platform_device scif2_device = {
 117         .name           = "sh-sci",
 118         .id             = 2,
 119         .dev            = {
 120                 .platform_data  = &scif2_platform_data,
 121         },
 122 };
 123
 124 /* SCIFA3 */
 125 static struct plat_sci_port scif3_platform_data = {
 126         .mapbase        = 0xe6c70000,
 127         .flags          = UPF_BOOT_AUTOCONF,
 128         .scscr          = SCSCR_RE | SCSCR_TE,
 129         .scbrr_algo_id  = SCBRR_ALGO_4,
 130         .type           = PORT_SCIFA,
 131         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 132                             evt2irq(0x0c60), evt2irq(0x0c60) },
 133 };
 134
 135 static struct platform_device scif3_device = {
 136         .name           = "sh-sci",
 137         .id             = 3,
 138         .dev            = {
 139                 .platform_data  = &scif3_platform_data,
 140         },
 141 };
 142
 143 /* SCIFA4 */
 144 static struct plat_sci_port scif4_platform_data = {
 145         .mapbase        = 0xe6c80000,
 146         .flags          = UPF_BOOT_AUTOCONF,
 147         .scscr          = SCSCR_RE | SCSCR_TE,
 148         .scbrr_algo_id  = SCBRR_ALGO_4,
 149         .type           = PORT_SCIFA,
 150         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 151                             evt2irq(0x0d20), evt2irq(0x0d20) },
 152 };
 153
 154 static struct platform_device scif4_device = {
 155         .name           = "sh-sci",
 156         .id             = 4,
 157         .dev            = {
 158                 .platform_data  = &scif4_platform_data,
 159         },
 160 };
 161
 162 /* SCIFA5 */
 163 static struct plat_sci_port scif5_platform_data = {
 164         .mapbase        = 0xe6cb0000,
 165         .flags          = UPF_BOOT_AUTOCONF,
 166         .scscr          = SCSCR_RE | SCSCR_TE,
 167         .scbrr_algo_id  = SCBRR_ALGO_4,
 168         .type           = PORT_SCIFA,
 169         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 170                             evt2irq(0x0d40), evt2irq(0x0d40) },
 171 };
 172
 173 static struct platform_device scif5_device = {
 174         .name           = "sh-sci",
 175         .id             = 5,
 176         .dev            = {
 177                 .platform_data  = &scif5_platform_data,
 178         },
 179 };
 180
 181 /* SCIFB */
 182 static struct plat_sci_port scif6_platform_data = {
 183         .mapbase        = 0xe6c30000,
 184         .flags          = UPF_BOOT_AUTOCONF,
 185         .scscr          = SCSCR_RE | SCSCR_TE,
 186         .scbrr_algo_id  = SCBRR_ALGO_4,
 187         .type           = PORT_SCIFB,
 188         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 189                             evt2irq(0x0d60), evt2irq(0x0d60) },
 190 };
 191
 192 static struct platform_device scif6_device = {
 193         .name           = "sh-sci",
 194         .id             = 6,
 195         .dev            = {
 196                 .platform_data  = &scif6_platform_data,
 197         },
 198 };
 199
 200 /* CMT */
 201 static struct sh_timer_config cmt2_platform_data = {
 202         .name = "CMT2",
 203         .channel_offset = 0x40,
 204         .timer_bit = 5,
 205         .clockevent_rating = 125,
 206         .clocksource_rating = 125,
 207 };
 208
 209 static struct resource cmt2_resources[] = {
 210         [0] = {
 211                 .name   = "CMT2",
 212                 .start  = 0xe6130040,
 213                 .end    = 0xe613004b,
 214                 .flags  = IORESOURCE_MEM,
 215         },
 216         [1] = {
 217                 .start  = evt2irq(0x0b80), /* CMT2 */
 218                 .flags  = IORESOURCE_IRQ,
 219         },
 220 };
 221
 222 static struct platform_device cmt2_device = {
 223         .name           = "sh_cmt",
 224         .id             = 2,
 225         .dev = {
 226                 .platform_data  = &cmt2_platform_data,
 227         },
 228         .resource       = cmt2_resources,
 229         .num_resources  = ARRAY_SIZE(cmt2_resources),
 230 };
 231
 232 /* TMU */
 233 static struct sh_timer_config tmu00_platform_data = {
 234         .name = "TMU00",
 235         .channel_offset = 0x4,
 236         .timer_bit = 0,
 237         .clockevent_rating = 200,
 238 };
 239
 240 static struct resource tmu00_resources[] = {
 241         [0] = {
 242                 .name   = "TMU00",
 243                 .start  = 0xfff60008,
 244                 .end    = 0xfff60013,
 245                 .flags  = IORESOURCE_MEM,
 246         },
 247         [1] = {
 248                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 249                 .flags  = IORESOURCE_IRQ,
 250         },
 251 };
 252
 253 static struct platform_device tmu00_device = {
 254         .name           = "sh_tmu",
 255         .id             = 0,
 256         .dev = {
 257                 .platform_data  = &tmu00_platform_data,
 258         },
 259         .resource       = tmu00_resources,
 260         .num_resources  = ARRAY_SIZE(tmu00_resources),
 261 };
 262
 263 static struct sh_timer_config tmu01_platform_data = {
 264         .name = "TMU01",
 265         .channel_offset = 0x10,
 266         .timer_bit = 1,
 267         .clocksource_rating = 200,
 268 };
 269
 270 static struct resource tmu01_resources[] = {
 271         [0] = {
 272                 .name   = "TMU01",
 273                 .start  = 0xfff60014,
 274                 .end    = 0xfff6001f,
 275                 .flags  = IORESOURCE_MEM,
 276         },
 277         [1] = {
 278                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 279                 .flags  = IORESOURCE_IRQ,
 280         },
 281 };
 282
 283 static struct platform_device tmu01_device = {
 284         .name           = "sh_tmu",
 285         .id             = 1,
 286         .dev = {
 287                 .platform_data  = &tmu01_platform_data,
 288         },
 289         .resource       = tmu01_resources,
 290         .num_resources  = ARRAY_SIZE(tmu01_resources),
 291 };
 292
 293 /* I2C */
 294 static struct resource iic0_resources[] = {
 295         [0] = {
 296                 .name   = "IIC0",
 297                 .start  = 0xFFF20000,
 298                 .end    = 0xFFF20425 - 1,
 299                 .flags  = IORESOURCE_MEM,
 300         },
 301         [1] = {
 302                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 303                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 304                 .flags  = IORESOURCE_IRQ,
 305         },
 306 };
 307
 308 static struct platform_device iic0_device = {
 309         .name           = "i2c-sh_mobile",
 310         .id             = 0, /* "i2c0" clock */
 311         .num_resources  = ARRAY_SIZE(iic0_resources),
 312         .resource       = iic0_resources,
 313 };
 314
 315 static struct resource iic1_resources[] = {
 316         [0] = {
 317                 .name   = "IIC1",
 318                 .start  = 0xE6C20000,
 319                 .end    = 0xE6C20425 - 1,
 320                 .flags  = IORESOURCE_MEM,
 321         },
 322         [1] = {
 323                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 324                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 325                 .flags  = IORESOURCE_IRQ,
 326         },
 327 };
 328
 329 static struct platform_device iic1_device = {
 330         .name           = "i2c-sh_mobile",
 331         .id             = 1, /* "i2c1" clock */
 332         .num_resources  = ARRAY_SIZE(iic1_resources),
 333         .resource       = iic1_resources,
 334 };
 335
 336 /* DMA */
 337 /* Transmit sizes and respective CHCR register values */
 338 enum {
 339         XMIT_SZ_8BIT            = 0,
 340         XMIT_SZ_16BIT           = 1,
 341         XMIT_SZ_32BIT           = 2,
 342         XMIT_SZ_64BIT           = 7,
 343         XMIT_SZ_128BIT          = 3,
 344         XMIT_SZ_256BIT          = 4,
 345         XMIT_SZ_512BIT          = 5,
 346 };
 347
 348 /* log2(size / 8) - used to calculate number of transfers */
 349 #define TS_SHIFT {                      \
 350         [XMIT_SZ_8BIT]          = 0,    \
 351         [XMIT_SZ_16BIT]         = 1,    \
 352         [XMIT_SZ_32BIT]         = 2,    \
 353         [XMIT_SZ_64BIT]         = 3,    \
 354         [XMIT_SZ_128BIT]        = 4,    \
 355         [XMIT_SZ_256BIT]        = 5,    \
 356         [XMIT_SZ_512BIT]        = 6,    \
 357 }
 358
 359 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
 360                          (((i) & 0xc) << (20 - 2)))
 361
 362 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 363         {
 364                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 365                 .addr           = 0xe6c40020,
 366                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 367                 .mid_rid        = 0x21,
 368         }, {
 369                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 370                 .addr           = 0xe6c40024,
 371                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 372                 .mid_rid        = 0x22,
 373         }, {
 374                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 375                 .addr           = 0xe6c50020,
 376                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 377                 .mid_rid        = 0x25,
 378         }, {
 379                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 380                 .addr           = 0xe6c50024,
 381                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 382                 .mid_rid        = 0x26,
 383         }, {
 384                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 385                 .addr           = 0xe6c60020,
 386                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 387                 .mid_rid        = 0x29,
 388         }, {
 389                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 390                 .addr           = 0xe6c60024,
 391                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 392                 .mid_rid        = 0x2a,
 393         }, {
 394                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 395                 .addr           = 0xe6c70020,
 396                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 397                 .mid_rid        = 0x2d,
 398         }, {
 399                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 400                 .addr           = 0xe6c70024,
 401                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 402                 .mid_rid        = 0x2e,
 403         }, {
 404                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 405                 .addr           = 0xe6c80020,
 406                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 407                 .mid_rid        = 0x39,
 408         }, {
 409                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 410                 .addr           = 0xe6c80024,
 411                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 412                 .mid_rid        = 0x3a,
 413         }, {
 414                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 415                 .addr           = 0xe6cb0020,
 416                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 417                 .mid_rid        = 0x35,
 418         }, {
 419                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 420                 .addr           = 0xe6cb0024,
 421                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 422                 .mid_rid        = 0x36,
 423         }, {
 424                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 425                 .addr           = 0xe6c30040,
 426                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 427                 .mid_rid        = 0x3d,
 428         }, {
 429                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 430                 .addr           = 0xe6c30060,
 431                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 432                 .mid_rid        = 0x3e,
 433         }, {
 434                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 435                 .addr           = 0xe6850030,
 436                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 437                 .mid_rid        = 0xc1,
 438         }, {
 439                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 440                 .addr           = 0xe6850030,
 441                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 442                 .mid_rid        = 0xc2,
 443         }, {
 444                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 445                 .addr           = 0xe6860030,
 446                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 447                 .mid_rid        = 0xc9,
 448         }, {
 449                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 450                 .addr           = 0xe6860030,
 451                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 452                 .mid_rid        = 0xca,
 453         }, {
 454                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 455                 .addr           = 0xe6870030,
 456                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 457                 .mid_rid        = 0xcd,
 458         }, {
 459                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 460                 .addr           = 0xe6870030,
 461                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 462                 .mid_rid        = 0xce,
 463         }, {
 464                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 465                 .addr           = 0xe6bd0034,
 466                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 467                 .mid_rid        = 0xd1,
 468         }, {
 469                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 470                 .addr           = 0xe6bd0034,
 471                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 472                 .mid_rid        = 0xd2,
 473         },
 474 };
 475
 476 #define SH7372_CHCLR 0x220
 477
 478 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 479         {
 480                 .offset = 0,
 481                 .dmars = 0,
 482                 .dmars_bit = 0,
 483                 .chclr_offset = SH7372_CHCLR + 0,
 484         }, {
 485                 .offset = 0x10,
 486                 .dmars = 0,
 487                 .dmars_bit = 8,
 488                 .chclr_offset = SH7372_CHCLR + 0x10,
 489         }, {
 490                 .offset = 0x20,
 491                 .dmars = 4,
 492                 .dmars_bit = 0,
 493                 .chclr_offset = SH7372_CHCLR + 0x20,
 494         }, {
 495                 .offset = 0x30,
 496                 .dmars = 4,
 497                 .dmars_bit = 8,
 498                 .chclr_offset = SH7372_CHCLR + 0x30,
 499         }, {
 500                 .offset = 0x50,
 501                 .dmars = 8,
 502                 .dmars_bit = 0,
 503                 .chclr_offset = SH7372_CHCLR + 0x50,
 504         }, {
 505                 .offset = 0x60,
 506                 .dmars = 8,
 507                 .dmars_bit = 8,
 508                 .chclr_offset = SH7372_CHCLR + 0x60,
 509         }
 510 };
 511
 512 static const unsigned int ts_shift[] = TS_SHIFT;
 513
 514 static struct sh_dmae_pdata dma_platform_data = {
 515         .slave          = sh7372_dmae_slaves,
 516         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 517         .channel        = sh7372_dmae_channels,
 518         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 519         .ts_low_shift   = 3,
 520         .ts_low_mask    = 0x18,
 521         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 522         .ts_high_mask   = 0x00300000,
 523         .ts_shift       = ts_shift,
 524         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 525         .dmaor_init     = DMAOR_DME,
 526         .chclr_present  = 1,
 527 };
 528
 529 /* Resource order important! */
 530 static struct resource sh7372_dmae0_resources[] = {
 531         {
 532                 /* Channel registers and DMAOR */
 533                 .start  = 0xfe008020,
 534                 .end    = 0xfe00828f,
 535                 .flags  = IORESOURCE_MEM,
 536         },
 537         {
 538                 /* DMARSx */
 539                 .start  = 0xfe009000,
 540                 .end    = 0xfe00900b,
 541                 .flags  = IORESOURCE_MEM,
 542         },
 543         {
 544                 .name   = "error_irq",
 545                 .start  = evt2irq(0x20c0),
 546                 .end    = evt2irq(0x20c0),
 547                 .flags  = IORESOURCE_IRQ,
 548         },
 549         {
 550                 /* IRQ for channels 0-5 */
 551                 .start  = evt2irq(0x2000),
 552                 .end    = evt2irq(0x20a0),
 553                 .flags  = IORESOURCE_IRQ,
 554         },
 555 };
 556
 557 /* Resource order important! */
 558 static struct resource sh7372_dmae1_resources[] = {
 559         {
 560                 /* Channel registers and DMAOR */
 561                 .start  = 0xfe018020,
 562                 .end    = 0xfe01828f,
 563                 .flags  = IORESOURCE_MEM,
 564         },
 565         {
 566                 /* DMARSx */
 567                 .start  = 0xfe019000,
 568                 .end    = 0xfe01900b,
 569                 .flags  = IORESOURCE_MEM,
 570         },
 571         {
 572                 .name   = "error_irq",
 573                 .start  = evt2irq(0x21c0),
 574                 .end    = evt2irq(0x21c0),
 575                 .flags  = IORESOURCE_IRQ,
 576         },
 577         {
 578                 /* IRQ for channels 0-5 */
 579                 .start  = evt2irq(0x2100),
 580                 .end    = evt2irq(0x21a0),
 581                 .flags  = IORESOURCE_IRQ,
 582         },
 583 };
 584
 585 /* Resource order important! */
 586 static struct resource sh7372_dmae2_resources[] = {
 587         {
 588                 /* Channel registers and DMAOR */
 589                 .start  = 0xfe028020,
 590                 .end    = 0xfe02828f,
 591                 .flags  = IORESOURCE_MEM,
 592         },
 593         {
 594                 /* DMARSx */
 595                 .start  = 0xfe029000,
 596                 .end    = 0xfe02900b,
 597                 .flags  = IORESOURCE_MEM,
 598         },
 599         {
 600                 .name   = "error_irq",
 601                 .start  = evt2irq(0x22c0),
 602                 .end    = evt2irq(0x22c0),
 603                 .flags  = IORESOURCE_IRQ,
 604         },
 605         {
 606                 /* IRQ for channels 0-5 */
 607                 .start  = evt2irq(0x2200),
 608                 .end    = evt2irq(0x22a0),
 609                 .flags  = IORESOURCE_IRQ,
 610         },
 611 };
 612
 613 static struct platform_device dma0_device = {
 614         .name           = "sh-dma-engine",
 615         .id             = 0,
 616         .resource       = sh7372_dmae0_resources,
 617         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 618         .dev            = {
 619                 .platform_data  = &dma_platform_data,
 620         },
 621 };
 622
 623 static struct platform_device dma1_device = {
 624         .name           = "sh-dma-engine",
 625         .id             = 1,
 626         .resource       = sh7372_dmae1_resources,
 627         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 628         .dev            = {
 629                 .platform_data  = &dma_platform_data,
 630         },
 631 };
 632
 633 static struct platform_device dma2_device = {
 634         .name           = "sh-dma-engine",
 635         .id             = 2,
 636         .resource       = sh7372_dmae2_resources,
 637         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 638         .dev            = {
 639                 .platform_data  = &dma_platform_data,
 640         },
 641 };
 642
 643 /*
 644  * USB-DMAC
 645  */
 646
 647 unsigned int usbts_shift[] = {3, 4, 5};
 648
 649 enum {
 650         XMIT_SZ_8BYTE           = 0,
 651         XMIT_SZ_16BYTE          = 1,
 652         XMIT_SZ_32BYTE          = 2,
 653 };
 654
 655 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
 656
 657 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 658         {
 659                 .offset = 0,
 660         }, {
 661                 .offset = 0x20,
 662         },
 663 };
 664
 665 /* USB DMAC0 */
 666 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 667         {
 668                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 669                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 670         }, {
 671                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 672                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 673         },
 674 };
 675
 676 static struct sh_dmae_pdata usb_dma0_platform_data = {
 677         .slave          = sh7372_usb_dmae0_slaves,
 678         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 679         .channel        = sh7372_usb_dmae_channels,
 680         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 681         .ts_low_shift   = 6,
 682         .ts_low_mask    = 0xc0,
 683         .ts_high_shift  = 0,
 684         .ts_high_mask   = 0,
 685         .ts_shift       = usbts_shift,
 686         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
 687         .dmaor_init     = DMAOR_DME,
 688         .chcr_offset    = 0x14,
 689         .chcr_ie_bit    = 1 << 5,
 690         .dmaor_is_32bit = 1,
 691         .needs_tend_set = 1,
 692         .no_dmars       = 1,
 693         .slave_only     = 1,
 694 };
 695
 696 static struct resource sh7372_usb_dmae0_resources[] = {
 697         {
 698                 /* Channel registers and DMAOR */
 699                 .start  = 0xe68a0020,
 700                 .end    = 0xe68a0064 - 1,
 701                 .flags  = IORESOURCE_MEM,
 702         },
 703         {
 704                 /* VCR/SWR/DMICR */
 705                 .start  = 0xe68a0000,
 706                 .end    = 0xe68a0014 - 1,
 707                 .flags  = IORESOURCE_MEM,
 708         },
 709         {
 710                 /* IRQ for channels */
 711                 .start  = evt2irq(0x0a00),
 712                 .end    = evt2irq(0x0a00),
 713                 .flags  = IORESOURCE_IRQ,
 714         },
 715 };
 716
 717 static struct platform_device usb_dma0_device = {
 718         .name           = "sh-dma-engine",
 719         .id             = 3,
 720         .resource       = sh7372_usb_dmae0_resources,
 721         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 722         .dev            = {
 723                 .platform_data  = &usb_dma0_platform_data,
 724         },
 725 };
 726
 727 /* USB DMAC1 */
 728 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 729         {
 730                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 731                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 732         }, {
 733                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 734                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 735         },
 736 };
 737
 738 static struct sh_dmae_pdata usb_dma1_platform_data = {
 739         .slave          = sh7372_usb_dmae1_slaves,
 740         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 741         .channel        = sh7372_usb_dmae_channels,
 742         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 743         .ts_low_shift   = 6,
 744         .ts_low_mask    = 0xc0,
 745         .ts_high_shift  = 0,
 746         .ts_high_mask   = 0,
 747         .ts_shift       = usbts_shift,
 748         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
 749         .dmaor_init     = DMAOR_DME,
 750         .chcr_offset    = 0x14,
 751         .chcr_ie_bit    = 1 << 5,
 752         .dmaor_is_32bit = 1,
 753         .needs_tend_set = 1,
 754         .no_dmars       = 1,
 755         .slave_only     = 1,
 756 };
 757
 758 static struct resource sh7372_usb_dmae1_resources[] = {
 759         {
 760                 /* Channel registers and DMAOR */
 761                 .start  = 0xe68c0020,
 762                 .end    = 0xe68c0064 - 1,
 763                 .flags  = IORESOURCE_MEM,
 764         },
 765         {
 766                 /* VCR/SWR/DMICR */
 767                 .start  = 0xe68c0000,
 768                 .end    = 0xe68c0014 - 1,
 769                 .flags  = IORESOURCE_MEM,
 770         },
 771         {
 772                 /* IRQ for channels */
 773                 .start  = evt2irq(0x1d00),
 774                 .end    = evt2irq(0x1d00),
 775                 .flags  = IORESOURCE_IRQ,
 776         },
 777 };
 778
 779 static struct platform_device usb_dma1_device = {
 780         .name           = "sh-dma-engine",
 781         .id             = 4,
 782         .resource       = sh7372_usb_dmae1_resources,
 783         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 784         .dev            = {
 785                 .platform_data  = &usb_dma1_platform_data,
 786         },
 787 };
 788
 789 /* VPU */
 790 static struct uio_info vpu_platform_data = {
 791         .name = "VPU5HG",
 792         .version = "0",
 793         .irq = intcs_evt2irq(0x980),
 794 };
 795
 796 static struct resource vpu_resources[] = {
 797         [0] = {
 798                 .name   = "VPU",
 799                 .start  = 0xfe900000,
 800                 .end    = 0xfe900157,
 801                 .flags  = IORESOURCE_MEM,
 802         },
 803 };
 804
 805 static struct platform_device vpu_device = {
 806         .name           = "uio_pdrv_genirq",
 807         .id             = 0,
 808         .dev = {
 809                 .platform_data  = &vpu_platform_data,
 810         },
 811         .resource       = vpu_resources,
 812         .num_resources  = ARRAY_SIZE(vpu_resources),
 813 };
 814
 815 /* VEU0 */
 816 static struct uio_info veu0_platform_data = {
 817         .name = "VEU0",
 818         .version = "0",
 819         .irq = intcs_evt2irq(0x700),
 820 };
 821
 822 static struct resource veu0_resources[] = {
 823         [0] = {
 824                 .name   = "VEU0",
 825                 .start  = 0xfe920000,
 826                 .end    = 0xfe9200cb,
 827                 .flags  = IORESOURCE_MEM,
 828         },
 829 };
 830
 831 static struct platform_device veu0_device = {
 832         .name           = "uio_pdrv_genirq",
 833         .id             = 1,
 834         .dev = {
 835                 .platform_data  = &veu0_platform_data,
 836         },
 837         .resource       = veu0_resources,
 838         .num_resources  = ARRAY_SIZE(veu0_resources),
 839 };
 840
 841 /* VEU1 */
 842 static struct uio_info veu1_platform_data = {
 843         .name = "VEU1",
 844         .version = "0",
 845         .irq = intcs_evt2irq(0x720),
 846 };
 847
 848 static struct resource veu1_resources[] = {
 849         [0] = {
 850                 .name   = "VEU1",
 851                 .start  = 0xfe924000,
 852                 .end    = 0xfe9240cb,
 853                 .flags  = IORESOURCE_MEM,
 854         },
 855 };
 856
 857 static struct platform_device veu1_device = {
 858         .name           = "uio_pdrv_genirq",
 859         .id             = 2,
 860         .dev = {
 861                 .platform_data  = &veu1_platform_data,
 862         },
 863         .resource       = veu1_resources,
 864         .num_resources  = ARRAY_SIZE(veu1_resources),
 865 };
 866
 867 /* VEU2 */
 868 static struct uio_info veu2_platform_data = {
 869         .name = "VEU2",
 870         .version = "0",
 871         .irq = intcs_evt2irq(0x740),
 872 };
 873
 874 static struct resource veu2_resources[] = {
 875         [0] = {
 876                 .name   = "VEU2",
 877                 .start  = 0xfe928000,
 878                 .end    = 0xfe928307,
 879                 .flags  = IORESOURCE_MEM,
 880         },
 881 };
 882
 883 static struct platform_device veu2_device = {
 884         .name           = "uio_pdrv_genirq",
 885         .id             = 3,
 886         .dev = {
 887                 .platform_data  = &veu2_platform_data,
 888         },
 889         .resource       = veu2_resources,
 890         .num_resources  = ARRAY_SIZE(veu2_resources),
 891 };
 892
 893 /* VEU3 */
 894 static struct uio_info veu3_platform_data = {
 895         .name = "VEU3",
 896         .version = "0",
 897         .irq = intcs_evt2irq(0x760),
 898 };
 899
 900 static struct resource veu3_resources[] = {
 901         [0] = {
 902                 .name   = "VEU3",
 903                 .start  = 0xfe92c000,
 904                 .end    = 0xfe92c307,
 905                 .flags  = IORESOURCE_MEM,
 906         },
 907 };
 908
 909 static struct platform_device veu3_device = {
 910         .name           = "uio_pdrv_genirq",
 911         .id             = 4,
 912         .dev = {
 913                 .platform_data  = &veu3_platform_data,
 914         },
 915         .resource       = veu3_resources,
 916         .num_resources  = ARRAY_SIZE(veu3_resources),
 917 };
 918
 919 /* JPU */
 920 static struct uio_info jpu_platform_data = {
 921         .name = "JPU",
 922         .version = "0",
 923         .irq = intcs_evt2irq(0x560),
 924 };
 925
 926 static struct resource jpu_resources[] = {
 927         [0] = {
 928                 .name   = "JPU",
 929                 .start  = 0xfe980000,
 930                 .end    = 0xfe9902d3,
 931                 .flags  = IORESOURCE_MEM,
 932         },
 933 };
 934
 935 static struct platform_device jpu_device = {
 936         .name           = "uio_pdrv_genirq",
 937         .id             = 5,
 938         .dev = {
 939                 .platform_data  = &jpu_platform_data,
 940         },
 941         .resource       = jpu_resources,
 942         .num_resources  = ARRAY_SIZE(jpu_resources),
 943 };
 944
 945 /* SPU2DSP0 */
 946 static struct uio_info spu0_platform_data = {
 947         .name = "SPU2DSP0",
 948         .version = "0",
 949         .irq = evt2irq(0x1800),
 950 };
 951
 952 static struct resource spu0_resources[] = {
 953         [0] = {
 954                 .name   = "SPU2DSP0",
 955                 .start  = 0xfe200000,
 956                 .end    = 0xfe2fffff,
 957                 .flags  = IORESOURCE_MEM,
 958         },
 959 };
 960
 961 static struct platform_device spu0_device = {
 962         .name           = "uio_pdrv_genirq",
 963         .id             = 6,
 964         .dev = {
 965                 .platform_data  = &spu0_platform_data,
 966         },
 967         .resource       = spu0_resources,
 968         .num_resources  = ARRAY_SIZE(spu0_resources),
 969 };
 970
 971 /* SPU2DSP1 */
 972 static struct uio_info spu1_platform_data = {
 973         .name = "SPU2DSP1",
 974         .version = "0",
 975         .irq = evt2irq(0x1820),
 976 };
 977
 978 static struct resource spu1_resources[] = {
 979         [0] = {
 980                 .name   = "SPU2DSP1",
 981                 .start  = 0xfe300000,
 982                 .end    = 0xfe3fffff,
 983                 .flags  = IORESOURCE_MEM,
 984         },
 985 };
 986
 987 static struct platform_device spu1_device = {
 988         .name           = "uio_pdrv_genirq",
 989         .id             = 7,
 990         .dev = {
 991                 .platform_data  = &spu1_platform_data,
 992         },
 993         .resource       = spu1_resources,
 994         .num_resources  = ARRAY_SIZE(spu1_resources),
 995 };
 996
 997 static struct platform_device *sh7372_early_devices[] __initdata = {
 998         &scif0_device,
 999         &scif1_device,
1000         &scif2_device,
1001         &scif3_device,
1002         &scif4_device,
1003         &scif5_device,
1004         &scif6_device,
1005         &cmt2_device,
1006         &tmu00_device,
1007         &tmu01_device,
1008 };
1009
1010 static struct platform_device *sh7372_late_devices[] __initdata = {
1011         &iic0_device,
1012         &iic1_device,
1013         &dma0_device,
1014         &dma1_device,
1015         &dma2_device,
1016         &usb_dma0_device,
1017         &usb_dma1_device,
1018         &vpu_device,
1019         &veu0_device,
1020         &veu1_device,
1021         &veu2_device,
1022         &veu3_device,
1023         &jpu_device,
1024         &spu0_device,
1025         &spu1_device,
1026 };
1027
1028 void __init sh7372_add_standard_devices(void)
1029 {
1030         sh7372_init_pm_domain(&sh7372_a4lc);
1031         sh7372_init_pm_domain(&sh7372_a4mp);
1032         sh7372_init_pm_domain(&sh7372_d4);
1033         sh7372_init_pm_domain(&sh7372_a4r);
1034         sh7372_init_pm_domain(&sh7372_a3rv);
1035         sh7372_init_pm_domain(&sh7372_a3ri);
1036         sh7372_init_pm_domain(&sh7372_a4s);
1037         sh7372_init_pm_domain(&sh7372_a3sp);
1038         sh7372_init_pm_domain(&sh7372_a3sg);
1039
1040         sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1041         sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1042
1043         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1044         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1045
1046         platform_add_devices(sh7372_early_devices,
1047                             ARRAY_SIZE(sh7372_early_devices));
1048
1049         platform_add_devices(sh7372_late_devices,
1050                             ARRAY_SIZE(sh7372_late_devices));
1051
1052         sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1053         sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1054         sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1055         sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1056         sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1057         sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1058         sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1059         sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1060         sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1061         sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1062         sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1063         sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1064         sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1065         sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1066         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1067         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1068         sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1069         sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1070         sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1071         sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1072         sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1073         sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1074         sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
1075         sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
1076 }
1077
1078 static void __init sh7372_earlytimer_init(void)
1079 {
1080         sh7372_clock_init();
1081         shmobile_earlytimer_init();
1082 }
1083
1084 void __init sh7372_add_early_devices(void)
1085 {
1086         early_platform_add_devices(sh7372_early_devices,
1087                                    ARRAY_SIZE(sh7372_early_devices));
1088
1089         /* setup early console here as well */
1090         shmobile_setup_console();
1091
1092         /* override timer setup with soc-specific code */
1093         shmobile_timer.init = sh7372_earlytimer_init;
1094 }