2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_dma.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <linux/pm_domain.h>
34 #include <linux/dma-mapping.h>
35 #include <mach/hardware.h>
36 #include <mach/irqs.h>
37 #include <mach/sh7372.h>
38 #include <mach/common.h>
39 #include <asm/mach/map.h>
40 #include <asm/mach-types.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/time.h>
44 static struct map_desc sh7372_io_desc[] __initdata = {
45 /* create a 1:1 entity map for 0xe6xxxxxx
46 * used by CPGA, INTC and PFC.
49 .virtual = 0xe6000000,
50 .pfn = __phys_to_pfn(0xe6000000),
52 .type = MT_DEVICE_NONSHARED
56 void __init sh7372_map_io(void)
58 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
61 * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
62 * enough to allocate the frame buffer memory.
64 init_consistent_dma_size(12 << 20);
68 static struct plat_sci_port scif0_platform_data = {
69 .mapbase = 0xe6c40000,
70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE,
72 .scbrr_algo_id = SCBRR_ALGO_4,
74 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
75 evt2irq(0x0c00), evt2irq(0x0c00) },
78 static struct platform_device scif0_device = {
82 .platform_data = &scif0_platform_data,
87 static struct plat_sci_port scif1_platform_data = {
88 .mapbase = 0xe6c50000,
89 .flags = UPF_BOOT_AUTOCONF,
90 .scscr = SCSCR_RE | SCSCR_TE,
91 .scbrr_algo_id = SCBRR_ALGO_4,
93 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
94 evt2irq(0x0c20), evt2irq(0x0c20) },
97 static struct platform_device scif1_device = {
101 .platform_data = &scif1_platform_data,
106 static struct plat_sci_port scif2_platform_data = {
107 .mapbase = 0xe6c60000,
108 .flags = UPF_BOOT_AUTOCONF,
109 .scscr = SCSCR_RE | SCSCR_TE,
110 .scbrr_algo_id = SCBRR_ALGO_4,
112 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
113 evt2irq(0x0c40), evt2irq(0x0c40) },
116 static struct platform_device scif2_device = {
120 .platform_data = &scif2_platform_data,
125 static struct plat_sci_port scif3_platform_data = {
126 .mapbase = 0xe6c70000,
127 .flags = UPF_BOOT_AUTOCONF,
128 .scscr = SCSCR_RE | SCSCR_TE,
129 .scbrr_algo_id = SCBRR_ALGO_4,
131 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
132 evt2irq(0x0c60), evt2irq(0x0c60) },
135 static struct platform_device scif3_device = {
139 .platform_data = &scif3_platform_data,
144 static struct plat_sci_port scif4_platform_data = {
145 .mapbase = 0xe6c80000,
146 .flags = UPF_BOOT_AUTOCONF,
147 .scscr = SCSCR_RE | SCSCR_TE,
148 .scbrr_algo_id = SCBRR_ALGO_4,
150 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
151 evt2irq(0x0d20), evt2irq(0x0d20) },
154 static struct platform_device scif4_device = {
158 .platform_data = &scif4_platform_data,
163 static struct plat_sci_port scif5_platform_data = {
164 .mapbase = 0xe6cb0000,
165 .flags = UPF_BOOT_AUTOCONF,
166 .scscr = SCSCR_RE | SCSCR_TE,
167 .scbrr_algo_id = SCBRR_ALGO_4,
169 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
170 evt2irq(0x0d40), evt2irq(0x0d40) },
173 static struct platform_device scif5_device = {
177 .platform_data = &scif5_platform_data,
182 static struct plat_sci_port scif6_platform_data = {
183 .mapbase = 0xe6c30000,
184 .flags = UPF_BOOT_AUTOCONF,
185 .scscr = SCSCR_RE | SCSCR_TE,
186 .scbrr_algo_id = SCBRR_ALGO_4,
188 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
189 evt2irq(0x0d60), evt2irq(0x0d60) },
192 static struct platform_device scif6_device = {
196 .platform_data = &scif6_platform_data,
201 static struct sh_timer_config cmt2_platform_data = {
203 .channel_offset = 0x40,
205 .clockevent_rating = 125,
206 .clocksource_rating = 125,
209 static struct resource cmt2_resources[] = {
214 .flags = IORESOURCE_MEM,
217 .start = evt2irq(0x0b80), /* CMT2 */
218 .flags = IORESOURCE_IRQ,
222 static struct platform_device cmt2_device = {
226 .platform_data = &cmt2_platform_data,
228 .resource = cmt2_resources,
229 .num_resources = ARRAY_SIZE(cmt2_resources),
233 static struct sh_timer_config tmu00_platform_data = {
235 .channel_offset = 0x4,
237 .clockevent_rating = 200,
240 static struct resource tmu00_resources[] = {
245 .flags = IORESOURCE_MEM,
248 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
249 .flags = IORESOURCE_IRQ,
253 static struct platform_device tmu00_device = {
257 .platform_data = &tmu00_platform_data,
259 .resource = tmu00_resources,
260 .num_resources = ARRAY_SIZE(tmu00_resources),
263 static struct sh_timer_config tmu01_platform_data = {
265 .channel_offset = 0x10,
267 .clocksource_rating = 200,
270 static struct resource tmu01_resources[] = {
275 .flags = IORESOURCE_MEM,
278 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
279 .flags = IORESOURCE_IRQ,
283 static struct platform_device tmu01_device = {
287 .platform_data = &tmu01_platform_data,
289 .resource = tmu01_resources,
290 .num_resources = ARRAY_SIZE(tmu01_resources),
294 static struct resource iic0_resources[] = {
298 .end = 0xFFF20425 - 1,
299 .flags = IORESOURCE_MEM,
302 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
303 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
304 .flags = IORESOURCE_IRQ,
308 static struct platform_device iic0_device = {
309 .name = "i2c-sh_mobile",
310 .id = 0, /* "i2c0" clock */
311 .num_resources = ARRAY_SIZE(iic0_resources),
312 .resource = iic0_resources,
315 static struct resource iic1_resources[] = {
319 .end = 0xE6C20425 - 1,
320 .flags = IORESOURCE_MEM,
323 .start = evt2irq(0x780), /* IIC1_ALI1 */
324 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
325 .flags = IORESOURCE_IRQ,
329 static struct platform_device iic1_device = {
330 .name = "i2c-sh_mobile",
331 .id = 1, /* "i2c1" clock */
332 .num_resources = ARRAY_SIZE(iic1_resources),
333 .resource = iic1_resources,
337 /* Transmit sizes and respective CHCR register values */
348 /* log2(size / 8) - used to calculate number of transfers */
350 [XMIT_SZ_8BIT] = 0, \
351 [XMIT_SZ_16BIT] = 1, \
352 [XMIT_SZ_32BIT] = 2, \
353 [XMIT_SZ_64BIT] = 3, \
354 [XMIT_SZ_128BIT] = 4, \
355 [XMIT_SZ_256BIT] = 5, \
356 [XMIT_SZ_512BIT] = 6, \
359 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
360 (((i) & 0xc) << (20 - 2)))
362 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
364 .slave_id = SHDMA_SLAVE_SCIF0_TX,
366 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
369 .slave_id = SHDMA_SLAVE_SCIF0_RX,
371 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
374 .slave_id = SHDMA_SLAVE_SCIF1_TX,
376 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
379 .slave_id = SHDMA_SLAVE_SCIF1_RX,
381 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
384 .slave_id = SHDMA_SLAVE_SCIF2_TX,
386 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
389 .slave_id = SHDMA_SLAVE_SCIF2_RX,
391 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
394 .slave_id = SHDMA_SLAVE_SCIF3_TX,
396 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
399 .slave_id = SHDMA_SLAVE_SCIF3_RX,
401 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
404 .slave_id = SHDMA_SLAVE_SCIF4_TX,
406 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
409 .slave_id = SHDMA_SLAVE_SCIF4_RX,
411 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
414 .slave_id = SHDMA_SLAVE_SCIF5_TX,
416 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
419 .slave_id = SHDMA_SLAVE_SCIF5_RX,
421 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
424 .slave_id = SHDMA_SLAVE_SCIF6_TX,
426 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
429 .slave_id = SHDMA_SLAVE_SCIF6_RX,
431 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
434 .slave_id = SHDMA_SLAVE_SDHI0_TX,
436 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
439 .slave_id = SHDMA_SLAVE_SDHI0_RX,
441 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
444 .slave_id = SHDMA_SLAVE_SDHI1_TX,
446 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
449 .slave_id = SHDMA_SLAVE_SDHI1_RX,
451 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
454 .slave_id = SHDMA_SLAVE_SDHI2_TX,
456 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
459 .slave_id = SHDMA_SLAVE_SDHI2_RX,
461 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
464 .slave_id = SHDMA_SLAVE_MMCIF_TX,
466 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
469 .slave_id = SHDMA_SLAVE_MMCIF_RX,
471 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
476 #define SH7372_CHCLR 0x220
478 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
483 .chclr_offset = SH7372_CHCLR + 0,
488 .chclr_offset = SH7372_CHCLR + 0x10,
493 .chclr_offset = SH7372_CHCLR + 0x20,
498 .chclr_offset = SH7372_CHCLR + 0x30,
503 .chclr_offset = SH7372_CHCLR + 0x50,
508 .chclr_offset = SH7372_CHCLR + 0x60,
512 static const unsigned int ts_shift[] = TS_SHIFT;
514 static struct sh_dmae_pdata dma_platform_data = {
515 .slave = sh7372_dmae_slaves,
516 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
517 .channel = sh7372_dmae_channels,
518 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
521 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
522 .ts_high_mask = 0x00300000,
523 .ts_shift = ts_shift,
524 .ts_shift_num = ARRAY_SIZE(ts_shift),
525 .dmaor_init = DMAOR_DME,
529 /* Resource order important! */
530 static struct resource sh7372_dmae0_resources[] = {
532 /* Channel registers and DMAOR */
535 .flags = IORESOURCE_MEM,
541 .flags = IORESOURCE_MEM,
545 .start = evt2irq(0x20c0),
546 .end = evt2irq(0x20c0),
547 .flags = IORESOURCE_IRQ,
550 /* IRQ for channels 0-5 */
551 .start = evt2irq(0x2000),
552 .end = evt2irq(0x20a0),
553 .flags = IORESOURCE_IRQ,
557 /* Resource order important! */
558 static struct resource sh7372_dmae1_resources[] = {
560 /* Channel registers and DMAOR */
563 .flags = IORESOURCE_MEM,
569 .flags = IORESOURCE_MEM,
573 .start = evt2irq(0x21c0),
574 .end = evt2irq(0x21c0),
575 .flags = IORESOURCE_IRQ,
578 /* IRQ for channels 0-5 */
579 .start = evt2irq(0x2100),
580 .end = evt2irq(0x21a0),
581 .flags = IORESOURCE_IRQ,
585 /* Resource order important! */
586 static struct resource sh7372_dmae2_resources[] = {
588 /* Channel registers and DMAOR */
591 .flags = IORESOURCE_MEM,
597 .flags = IORESOURCE_MEM,
601 .start = evt2irq(0x22c0),
602 .end = evt2irq(0x22c0),
603 .flags = IORESOURCE_IRQ,
606 /* IRQ for channels 0-5 */
607 .start = evt2irq(0x2200),
608 .end = evt2irq(0x22a0),
609 .flags = IORESOURCE_IRQ,
613 static struct platform_device dma0_device = {
614 .name = "sh-dma-engine",
616 .resource = sh7372_dmae0_resources,
617 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
619 .platform_data = &dma_platform_data,
623 static struct platform_device dma1_device = {
624 .name = "sh-dma-engine",
626 .resource = sh7372_dmae1_resources,
627 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
629 .platform_data = &dma_platform_data,
633 static struct platform_device dma2_device = {
634 .name = "sh-dma-engine",
636 .resource = sh7372_dmae2_resources,
637 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
639 .platform_data = &dma_platform_data,
647 unsigned int usbts_shift[] = {3, 4, 5};
655 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
657 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
666 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
668 .slave_id = SHDMA_SLAVE_USB0_TX,
669 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
671 .slave_id = SHDMA_SLAVE_USB0_RX,
672 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
676 static struct sh_dmae_pdata usb_dma0_platform_data = {
677 .slave = sh7372_usb_dmae0_slaves,
678 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
679 .channel = sh7372_usb_dmae_channels,
680 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
685 .ts_shift = usbts_shift,
686 .ts_shift_num = ARRAY_SIZE(usbts_shift),
687 .dmaor_init = DMAOR_DME,
689 .chcr_ie_bit = 1 << 5,
696 static struct resource sh7372_usb_dmae0_resources[] = {
698 /* Channel registers and DMAOR */
700 .end = 0xe68a0064 - 1,
701 .flags = IORESOURCE_MEM,
706 .end = 0xe68a0014 - 1,
707 .flags = IORESOURCE_MEM,
710 /* IRQ for channels */
711 .start = evt2irq(0x0a00),
712 .end = evt2irq(0x0a00),
713 .flags = IORESOURCE_IRQ,
717 static struct platform_device usb_dma0_device = {
718 .name = "sh-dma-engine",
720 .resource = sh7372_usb_dmae0_resources,
721 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
723 .platform_data = &usb_dma0_platform_data,
728 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
730 .slave_id = SHDMA_SLAVE_USB1_TX,
731 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
733 .slave_id = SHDMA_SLAVE_USB1_RX,
734 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
738 static struct sh_dmae_pdata usb_dma1_platform_data = {
739 .slave = sh7372_usb_dmae1_slaves,
740 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
741 .channel = sh7372_usb_dmae_channels,
742 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
747 .ts_shift = usbts_shift,
748 .ts_shift_num = ARRAY_SIZE(usbts_shift),
749 .dmaor_init = DMAOR_DME,
751 .chcr_ie_bit = 1 << 5,
758 static struct resource sh7372_usb_dmae1_resources[] = {
760 /* Channel registers and DMAOR */
762 .end = 0xe68c0064 - 1,
763 .flags = IORESOURCE_MEM,
768 .end = 0xe68c0014 - 1,
769 .flags = IORESOURCE_MEM,
772 /* IRQ for channels */
773 .start = evt2irq(0x1d00),
774 .end = evt2irq(0x1d00),
775 .flags = IORESOURCE_IRQ,
779 static struct platform_device usb_dma1_device = {
780 .name = "sh-dma-engine",
782 .resource = sh7372_usb_dmae1_resources,
783 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
785 .platform_data = &usb_dma1_platform_data,
790 static struct uio_info vpu_platform_data = {
793 .irq = intcs_evt2irq(0x980),
796 static struct resource vpu_resources[] = {
801 .flags = IORESOURCE_MEM,
805 static struct platform_device vpu_device = {
806 .name = "uio_pdrv_genirq",
809 .platform_data = &vpu_platform_data,
811 .resource = vpu_resources,
812 .num_resources = ARRAY_SIZE(vpu_resources),
816 static struct uio_info veu0_platform_data = {
819 .irq = intcs_evt2irq(0x700),
822 static struct resource veu0_resources[] = {
827 .flags = IORESOURCE_MEM,
831 static struct platform_device veu0_device = {
832 .name = "uio_pdrv_genirq",
835 .platform_data = &veu0_platform_data,
837 .resource = veu0_resources,
838 .num_resources = ARRAY_SIZE(veu0_resources),
842 static struct uio_info veu1_platform_data = {
845 .irq = intcs_evt2irq(0x720),
848 static struct resource veu1_resources[] = {
853 .flags = IORESOURCE_MEM,
857 static struct platform_device veu1_device = {
858 .name = "uio_pdrv_genirq",
861 .platform_data = &veu1_platform_data,
863 .resource = veu1_resources,
864 .num_resources = ARRAY_SIZE(veu1_resources),
868 static struct uio_info veu2_platform_data = {
871 .irq = intcs_evt2irq(0x740),
874 static struct resource veu2_resources[] = {
879 .flags = IORESOURCE_MEM,
883 static struct platform_device veu2_device = {
884 .name = "uio_pdrv_genirq",
887 .platform_data = &veu2_platform_data,
889 .resource = veu2_resources,
890 .num_resources = ARRAY_SIZE(veu2_resources),
894 static struct uio_info veu3_platform_data = {
897 .irq = intcs_evt2irq(0x760),
900 static struct resource veu3_resources[] = {
905 .flags = IORESOURCE_MEM,
909 static struct platform_device veu3_device = {
910 .name = "uio_pdrv_genirq",
913 .platform_data = &veu3_platform_data,
915 .resource = veu3_resources,
916 .num_resources = ARRAY_SIZE(veu3_resources),
920 static struct uio_info jpu_platform_data = {
923 .irq = intcs_evt2irq(0x560),
926 static struct resource jpu_resources[] = {
931 .flags = IORESOURCE_MEM,
935 static struct platform_device jpu_device = {
936 .name = "uio_pdrv_genirq",
939 .platform_data = &jpu_platform_data,
941 .resource = jpu_resources,
942 .num_resources = ARRAY_SIZE(jpu_resources),
946 static struct uio_info spu0_platform_data = {
949 .irq = evt2irq(0x1800),
952 static struct resource spu0_resources[] = {
957 .flags = IORESOURCE_MEM,
961 static struct platform_device spu0_device = {
962 .name = "uio_pdrv_genirq",
965 .platform_data = &spu0_platform_data,
967 .resource = spu0_resources,
968 .num_resources = ARRAY_SIZE(spu0_resources),
972 static struct uio_info spu1_platform_data = {
975 .irq = evt2irq(0x1820),
978 static struct resource spu1_resources[] = {
983 .flags = IORESOURCE_MEM,
987 static struct platform_device spu1_device = {
988 .name = "uio_pdrv_genirq",
991 .platform_data = &spu1_platform_data,
993 .resource = spu1_resources,
994 .num_resources = ARRAY_SIZE(spu1_resources),
997 static struct platform_device *sh7372_early_devices[] __initdata = {
1010 static struct platform_device *sh7372_late_devices[] __initdata = {
1028 void __init sh7372_add_standard_devices(void)
1030 sh7372_init_pm_domain(&sh7372_a4lc);
1031 sh7372_init_pm_domain(&sh7372_a4mp);
1032 sh7372_init_pm_domain(&sh7372_d4);
1033 sh7372_init_pm_domain(&sh7372_a4r);
1034 sh7372_init_pm_domain(&sh7372_a3rv);
1035 sh7372_init_pm_domain(&sh7372_a3ri);
1036 sh7372_init_pm_domain(&sh7372_a4s);
1037 sh7372_init_pm_domain(&sh7372_a3sp);
1038 sh7372_init_pm_domain(&sh7372_a3sg);
1040 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1041 sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1043 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1044 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1046 platform_add_devices(sh7372_early_devices,
1047 ARRAY_SIZE(sh7372_early_devices));
1049 platform_add_devices(sh7372_late_devices,
1050 ARRAY_SIZE(sh7372_late_devices));
1052 sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1053 sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1054 sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1055 sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1056 sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1057 sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1058 sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1059 sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1060 sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1061 sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1062 sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1063 sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1064 sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1065 sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1066 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1067 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1068 sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1069 sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1070 sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1071 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1072 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1073 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1074 sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
1075 sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
1078 static void __init sh7372_earlytimer_init(void)
1080 sh7372_clock_init();
1081 shmobile_earlytimer_init();
1084 void __init sh7372_add_early_devices(void)
1086 early_platform_add_devices(sh7372_early_devices,
1087 ARRAY_SIZE(sh7372_early_devices));
1089 /* setup early console here as well */
1090 shmobile_setup_console();
1092 /* override timer setup with soc-specific code */
1093 shmobile_timer.init = sh7372_earlytimer_init;