Pileus Git - ~andy/linux/blob - arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/serial_sci.h>
  28 #include <linux/sh_dma.h>
  29 #include <linux/sh_timer.h>
  30 #include <mach/dma-register.h>
  31 #include <mach/r8a7740.h>
  32 #include <mach/pm-rmobile.h>
  33 #include <mach/common.h>
  34 #include <mach/irqs.h>
  35 #include <asm/mach-types.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/time.h>
  39
  40 static struct map_desc r8a7740_io_desc[] __initdata = {
  41          /*
  42           * for CPGA/INTC/PFC
  43           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  44           */
  45         {
  46                 .virtual        = 0xe6000000,
  47                 .pfn            = __phys_to_pfn(0xe6000000),
  48                 .length         = 160 << 20,
  49                 .type           = MT_DEVICE_NONSHARED
  50         },
  51 #ifdef CONFIG_CACHE_L2X0
  52         /*
  53          * for l2x0_init()
  54          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  55          */
  56         {
  57                 .virtual        = 0xf0002000,
  58                 .pfn            = __phys_to_pfn(0xf0100000),
  59                 .length         = PAGE_SIZE,
  60                 .type           = MT_DEVICE_NONSHARED
  61         },
  62 #endif
  63 };
  64
  65 void __init r8a7740_map_io(void)
  66 {
  67         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  68 }
  69
  70 /* PFC */
  71 static struct resource r8a7740_pfc_resources[] = {
  72         [0] = {
  73                 .start  = 0xe6050000,
  74                 .end    = 0xe6057fff,
  75                 .flags  = IORESOURCE_MEM,
  76         },
  77         [1] = {
  78                 .start  = 0xe605800c,
  79                 .end    = 0xe605802b,
  80                 .flags  = IORESOURCE_MEM,
  81         }
  82 };
  83
  84 static struct platform_device r8a7740_pfc_device = {
  85         .name           = "pfc-r8a7740",
  86         .id             = -1,
  87         .resource       = r8a7740_pfc_resources,
  88         .num_resources  = ARRAY_SIZE(r8a7740_pfc_resources),
  89 };
  90
  91 void __init r8a7740_pinmux_init(void)
  92 {
  93         platform_device_register(&r8a7740_pfc_device);
  94 }
  95
  96 /* SCIFA0 */
  97 static struct plat_sci_port scif0_platform_data = {
  98         .mapbase        = 0xe6c40000,
  99         .flags          = UPF_BOOT_AUTOCONF,
 100         .scscr          = SCSCR_RE | SCSCR_TE,
 101         .scbrr_algo_id  = SCBRR_ALGO_4,
 102         .type           = PORT_SCIFA,
 103         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
 104 };
 105
 106 static struct platform_device scif0_device = {
 107         .name           = "sh-sci",
 108         .id             = 0,
 109         .dev            = {
 110                 .platform_data  = &scif0_platform_data,
 111         },
 112 };
 113
 114 /* SCIFA1 */
 115 static struct plat_sci_port scif1_platform_data = {
 116         .mapbase        = 0xe6c50000,
 117         .flags          = UPF_BOOT_AUTOCONF,
 118         .scscr          = SCSCR_RE | SCSCR_TE,
 119         .scbrr_algo_id  = SCBRR_ALGO_4,
 120         .type           = PORT_SCIFA,
 121         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
 122 };
 123
 124 static struct platform_device scif1_device = {
 125         .name           = "sh-sci",
 126         .id             = 1,
 127         .dev            = {
 128                 .platform_data  = &scif1_platform_data,
 129         },
 130 };
 131
 132 /* SCIFA2 */
 133 static struct plat_sci_port scif2_platform_data = {
 134         .mapbase        = 0xe6c60000,
 135         .flags          = UPF_BOOT_AUTOCONF,
 136         .scscr          = SCSCR_RE | SCSCR_TE,
 137         .scbrr_algo_id  = SCBRR_ALGO_4,
 138         .type           = PORT_SCIFA,
 139         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
 140 };
 141
 142 static struct platform_device scif2_device = {
 143         .name           = "sh-sci",
 144         .id             = 2,
 145         .dev            = {
 146                 .platform_data  = &scif2_platform_data,
 147         },
 148 };
 149
 150 /* SCIFA3 */
 151 static struct plat_sci_port scif3_platform_data = {
 152         .mapbase        = 0xe6c70000,
 153         .flags          = UPF_BOOT_AUTOCONF,
 154         .scscr          = SCSCR_RE | SCSCR_TE,
 155         .scbrr_algo_id  = SCBRR_ALGO_4,
 156         .type           = PORT_SCIFA,
 157         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
 158 };
 159
 160 static struct platform_device scif3_device = {
 161         .name           = "sh-sci",
 162         .id             = 3,
 163         .dev            = {
 164                 .platform_data  = &scif3_platform_data,
 165         },
 166 };
 167
 168 /* SCIFA4 */
 169 static struct plat_sci_port scif4_platform_data = {
 170         .mapbase        = 0xe6c80000,
 171         .flags          = UPF_BOOT_AUTOCONF,
 172         .scscr          = SCSCR_RE | SCSCR_TE,
 173         .scbrr_algo_id  = SCBRR_ALGO_4,
 174         .type           = PORT_SCIFA,
 175         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
 176 };
 177
 178 static struct platform_device scif4_device = {
 179         .name           = "sh-sci",
 180         .id             = 4,
 181         .dev            = {
 182                 .platform_data  = &scif4_platform_data,
 183         },
 184 };
 185
 186 /* SCIFA5 */
 187 static struct plat_sci_port scif5_platform_data = {
 188         .mapbase        = 0xe6cb0000,
 189         .flags          = UPF_BOOT_AUTOCONF,
 190         .scscr          = SCSCR_RE | SCSCR_TE,
 191         .scbrr_algo_id  = SCBRR_ALGO_4,
 192         .type           = PORT_SCIFA,
 193         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
 194 };
 195
 196 static struct platform_device scif5_device = {
 197         .name           = "sh-sci",
 198         .id             = 5,
 199         .dev            = {
 200                 .platform_data  = &scif5_platform_data,
 201         },
 202 };
 203
 204 /* SCIFA6 */
 205 static struct plat_sci_port scif6_platform_data = {
 206         .mapbase        = 0xe6cc0000,
 207         .flags          = UPF_BOOT_AUTOCONF,
 208         .scscr          = SCSCR_RE | SCSCR_TE,
 209         .scbrr_algo_id  = SCBRR_ALGO_4,
 210         .type           = PORT_SCIFA,
 211         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
 212 };
 213
 214 static struct platform_device scif6_device = {
 215         .name           = "sh-sci",
 216         .id             = 6,
 217         .dev            = {
 218                 .platform_data  = &scif6_platform_data,
 219         },
 220 };
 221
 222 /* SCIFA7 */
 223 static struct plat_sci_port scif7_platform_data = {
 224         .mapbase        = 0xe6cd0000,
 225         .flags          = UPF_BOOT_AUTOCONF,
 226         .scscr          = SCSCR_RE | SCSCR_TE,
 227         .scbrr_algo_id  = SCBRR_ALGO_4,
 228         .type           = PORT_SCIFA,
 229         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
 230 };
 231
 232 static struct platform_device scif7_device = {
 233         .name           = "sh-sci",
 234         .id             = 7,
 235         .dev            = {
 236                 .platform_data  = &scif7_platform_data,
 237         },
 238 };
 239
 240 /* SCIFB */
 241 static struct plat_sci_port scifb_platform_data = {
 242         .mapbase        = 0xe6c30000,
 243         .flags          = UPF_BOOT_AUTOCONF,
 244         .scscr          = SCSCR_RE | SCSCR_TE,
 245         .scbrr_algo_id  = SCBRR_ALGO_4,
 246         .type           = PORT_SCIFB,
 247         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
 248 };
 249
 250 static struct platform_device scifb_device = {
 251         .name           = "sh-sci",
 252         .id             = 8,
 253         .dev            = {
 254                 .platform_data  = &scifb_platform_data,
 255         },
 256 };
 257
 258 /* CMT */
 259 static struct sh_timer_config cmt10_platform_data = {
 260         .name = "CMT10",
 261         .channel_offset = 0x10,
 262         .timer_bit = 0,
 263         .clockevent_rating = 125,
 264         .clocksource_rating = 125,
 265 };
 266
 267 static struct resource cmt10_resources[] = {
 268         [0] = {
 269                 .name   = "CMT10",
 270                 .start  = 0xe6138010,
 271                 .end    = 0xe613801b,
 272                 .flags  = IORESOURCE_MEM,
 273         },
 274         [1] = {
 275                 .start  = evt2irq(0x0b00),
 276                 .flags  = IORESOURCE_IRQ,
 277         },
 278 };
 279
 280 static struct platform_device cmt10_device = {
 281         .name           = "sh_cmt",
 282         .id             = 10,
 283         .dev = {
 284                 .platform_data  = &cmt10_platform_data,
 285         },
 286         .resource       = cmt10_resources,
 287         .num_resources  = ARRAY_SIZE(cmt10_resources),
 288 };
 289
 290 /* TMU */
 291 static struct sh_timer_config tmu00_platform_data = {
 292         .name = "TMU00",
 293         .channel_offset = 0x4,
 294         .timer_bit = 0,
 295         .clockevent_rating = 200,
 296 };
 297
 298 static struct resource tmu00_resources[] = {
 299         [0] = {
 300                 .name   = "TMU00",
 301                 .start  = 0xfff80008,
 302                 .end    = 0xfff80014 - 1,
 303                 .flags  = IORESOURCE_MEM,
 304         },
 305         [1] = {
 306                 .start  = intcs_evt2irq(0xe80),
 307                 .flags  = IORESOURCE_IRQ,
 308         },
 309 };
 310
 311 static struct platform_device tmu00_device = {
 312         .name           = "sh_tmu",
 313         .id             = 0,
 314         .dev = {
 315                 .platform_data  = &tmu00_platform_data,
 316         },
 317         .resource       = tmu00_resources,
 318         .num_resources  = ARRAY_SIZE(tmu00_resources),
 319 };
 320
 321 static struct sh_timer_config tmu01_platform_data = {
 322         .name = "TMU01",
 323         .channel_offset = 0x10,
 324         .timer_bit = 1,
 325         .clocksource_rating = 200,
 326 };
 327
 328 static struct resource tmu01_resources[] = {
 329         [0] = {
 330                 .name   = "TMU01",
 331                 .start  = 0xfff80014,
 332                 .end    = 0xfff80020 - 1,
 333                 .flags  = IORESOURCE_MEM,
 334         },
 335         [1] = {
 336                 .start  = intcs_evt2irq(0xea0),
 337                 .flags  = IORESOURCE_IRQ,
 338         },
 339 };
 340
 341 static struct platform_device tmu01_device = {
 342         .name           = "sh_tmu",
 343         .id             = 1,
 344         .dev = {
 345                 .platform_data  = &tmu01_platform_data,
 346         },
 347         .resource       = tmu01_resources,
 348         .num_resources  = ARRAY_SIZE(tmu01_resources),
 349 };
 350
 351 static struct sh_timer_config tmu02_platform_data = {
 352         .name = "TMU02",
 353         .channel_offset = 0x1C,
 354         .timer_bit = 2,
 355         .clocksource_rating = 200,
 356 };
 357
 358 static struct resource tmu02_resources[] = {
 359         [0] = {
 360                 .name   = "TMU02",
 361                 .start  = 0xfff80020,
 362                 .end    = 0xfff8002C - 1,
 363                 .flags  = IORESOURCE_MEM,
 364         },
 365         [1] = {
 366                 .start  = intcs_evt2irq(0xec0),
 367                 .flags  = IORESOURCE_IRQ,
 368         },
 369 };
 370
 371 static struct platform_device tmu02_device = {
 372         .name           = "sh_tmu",
 373         .id             = 2,
 374         .dev = {
 375                 .platform_data  = &tmu02_platform_data,
 376         },
 377         .resource       = tmu02_resources,
 378         .num_resources  = ARRAY_SIZE(tmu02_resources),
 379 };
 380
 381 static struct platform_device *r8a7740_early_devices[] __initdata = {
 382         &scif0_device,
 383         &scif1_device,
 384         &scif2_device,
 385         &scif3_device,
 386         &scif4_device,
 387         &scif5_device,
 388         &scif6_device,
 389         &scif7_device,
 390         &scifb_device,
 391         &cmt10_device,
 392         &tmu00_device,
 393         &tmu01_device,
 394         &tmu02_device,
 395 };
 396
 397 /* DMA */
 398 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 399         {
 400                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 401                 .addr           = 0xe6850030,
 402                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 403                 .mid_rid        = 0xc1,
 404         }, {
 405                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 406                 .addr           = 0xe6850030,
 407                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 408                 .mid_rid        = 0xc2,
 409         }, {
 410                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 411                 .addr           = 0xe6860030,
 412                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 413                 .mid_rid        = 0xc9,
 414         }, {
 415                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 416                 .addr           = 0xe6860030,
 417                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 418                 .mid_rid        = 0xca,
 419         }, {
 420                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 421                 .addr           = 0xe6870030,
 422                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 423                 .mid_rid        = 0xcd,
 424         }, {
 425                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 426                 .addr           = 0xe6870030,
 427                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 428                 .mid_rid        = 0xce,
 429         }, {
 430                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 431                 .addr           = 0xfe1f0024,
 432                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 433                 .mid_rid        = 0xb1,
 434         }, {
 435                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 436                 .addr           = 0xfe1f0020,
 437                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 438                 .mid_rid        = 0xb2,
 439         }, {
 440                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 441                 .addr           = 0xfe1f0064,
 442                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 443                 .mid_rid        = 0xb5,
 444         },
 445 };
 446
 447 #define DMA_CHANNEL(a, b, c)                    \
 448 {                                               \
 449         .offset         = a,                    \
 450         .dmars          = b,                    \
 451         .dmars_bit      = c,                    \
 452         .chclr_offset   = (0x220 - 0x20) + a    \
 453 }
 454
 455 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 456         DMA_CHANNEL(0x00, 0, 0),
 457         DMA_CHANNEL(0x10, 0, 8),
 458         DMA_CHANNEL(0x20, 4, 0),
 459         DMA_CHANNEL(0x30, 4, 8),
 460         DMA_CHANNEL(0x50, 8, 0),
 461         DMA_CHANNEL(0x60, 8, 8),
 462 };
 463
 464 static struct sh_dmae_pdata dma_platform_data = {
 465         .slave          = r8a7740_dmae_slaves,
 466         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 467         .channel        = r8a7740_dmae_channels,
 468         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 469         .ts_low_shift   = TS_LOW_SHIFT,
 470         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 471         .ts_high_shift  = TS_HI_SHIFT,
 472         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 473         .ts_shift       = dma_ts_shift,
 474         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 475         .dmaor_init     = DMAOR_DME,
 476         .chclr_present  = 1,
 477 };
 478
 479 /* Resource order important! */
 480 static struct resource r8a7740_dmae0_resources[] = {
 481         {
 482                 /* Channel registers and DMAOR */
 483                 .start  = 0xfe008020,
 484                 .end    = 0xfe00828f,
 485                 .flags  = IORESOURCE_MEM,
 486         },
 487         {
 488                 /* DMARSx */
 489                 .start  = 0xfe009000,
 490                 .end    = 0xfe00900b,
 491                 .flags  = IORESOURCE_MEM,
 492         },
 493         {
 494                 .name   = "error_irq",
 495                 .start  = evt2irq(0x20c0),
 496                 .end    = evt2irq(0x20c0),
 497                 .flags  = IORESOURCE_IRQ,
 498         },
 499         {
 500                 /* IRQ for channels 0-5 */
 501                 .start  = evt2irq(0x2000),
 502                 .end    = evt2irq(0x20a0),
 503                 .flags  = IORESOURCE_IRQ,
 504         },
 505 };
 506
 507 /* Resource order important! */
 508 static struct resource r8a7740_dmae1_resources[] = {
 509         {
 510                 /* Channel registers and DMAOR */
 511                 .start  = 0xfe018020,
 512                 .end    = 0xfe01828f,
 513                 .flags  = IORESOURCE_MEM,
 514         },
 515         {
 516                 /* DMARSx */
 517                 .start  = 0xfe019000,
 518                 .end    = 0xfe01900b,
 519                 .flags  = IORESOURCE_MEM,
 520         },
 521         {
 522                 .name   = "error_irq",
 523                 .start  = evt2irq(0x21c0),
 524                 .end    = evt2irq(0x21c0),
 525                 .flags  = IORESOURCE_IRQ,
 526         },
 527         {
 528                 /* IRQ for channels 0-5 */
 529                 .start  = evt2irq(0x2100),
 530                 .end    = evt2irq(0x21a0),
 531                 .flags  = IORESOURCE_IRQ,
 532         },
 533 };
 534
 535 /* Resource order important! */
 536 static struct resource r8a7740_dmae2_resources[] = {
 537         {
 538                 /* Channel registers and DMAOR */
 539                 .start  = 0xfe028020,
 540                 .end    = 0xfe02828f,
 541                 .flags  = IORESOURCE_MEM,
 542         },
 543         {
 544                 /* DMARSx */
 545                 .start  = 0xfe029000,
 546                 .end    = 0xfe02900b,
 547                 .flags  = IORESOURCE_MEM,
 548         },
 549         {
 550                 .name   = "error_irq",
 551                 .start  = evt2irq(0x22c0),
 552                 .end    = evt2irq(0x22c0),
 553                 .flags  = IORESOURCE_IRQ,
 554         },
 555         {
 556                 /* IRQ for channels 0-5 */
 557                 .start  = evt2irq(0x2200),
 558                 .end    = evt2irq(0x22a0),
 559                 .flags  = IORESOURCE_IRQ,
 560         },
 561 };
 562
 563 static struct platform_device dma0_device = {
 564         .name           = "sh-dma-engine",
 565         .id             = 0,
 566         .resource       = r8a7740_dmae0_resources,
 567         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 568         .dev            = {
 569                 .platform_data  = &dma_platform_data,
 570         },
 571 };
 572
 573 static struct platform_device dma1_device = {
 574         .name           = "sh-dma-engine",
 575         .id             = 1,
 576         .resource       = r8a7740_dmae1_resources,
 577         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 578         .dev            = {
 579                 .platform_data  = &dma_platform_data,
 580         },
 581 };
 582
 583 static struct platform_device dma2_device = {
 584         .name           = "sh-dma-engine",
 585         .id             = 2,
 586         .resource       = r8a7740_dmae2_resources,
 587         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 588         .dev            = {
 589                 .platform_data  = &dma_platform_data,
 590         },
 591 };
 592
 593 /* USB-DMAC */
 594 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 595         {
 596                 .offset = 0,
 597         }, {
 598                 .offset = 0x20,
 599         },
 600 };
 601
 602 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 603         {
 604                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 605                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 606         }, {
 607                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 608                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 609         },
 610 };
 611
 612 static struct sh_dmae_pdata usb_dma_platform_data = {
 613         .slave          = r8a7740_usb_dma_slaves,
 614         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 615         .channel        = r8a7740_usb_dma_channels,
 616         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 617         .ts_low_shift   = USBTS_LOW_SHIFT,
 618         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 619         .ts_high_shift  = USBTS_HI_SHIFT,
 620         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 621         .ts_shift       = dma_usbts_shift,
 622         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 623         .dmaor_init     = DMAOR_DME,
 624         .chcr_offset    = 0x14,
 625         .chcr_ie_bit    = 1 << 5,
 626         .dmaor_is_32bit = 1,
 627         .needs_tend_set = 1,
 628         .no_dmars       = 1,
 629         .slave_only     = 1,
 630 };
 631
 632 static struct resource r8a7740_usb_dma_resources[] = {
 633         {
 634                 /* Channel registers and DMAOR */
 635                 .start  = 0xe68a0020,
 636                 .end    = 0xe68a0064 - 1,
 637                 .flags  = IORESOURCE_MEM,
 638         },
 639         {
 640                 /* VCR/SWR/DMICR */
 641                 .start  = 0xe68a0000,
 642                 .end    = 0xe68a0014 - 1,
 643                 .flags  = IORESOURCE_MEM,
 644         },
 645         {
 646                 /* IRQ for channels */
 647                 .start  = evt2irq(0x0a00),
 648                 .end    = evt2irq(0x0a00),
 649                 .flags  = IORESOURCE_IRQ,
 650         },
 651 };
 652
 653 static struct platform_device usb_dma_device = {
 654         .name           = "sh-dma-engine",
 655         .id             = 3,
 656         .resource       = r8a7740_usb_dma_resources,
 657         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 658         .dev            = {
 659                 .platform_data  = &usb_dma_platform_data,
 660         },
 661 };
 662
 663 /* I2C */
 664 static struct resource i2c0_resources[] = {
 665         [0] = {
 666                 .name   = "IIC0",
 667                 .start  = 0xfff20000,
 668                 .end    = 0xfff20425 - 1,
 669                 .flags  = IORESOURCE_MEM,
 670         },
 671         [1] = {
 672                 .start  = intcs_evt2irq(0xe00),
 673                 .end    = intcs_evt2irq(0xe60),
 674                 .flags  = IORESOURCE_IRQ,
 675         },
 676 };
 677
 678 static struct resource i2c1_resources[] = {
 679         [0] = {
 680                 .name   = "IIC1",
 681                 .start  = 0xe6c20000,
 682                 .end    = 0xe6c20425 - 1,
 683                 .flags  = IORESOURCE_MEM,
 684         },
 685         [1] = {
 686                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 687                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 688                 .flags  = IORESOURCE_IRQ,
 689         },
 690 };
 691
 692 static struct platform_device i2c0_device = {
 693         .name           = "i2c-sh_mobile",
 694         .id             = 0,
 695         .resource       = i2c0_resources,
 696         .num_resources  = ARRAY_SIZE(i2c0_resources),
 697 };
 698
 699 static struct platform_device i2c1_device = {
 700         .name           = "i2c-sh_mobile",
 701         .id             = 1,
 702         .resource       = i2c1_resources,
 703         .num_resources  = ARRAY_SIZE(i2c1_resources),
 704 };
 705
 706 static struct resource pmu_resources[] = {
 707         [0] = {
 708                 .start  = evt2irq(0x19a0),
 709                 .end    = evt2irq(0x19a0),
 710                 .flags  = IORESOURCE_IRQ,
 711         },
 712 };
 713
 714 static struct platform_device pmu_device = {
 715         .name   = "arm-pmu",
 716         .id     = -1,
 717         .num_resources = ARRAY_SIZE(pmu_resources),
 718         .resource = pmu_resources,
 719 };
 720
 721 static struct platform_device *r8a7740_late_devices[] __initdata = {
 722         &i2c0_device,
 723         &i2c1_device,
 724         &dma0_device,
 725         &dma1_device,
 726         &dma2_device,
 727         &usb_dma_device,
 728         &pmu_device,
 729 };
 730
 731 /*
 732  * r8a7740 chip has lasting errata on MERAM buffer.
 733  * this is work-around for it.
 734  * see
 735  *      "Media RAM (MERAM)" on r8a7740 documentation
 736  */
 737 #define MEBUFCNTR       0xFE950098
 738 void r8a7740_meram_workaround(void)
 739 {
 740         void __iomem *reg;
 741
 742         reg = ioremap_nocache(MEBUFCNTR, 4);
 743         if (reg) {
 744                 iowrite32(0x01600164, reg);
 745                 iounmap(reg);
 746         }
 747 }
 748
 749 #define ICCR    0x0004
 750 #define ICSTART 0x0070
 751
 752 #define i2c_read(reg, offset)           ioread8(reg + offset)
 753 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 754
 755 /*
 756  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 757  * this is work-around for it.
 758  */
 759 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 760 {
 761         struct resource *res;
 762         void __iomem *reg;
 763
 764         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 765         if (unlikely(!res)) {
 766                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 767                 return;
 768         }
 769
 770         reg = ioremap(res->start, resource_size(res));
 771         if (unlikely(!reg)) {
 772                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 773                 return;
 774         }
 775
 776         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 777         i2c_read(reg, ICCR); /* dummy read */
 778
 779         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 780         i2c_read(reg, ICSTART); /* dummy read */
 781
 782         udelay(10);
 783
 784         i2c_write(reg, ICCR, 0x01);
 785         i2c_write(reg, ICSTART, 0x00);
 786
 787         udelay(10);
 788
 789         i2c_write(reg, ICCR, 0x10);
 790         udelay(10);
 791         i2c_write(reg, ICCR, 0x00);
 792         udelay(10);
 793         i2c_write(reg, ICCR, 0x10);
 794         udelay(10);
 795
 796         iounmap(reg);
 797 }
 798
 799 void __init r8a7740_add_standard_devices(void)
 800 {
 801         /* I2C work-around */
 802         r8a7740_i2c_workaround(&i2c0_device);
 803         r8a7740_i2c_workaround(&i2c1_device);
 804
 805         r8a7740_init_pm_domains();
 806
 807         /* add devices */
 808         platform_add_devices(r8a7740_early_devices,
 809                             ARRAY_SIZE(r8a7740_early_devices));
 810         platform_add_devices(r8a7740_late_devices,
 811                              ARRAY_SIZE(r8a7740_late_devices));
 812
 813         /* add devices to PM domain  */
 814
 815         rmobile_add_device_to_domain("A3SP",    &scif0_device);
 816         rmobile_add_device_to_domain("A3SP",    &scif1_device);
 817         rmobile_add_device_to_domain("A3SP",    &scif2_device);
 818         rmobile_add_device_to_domain("A3SP",    &scif3_device);
 819         rmobile_add_device_to_domain("A3SP",    &scif4_device);
 820         rmobile_add_device_to_domain("A3SP",    &scif5_device);
 821         rmobile_add_device_to_domain("A3SP",    &scif6_device);
 822         rmobile_add_device_to_domain("A3SP",    &scif7_device);
 823         rmobile_add_device_to_domain("A3SP",    &scifb_device);
 824         rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 825 }
 826
 827 void __init r8a7740_add_early_devices(void)
 828 {
 829         early_platform_add_devices(r8a7740_early_devices,
 830                                    ARRAY_SIZE(r8a7740_early_devices));
 831
 832         /* setup early console here as well */
 833         shmobile_setup_console();
 834 }
 835
 836 #ifdef CONFIG_USE_OF
 837
 838 void __init r8a7740_add_early_devices_dt(void)
 839 {
 840         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
 841
 842         early_platform_add_devices(r8a7740_early_devices,
 843                                    ARRAY_SIZE(r8a7740_early_devices));
 844
 845         /* setup early console here as well */
 846         shmobile_setup_console();
 847 }
 848
 849 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
 850         { }
 851 };
 852
 853 void __init r8a7740_add_standard_devices_dt(void)
 854 {
 855         /* clocks are setup late during boot in the case of DT */
 856         r8a7740_clock_init(0);
 857
 858         platform_add_devices(r8a7740_early_devices,
 859                             ARRAY_SIZE(r8a7740_early_devices));
 860
 861         of_platform_populate(NULL, of_default_bus_match_table,
 862                              r8a7740_auxdata_lookup, NULL);
 863 }
 864
 865 static const char *r8a7740_boards_compat_dt[] __initdata = {
 866         "renesas,r8a7740",
 867         NULL,
 868 };
 869
 870 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
 871         .map_io         = r8a7740_map_io,
 872         .init_early     = r8a7740_add_early_devices_dt,
 873         .init_irq       = r8a7740_init_irq,
 874         .handle_irq     = shmobile_handle_irq_intc,
 875         .init_machine   = r8a7740_add_standard_devices_dt,
 876         .init_time      = shmobile_timer_init,
 877         .dt_compat      = r8a7740_boards_compat_dt,
 878 MACHINE_END
 879
 880 #endif /* CONFIG_USE_OF */