Pileus Git - ~andy/linux/blob - arch/arm/mach-shmobile/board-bockw.c

   1 /*
   2  * Bock-W board support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/mfd/tmio.h>
  23 #include <linux/mmc/host.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/pinctrl/machine.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regulator/fixed.h>
  28 #include <linux/regulator/machine.h>
  29 #include <linux/smsc911x.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/spi/flash.h>
  32 #include <media/soc_camera.h>
  33 #include <mach/common.h>
  34 #include <mach/irqs.h>
  35 #include <mach/r8a7778.h>
  36 #include <asm/mach/arch.h>
  37
  38 /*
  39  *      CN9(Upper side) SCIF/RCAN selection
  40  *
  41  *              1,4     3,6
  42  * SW40         SCIF    RCAN
  43  * SW41         SCIF    RCAN
  44  */
  45
  46 /*
  47  * MMC (CN26) pin
  48  *
  49  * SW6  (D2)    3 pin
  50  * SW7  (D5)    ON
  51  * SW8  (D3)    3 pin
  52  * SW10 (D4)    1 pin
  53  * SW12 (CLK)   1 pin
  54  * SW13 (D6)    3 pin
  55  * SW14 (CMD)   ON
  56  * SW15 (D6)    1 pin
  57  * SW16 (D0)    ON
  58  * SW17 (D1)    ON
  59  * SW18 (D7)    3 pin
  60  * SW19 (MMC)   1 pin
  61  */
  62
  63 /* Dummy supplies, where voltage doesn't matter */
  64 static struct regulator_consumer_supply dummy_supplies[] = {
  65         REGULATOR_SUPPLY("vddvario", "smsc911x"),
  66         REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  67 };
  68
  69 static struct smsc911x_platform_config smsc911x_data = {
  70         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  71         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
  72         .flags          = SMSC911X_USE_32BIT,
  73         .phy_interface  = PHY_INTERFACE_MODE_MII,
  74 };
  75
  76 static struct resource smsc911x_resources[] = {
  77         DEFINE_RES_MEM(0x18300000, 0x1000),
  78         DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
  79 };
  80
  81 /* USB */
  82 static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
  83
  84 /* SDHI */
  85 static struct sh_mobile_sdhi_info sdhi0_info = {
  86         .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
  87         .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  88         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
  89 };
  90
  91 static struct sh_eth_plat_data ether_platform_data __initdata = {
  92         .phy            = 0x01,
  93         .edmac_endian   = EDMAC_LITTLE_ENDIAN,
  94         .register_type  = SH_ETH_REG_FAST_RCAR,
  95         .phy_interface  = PHY_INTERFACE_MODE_RMII,
  96         /*
  97          * Although the LINK signal is available on the board, it's connected to
  98          * the link/activity LED output of the PHY, thus the link disappears and
  99          * reappears after each packet.  We'd be better off ignoring such signal
 100          * and getting the link state from the PHY indirectly.
 101          */
 102         .no_ether_link  = 1,
 103 };
 104
 105 /* I2C */
 106 static struct i2c_board_info i2c0_devices[] = {
 107         {
 108                 I2C_BOARD_INFO("rx8581", 0x51),
 109         },
 110 };
 111
 112 /* HSPI*/
 113 static struct mtd_partition m25p80_spi_flash_partitions[] = {
 114         {
 115                 .name   = "data(spi)",
 116                 .size   = 0x0100000,
 117                 .offset = 0,
 118         },
 119 };
 120
 121 static struct flash_platform_data spi_flash_data = {
 122         .name           = "m25p80",
 123         .type           = "s25fl008k",
 124         .parts          = m25p80_spi_flash_partitions,
 125         .nr_parts       = ARRAY_SIZE(m25p80_spi_flash_partitions),
 126 };
 127
 128 static struct spi_board_info spi_board_info[] __initdata = {
 129         {
 130                 .modalias       = "m25p80",
 131                 .max_speed_hz   = 104000000,
 132                 .chip_select    = 0,
 133                 .bus_num        = 0,
 134                 .mode           = SPI_MODE_0,
 135                 .platform_data  = &spi_flash_data,
 136         },
 137 };
 138
 139 /* MMC */
 140 static struct sh_mmcif_plat_data sh_mmcif_plat = {
 141         .sup_pclk       = 0,
 142         .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
 143         .caps           = MMC_CAP_4_BIT_DATA |
 144                           MMC_CAP_8_BIT_DATA |
 145                           MMC_CAP_NEEDS_POLL,
 146 };
 147
 148 static struct rcar_vin_platform_data vin_platform_data __initdata = {
 149         .flags  = RCAR_VIN_BT656,
 150 };
 151
 152 /* In the default configuration both decoders reside on I2C bus 0 */
 153 #define BOCKW_CAMERA(idx)                                               \
 154 static struct i2c_board_info camera##idx##_info = {                     \
 155         I2C_BOARD_INFO("ml86v7667", 0x41 + 2 * (idx)),                  \
 156 };                                                                      \
 157                                                                         \
 158 static struct soc_camera_link iclink##idx##_ml86v7667 __initdata = {    \
 159         .bus_id         = idx,                                          \
 160         .i2c_adapter_id = 0,                                            \
 161         .board_info     = &camera##idx##_info,                          \
 162 }
 163
 164 BOCKW_CAMERA(0);
 165 BOCKW_CAMERA(1);
 166
 167 static const struct pinctrl_map bockw_pinctrl_map[] = {
 168         /* Ether */
 169         PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778",
 170                                   "ether_rmii", "ether"),
 171         /* HSPI0 */
 172         PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
 173                                   "hspi0_a", "hspi0"),
 174         /* MMC */
 175         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
 176                                   "mmc_data8", "mmc"),
 177         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
 178                                   "mmc_ctrl", "mmc"),
 179         /* SCIF0 */
 180         PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
 181                                   "scif0_data_a", "scif0"),
 182         PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
 183                                   "scif0_ctrl", "scif0"),
 184         /* USB */
 185         PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
 186                                   "usb0", "usb0"),
 187         PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
 188                                   "usb1", "usb1"),
 189         /* SDHI0 */
 190         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
 191                                   "sdhi0", "sdhi0"),
 192         /* VIN0 */
 193         PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778",
 194                                   "vin0_clk", "vin0"),
 195         PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778",
 196                                   "vin0_data8", "vin0"),
 197         /* VIN1 */
 198         PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778",
 199                                   "vin1_clk", "vin1"),
 200         PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778",
 201                                   "vin1_data8", "vin1"),
 202 };
 203
 204 #define FPGA    0x18200000
 205 #define IRQ0MR  0x30
 206 #define PFC     0xfffc0000
 207 #define PUPR4   0x110
 208 static void __init bockw_init(void)
 209 {
 210         void __iomem *base;
 211
 212         r8a7778_clock_init();
 213         r8a7778_init_irq_extpin(1);
 214         r8a7778_add_standard_devices();
 215         r8a7778_add_usb_phy_device(&usb_phy_platform_data);
 216         r8a7778_add_ether_device(&ether_platform_data);
 217         r8a7778_add_i2c_device(0);
 218         r8a7778_add_hspi_device(0);
 219         r8a7778_add_mmc_device(&sh_mmcif_plat);
 220         r8a7778_add_vin_device(0, &vin_platform_data);
 221         /* VIN1 has a pin conflict with Ether */
 222         if (!IS_ENABLED(CONFIG_SH_ETH))
 223                 r8a7778_add_vin_device(1, &vin_platform_data);
 224         platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0,
 225                                       &iclink0_ml86v7667,
 226                                       sizeof(iclink0_ml86v7667));
 227         platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1,
 228                                       &iclink1_ml86v7667,
 229                                       sizeof(iclink1_ml86v7667));
 230
 231         i2c_register_board_info(0, i2c0_devices,
 232                                 ARRAY_SIZE(i2c0_devices));
 233         spi_register_board_info(spi_board_info,
 234                                 ARRAY_SIZE(spi_board_info));
 235         pinctrl_register_mappings(bockw_pinctrl_map,
 236                                   ARRAY_SIZE(bockw_pinctrl_map));
 237         r8a7778_pinmux_init();
 238
 239         /* for SMSC */
 240         base = ioremap_nocache(FPGA, SZ_1M);
 241         if (base) {
 242                 /*
 243                  * CAUTION
 244                  *
 245                  * IRQ0/1 is cascaded interrupt from FPGA.
 246                  * it should be cared in the future
 247                  * Now, it is assuming IRQ0 was used only from SMSC.
 248                  */
 249                 u16 val = ioread16(base + IRQ0MR);
 250                 val &= ~(1 << 4); /* enable SMSC911x */
 251                 iowrite16(val, base + IRQ0MR);
 252                 iounmap(base);
 253
 254                 regulator_register_fixed(0, dummy_supplies,
 255                                          ARRAY_SIZE(dummy_supplies));
 256
 257                 platform_device_register_resndata(
 258                         &platform_bus, "smsc911x", -1,
 259                         smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
 260                         &smsc911x_data, sizeof(smsc911x_data));
 261         }
 262
 263         /* for SDHI */
 264         base = ioremap_nocache(PFC, 0x200);
 265         if (base) {
 266                 /*
 267                  * FIXME
 268                  *
 269                  * SDHI CD/WP pin needs pull-up
 270                  */
 271                 iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
 272                 iounmap(base);
 273
 274                 r8a7778_sdhi_init(0, &sdhi0_info);
 275         }
 276 }
 277
 278 static const char *bockw_boards_compat_dt[] __initdata = {
 279         "renesas,bockw",
 280         NULL,
 281 };
 282
 283 DT_MACHINE_START(BOCKW_DT, "bockw")
 284         .init_early     = r8a7778_init_delay,
 285         .init_irq       = r8a7778_init_irq_dt,
 286         .init_machine   = bockw_init,
 287         .init_time      = shmobile_timer_init,
 288         .dt_compat      = bockw_boards_compat_dt,
 289         .init_late      = r8a7778_init_late,
 290 MACHINE_END