Pileus Git - ~andy/linux/blob - arch/arm/mach-s5pc100/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Copyright 2009 Samsung Electronics Co.
   6  *      Byungho Min <bhmin@samsung.com>
   7  *
   8  * Common Codes for S5PC100
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/list.h>
  19 #include <linux/timer.h>
  20 #include <linux/init.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/sysdev.h>
  24 #include <linux/serial_core.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/irq.h>
  29 #include <asm/proc-fns.h>
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33
  34 #include <mach/map.h>
  35 #include <mach/hardware.h>
  36 #include <mach/regs-clock.h>
  37
  38 #include <plat/cpu.h>
  39 #include <plat/devs.h>
  40 #include <plat/clock.h>
  41 #include <plat/sdhci.h>
  42 #include <plat/adc-core.h>
  43 #include <plat/ata-core.h>
  44 #include <plat/fb-core.h>
  45 #include <plat/iic-core.h>
  46 #include <plat/onenand-core.h>
  47 #include <plat/regs-serial.h>
  48
  49 #include "common.h"
  50
  51 static const char name_s5pc100[] = "S5PC100";
  52
  53 static struct cpu_table cpu_ids[] __initdata = {
  54         {
  55                 .idcode         = S5PC100_CPU_ID,
  56                 .idmask         = S5PC100_CPU_MASK,
  57                 .map_io         = s5pc100_map_io,
  58                 .init_clocks    = s5pc100_init_clocks,
  59                 .init_uarts     = s5pc100_init_uarts,
  60                 .init           = s5pc100_init,
  61                 .name           = name_s5pc100,
  62         },
  63 };
  64
  65 /* Initial IO mappings */
  66
  67 static struct map_desc s5pc100_iodesc[] __initdata = {
  68         {
  69                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  70                 .pfn            = __phys_to_pfn(S5PC100_PA_CHIPID),
  71                 .length         = SZ_4K,
  72                 .type           = MT_DEVICE,
  73         }, {
  74                 .virtual        = (unsigned long)S3C_VA_SYS,
  75                 .pfn            = __phys_to_pfn(S5PC100_PA_SYSCON),
  76                 .length         = SZ_64K,
  77                 .type           = MT_DEVICE,
  78         }, {
  79                 .virtual        = (unsigned long)S3C_VA_TIMER,
  80                 .pfn            = __phys_to_pfn(S5PC100_PA_TIMER),
  81                 .length         = SZ_16K,
  82                 .type           = MT_DEVICE,
  83         }, {
  84                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  85                 .pfn            = __phys_to_pfn(S5PC100_PA_WATCHDOG),
  86                 .length         = SZ_4K,
  87                 .type           = MT_DEVICE,
  88         }, {
  89                 .virtual        = (unsigned long)S5P_VA_SROMC,
  90                 .pfn            = __phys_to_pfn(S5PC100_PA_SROMC),
  91                 .length         = SZ_4K,
  92                 .type           = MT_DEVICE,
  93         }, {
  94                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  95                 .pfn            = __phys_to_pfn(S5PC100_PA_SYSTIMER),
  96                 .length         = SZ_16K,
  97                 .type           = MT_DEVICE,
  98         }, {
  99                 .virtual        = (unsigned long)S5P_VA_GPIO,
 100                 .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
 101                 .length         = SZ_4K,
 102                 .type           = MT_DEVICE,
 103         }, {
 104                 .virtual        = (unsigned long)VA_VIC0,
 105                 .pfn            = __phys_to_pfn(S5PC100_PA_VIC0),
 106                 .length         = SZ_16K,
 107                 .type           = MT_DEVICE,
 108         }, {
 109                 .virtual        = (unsigned long)VA_VIC1,
 110                 .pfn            = __phys_to_pfn(S5PC100_PA_VIC1),
 111                 .length         = SZ_16K,
 112                 .type           = MT_DEVICE,
 113         }, {
 114                 .virtual        = (unsigned long)VA_VIC2,
 115                 .pfn            = __phys_to_pfn(S5PC100_PA_VIC2),
 116                 .length         = SZ_16K,
 117                 .type           = MT_DEVICE,
 118         }, {
 119                 .virtual        = (unsigned long)S3C_VA_UART,
 120                 .pfn            = __phys_to_pfn(S3C_PA_UART),
 121                 .length         = SZ_512K,
 122                 .type           = MT_DEVICE,
 123         }, {
 124                 .virtual        = (unsigned long)S5PC100_VA_OTHERS,
 125                 .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
 126                 .length         = SZ_4K,
 127                 .type           = MT_DEVICE,
 128         }
 129 };
 130
 131 static void s5pc100_idle(void)
 132 {
 133         if (!need_resched())
 134                 cpu_do_idle();
 135
 136         local_irq_enable();
 137 }
 138
 139 /*
 140  * s5pc100_map_io
 141  *
 142  * register the standard CPU IO areas
 143  */
 144
 145 void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
 146 {
 147         /* initialize the io descriptors we need for initialization */
 148         iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
 149         if (mach_desc)
 150                 iotable_init(mach_desc, size);
 151
 152         /* detect cpu id and rev. */
 153         s5p_init_cpu(S5P_VA_CHIPID);
 154
 155         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 156 }
 157
 158 void __init s5pc100_map_io(void)
 159 {
 160         /* initialise device information early */
 161         s5pc100_default_sdhci0();
 162         s5pc100_default_sdhci1();
 163         s5pc100_default_sdhci2();
 164
 165         s3c_adc_setname("s3c64xx-adc");
 166
 167         /* the i2c devices are directly compatible with s3c2440 */
 168         s3c_i2c0_setname("s3c2440-i2c");
 169         s3c_i2c1_setname("s3c2440-i2c");
 170
 171         s3c_onenand_setname("s5pc100-onenand");
 172         s3c_fb_setname("s5pc100-fb");
 173         s3c_cfcon_setname("s5pc100-pata");
 174 }
 175
 176 void __init s5pc100_init_clocks(int xtal)
 177 {
 178         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 179
 180         s3c24xx_register_baseclocks(xtal);
 181         s5p_register_clocks(xtal);
 182         s5pc100_register_clocks();
 183         s5pc100_setup_clocks();
 184 }
 185
 186 void __init s5pc100_init_irq(void)
 187 {
 188         u32 vic[] = {~0, ~0, ~0};
 189
 190         /* VIC0, VIC1, and VIC2 are fully populated. */
 191         s5p_init_irq(vic, ARRAY_SIZE(vic));
 192 }
 193
 194 static struct sysdev_class s5pc100_sysclass = {
 195         .name   = "s5pc100-core",
 196 };
 197
 198 static struct sys_device s5pc100_sysdev = {
 199         .cls    = &s5pc100_sysclass,
 200 };
 201
 202 static int __init s5pc100_core_init(void)
 203 {
 204         return sysdev_class_register(&s5pc100_sysclass);
 205 }
 206 core_initcall(s5pc100_core_init);
 207
 208 int __init s5pc100_init(void)
 209 {
 210         printk(KERN_INFO "S5PC100: Initializing architecture\n");
 211
 212         /* set idle function */
 213         pm_idle = s5pc100_idle;
 214
 215         return sysdev_register(&s5pc100_sysdev);
 216 }
 217
 218 /* uart registration process */
 219
 220 void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 221 {
 222         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 223 }