Pileus Git - ~andy/linux/blob - arch/arm/mach-s5p64x0/common.c

   1 /*
   2  * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for S5P64X0 machines
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20 #include <linux/device.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/sched.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/gpio.h>
  26 #include <linux/irq.h>
  27
  28 #include <asm/irq.h>
  29 #include <asm/proc-fns.h>
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33
  34 #include <mach/map.h>
  35 #include <mach/hardware.h>
  36 #include <mach/regs-clock.h>
  37 #include <mach/regs-gpio.h>
  38
  39 #include <plat/cpu.h>
  40 #include <plat/clock.h>
  41 #include <plat/devs.h>
  42 #include <plat/pm.h>
  43 #include <plat/sdhci.h>
  44 #include <plat/adc-core.h>
  45 #include <plat/fb-core.h>
  46 #include <plat/gpio-cfg.h>
  47 #include <plat/regs-irqtype.h>
  48 #include <plat/regs-serial.h>
  49 #include <plat/watchdog-reset.h>
  50
  51 #include "common.h"
  52
  53 static const char name_s5p6440[] = "S5P6440";
  54 static const char name_s5p6450[] = "S5P6450";
  55
  56 static struct cpu_table cpu_ids[] __initdata = {
  57         {
  58                 .idcode         = S5P6440_CPU_ID,
  59                 .idmask         = S5P64XX_CPU_MASK,
  60                 .map_io         = s5p6440_map_io,
  61                 .init_clocks    = s5p6440_init_clocks,
  62                 .init_uarts     = s5p6440_init_uarts,
  63                 .init           = s5p64x0_init,
  64                 .name           = name_s5p6440,
  65         }, {
  66                 .idcode         = S5P6450_CPU_ID,
  67                 .idmask         = S5P64XX_CPU_MASK,
  68                 .map_io         = s5p6450_map_io,
  69                 .init_clocks    = s5p6450_init_clocks,
  70                 .init_uarts     = s5p6450_init_uarts,
  71                 .init           = s5p64x0_init,
  72                 .name           = name_s5p6450,
  73         },
  74 };
  75
  76 /* Initial IO mappings */
  77
  78 static struct map_desc s5p64x0_iodesc[] __initdata = {
  79         {
  80                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  81                 .pfn            = __phys_to_pfn(S5P64X0_PA_CHIPID),
  82                 .length         = SZ_4K,
  83                 .type           = MT_DEVICE,
  84         }, {
  85                 .virtual        = (unsigned long)S3C_VA_SYS,
  86                 .pfn            = __phys_to_pfn(S5P64X0_PA_SYSCON),
  87                 .length         = SZ_64K,
  88                 .type           = MT_DEVICE,
  89         }, {
  90                 .virtual        = (unsigned long)S3C_VA_TIMER,
  91                 .pfn            = __phys_to_pfn(S5P64X0_PA_TIMER),
  92                 .length         = SZ_16K,
  93                 .type           = MT_DEVICE,
  94         }, {
  95                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  96                 .pfn            = __phys_to_pfn(S5P64X0_PA_WDT),
  97                 .length         = SZ_4K,
  98                 .type           = MT_DEVICE,
  99         }, {
 100                 .virtual        = (unsigned long)S5P_VA_SROMC,
 101                 .pfn            = __phys_to_pfn(S5P64X0_PA_SROMC),
 102                 .length         = SZ_4K,
 103                 .type           = MT_DEVICE,
 104         }, {
 105                 .virtual        = (unsigned long)S5P_VA_GPIO,
 106                 .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)VA_VIC0,
 111                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
 112                 .length         = SZ_16K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)VA_VIC1,
 116                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
 117                 .length         = SZ_16K,
 118                 .type           = MT_DEVICE,
 119         },
 120 };
 121
 122 static struct map_desc s5p6440_iodesc[] __initdata = {
 123         {
 124                 .virtual        = (unsigned long)S3C_VA_UART,
 125                 .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
 126                 .length         = SZ_4K,
 127                 .type           = MT_DEVICE,
 128         },
 129 };
 130
 131 static struct map_desc s5p6450_iodesc[] __initdata = {
 132         {
 133                 .virtual        = (unsigned long)S3C_VA_UART,
 134                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
 135                 .length         = SZ_512K,
 136                 .type           = MT_DEVICE,
 137         }, {
 138                 .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
 139                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
 140                 .length         = SZ_4K,
 141                 .type           = MT_DEVICE,
 142         },
 143 };
 144
 145 static void s5p64x0_idle(void)
 146 {
 147         unsigned long val;
 148
 149         val = __raw_readl(S5P64X0_PWR_CFG);
 150         val &= ~(0x3 << 5);
 151         val |= (0x1 << 5);
 152         __raw_writel(val, S5P64X0_PWR_CFG);
 153
 154         cpu_do_idle();
 155 }
 156
 157 /*
 158  * s5p64x0_map_io
 159  *
 160  * register the standard CPU IO areas
 161  */
 162
 163 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
 164 {
 165         /* initialize the io descriptors we need for initialization */
 166         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
 167         if (mach_desc)
 168                 iotable_init(mach_desc, size);
 169
 170         /* detect cpu id and rev. */
 171         s5p_init_cpu(S5P64X0_SYS_ID);
 172
 173         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 174 }
 175
 176 void __init s5p6440_map_io(void)
 177 {
 178         /* initialize any device information early */
 179         s3c_adc_setname("s3c64xx-adc");
 180         s3c_fb_setname("s5p64x0-fb");
 181
 182         s5p64x0_default_sdhci0();
 183         s5p64x0_default_sdhci1();
 184         s5p6440_default_sdhci2();
 185
 186         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
 187         init_consistent_dma_size(SZ_8M);
 188 }
 189
 190 void __init s5p6450_map_io(void)
 191 {
 192         /* initialize any device information early */
 193         s3c_adc_setname("s3c64xx-adc");
 194         s3c_fb_setname("s5p64x0-fb");
 195
 196         s5p64x0_default_sdhci0();
 197         s5p64x0_default_sdhci1();
 198         s5p6450_default_sdhci2();
 199
 200         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
 201         init_consistent_dma_size(SZ_8M);
 202 }
 203
 204 /*
 205  * s5p64x0_init_clocks
 206  *
 207  * register and setup the CPU clocks
 208  */
 209
 210 void __init s5p6440_init_clocks(int xtal)
 211 {
 212         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 213
 214         s3c24xx_register_baseclocks(xtal);
 215         s5p_register_clocks(xtal);
 216         s5p6440_register_clocks();
 217         s5p6440_setup_clocks();
 218 }
 219
 220 void __init s5p6450_init_clocks(int xtal)
 221 {
 222         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 223
 224         s3c24xx_register_baseclocks(xtal);
 225         s5p_register_clocks(xtal);
 226         s5p6450_register_clocks();
 227         s5p6450_setup_clocks();
 228 }
 229
 230 /*
 231  * s5p64x0_init_irq
 232  *
 233  * register the CPU interrupts
 234  */
 235
 236 void __init s5p6440_init_irq(void)
 237 {
 238         /* S5P6440 supports 2 VIC */
 239         u32 vic[2];
 240
 241         /*
 242          * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
 243          * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
 244          */
 245         vic[0] = 0xff800ae7;
 246         vic[1] = 0xffbf23e5;
 247
 248         s5p_init_irq(vic, ARRAY_SIZE(vic));
 249 }
 250
 251 void __init s5p6450_init_irq(void)
 252 {
 253         /* S5P6450 supports only 2 VIC */
 254         u32 vic[2];
 255
 256         /*
 257          * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
 258          * VIC1 is missing IRQ VIC1[12, 14, 23]
 259          */
 260         vic[0] = 0xff9f1fff;
 261         vic[1] = 0xff7fafff;
 262
 263         s5p_init_irq(vic, ARRAY_SIZE(vic));
 264 }
 265
 266 struct bus_type s5p64x0_subsys = {
 267         .name           = "s5p64x0-core",
 268         .dev_name       = "s5p64x0-core",
 269 };
 270
 271 static struct device s5p64x0_dev = {
 272         .bus    = &s5p64x0_subsys,
 273 };
 274
 275 static int __init s5p64x0_core_init(void)
 276 {
 277         return subsys_system_register(&s5p64x0_subsys, NULL);
 278 }
 279 core_initcall(s5p64x0_core_init);
 280
 281 int __init s5p64x0_init(void)
 282 {
 283         printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
 284
 285         /* set idle function */
 286         arm_pm_idle = s5p64x0_idle;
 287
 288         return device_register(&s5p64x0_dev);
 289 }
 290
 291 /* uart registration process */
 292 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 293 {
 294         int uart;
 295
 296         for (uart = 0; uart < no; uart++) {
 297                 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
 298                 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
 299         }
 300
 301         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 302 }
 303
 304 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 305 {
 306         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 307 }
 308
 309 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 310
 311 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
 312 {
 313         int offs = eint_offset(data->irq);
 314         int shift;
 315         u32 ctrl, mask;
 316         u32 newvalue = 0;
 317
 318         if (offs > 15)
 319                 return -EINVAL;
 320
 321         switch (type) {
 322         case IRQ_TYPE_NONE:
 323                 printk(KERN_WARNING "No edge setting!\n");
 324                 break;
 325         case IRQ_TYPE_EDGE_RISING:
 326                 newvalue = S3C2410_EXTINT_RISEEDGE;
 327                 break;
 328         case IRQ_TYPE_EDGE_FALLING:
 329                 newvalue = S3C2410_EXTINT_FALLEDGE;
 330                 break;
 331         case IRQ_TYPE_EDGE_BOTH:
 332                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 333                 break;
 334         case IRQ_TYPE_LEVEL_LOW:
 335                 newvalue = S3C2410_EXTINT_LOWLEV;
 336                 break;
 337         case IRQ_TYPE_LEVEL_HIGH:
 338                 newvalue = S3C2410_EXTINT_HILEV;
 339                 break;
 340         default:
 341                 printk(KERN_ERR "No such irq type %d", type);
 342                 return -EINVAL;
 343         }
 344
 345         shift = (offs / 2) * 4;
 346         mask = 0x7 << shift;
 347
 348         ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
 349         ctrl |= newvalue << shift;
 350         __raw_writel(ctrl, S5P64X0_EINT0CON0);
 351
 352         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
 353         if (soc_is_s5p6450())
 354                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
 355         else
 356                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
 357
 358         return 0;
 359 }
 360
 361 /*
 362  * s5p64x0_irq_demux_eint
 363  *
 364  * This function demuxes the IRQ from the group0 external interrupts,
 365  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
 366  * the specific handlers s5p64x0_irq_demux_eintX_Y.
 367  */
 368 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
 369 {
 370         u32 status = __raw_readl(S5P64X0_EINT0PEND);
 371         u32 mask = __raw_readl(S5P64X0_EINT0MASK);
 372         unsigned int irq;
 373
 374         status &= ~mask;
 375         status >>= start;
 376         status &= (1 << (end - start + 1)) - 1;
 377
 378         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 379                 if (status & 1)
 380                         generic_handle_irq(irq);
 381                 status >>= 1;
 382         }
 383 }
 384
 385 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 386 {
 387         s5p64x0_irq_demux_eint(0, 3);
 388 }
 389
 390 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 391 {
 392         s5p64x0_irq_demux_eint(4, 11);
 393 }
 394
 395 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
 396                                         struct irq_desc *desc)
 397 {
 398         s5p64x0_irq_demux_eint(12, 15);
 399 }
 400
 401 static int s5p64x0_alloc_gc(void)
 402 {
 403         struct irq_chip_generic *gc;
 404         struct irq_chip_type *ct;
 405
 406         gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
 407                                     S5P_VA_GPIO, handle_level_irq);
 408         if (!gc) {
 409                 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
 410                         "external interrupts failed\n", __func__);
 411                 return -EINVAL;
 412         }
 413
 414         ct = gc->chip_types;
 415         ct->chip.irq_ack = irq_gc_ack_set_bit;
 416         ct->chip.irq_mask = irq_gc_mask_set_bit;
 417         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 418         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
 419         ct->chip.irq_set_wake = s3c_irqext_wake;
 420         ct->regs.ack = EINT0PEND_OFFSET;
 421         ct->regs.mask = EINT0MASK_OFFSET;
 422         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
 423                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 424         return 0;
 425 }
 426
 427 static int __init s5p64x0_init_irq_eint(void)
 428 {
 429         int ret = s5p64x0_alloc_gc();
 430         irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
 431         irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
 432         irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
 433
 434         return ret;
 435 }
 436 arch_initcall(s5p64x0_init_irq_eint);
 437
 438 void s5p64x0_restart(char mode, const char *cmd)
 439 {
 440         if (mode != 's')
 441                 arch_wdt_reset();
 442
 443         soft_restart(0);
 444 }