2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for S5P64X0 machines
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
20 #include <linux/device.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/gpio.h>
26 #include <linux/irq.h>
27 #include <linux/reboot.h>
30 #include <asm/proc-fns.h>
31 #include <asm/system_misc.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/irq.h>
37 #include <mach/hardware.h>
38 #include <mach/regs-clock.h>
39 #include <mach/regs-gpio.h>
42 #include <plat/clock.h>
43 #include <plat/devs.h>
45 #include <plat/sdhci.h>
46 #include <plat/adc-core.h>
47 #include <plat/fb-core.h>
48 #include <plat/spi-core.h>
49 #include <plat/gpio-cfg.h>
50 #include <plat/regs-irqtype.h>
51 #include <plat/regs-serial.h>
52 #include <plat/watchdog-reset.h>
56 static const char name_s5p6440[] = "S5P6440";
57 static const char name_s5p6450[] = "S5P6450";
59 static struct cpu_table cpu_ids[] __initdata = {
61 .idcode = S5P6440_CPU_ID,
62 .idmask = S5P64XX_CPU_MASK,
63 .map_io = s5p6440_map_io,
64 .init_clocks = s5p6440_init_clocks,
65 .init_uarts = s5p6440_init_uarts,
69 .idcode = S5P6450_CPU_ID,
70 .idmask = S5P64XX_CPU_MASK,
71 .map_io = s5p6450_map_io,
72 .init_clocks = s5p6450_init_clocks,
73 .init_uarts = s5p6450_init_uarts,
79 /* Initial IO mappings */
81 static struct map_desc s5p64x0_iodesc[] __initdata = {
83 .virtual = (unsigned long)S5P_VA_CHIPID,
84 .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID),
88 .virtual = (unsigned long)S3C_VA_SYS,
89 .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON),
93 .virtual = (unsigned long)S3C_VA_TIMER,
94 .pfn = __phys_to_pfn(S5P64X0_PA_TIMER),
98 .virtual = (unsigned long)S3C_VA_WATCHDOG,
99 .pfn = __phys_to_pfn(S5P64X0_PA_WDT),
103 .virtual = (unsigned long)S5P_VA_SROMC,
104 .pfn = __phys_to_pfn(S5P64X0_PA_SROMC),
108 .virtual = (unsigned long)S5P_VA_GPIO,
109 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
113 .virtual = (unsigned long)VA_VIC0,
114 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
118 .virtual = (unsigned long)VA_VIC1,
119 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
125 static struct map_desc s5p6440_iodesc[] __initdata = {
127 .virtual = (unsigned long)S3C_VA_UART,
128 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
134 static struct map_desc s5p6450_iodesc[] __initdata = {
136 .virtual = (unsigned long)S3C_VA_UART,
137 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
141 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
142 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
148 static void s5p64x0_idle(void)
152 val = __raw_readl(S5P64X0_PWR_CFG);
155 __raw_writel(val, S5P64X0_PWR_CFG);
163 * register the standard CPU IO areas
166 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
168 /* initialize the io descriptors we need for initialization */
169 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
171 iotable_init(mach_desc, size);
173 /* detect cpu id and rev. */
174 s5p_init_cpu(S5P64X0_SYS_ID);
176 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
177 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
181 void __init s5p6440_map_io(void)
183 /* initialize any device information early */
184 s3c_adc_setname("s3c64xx-adc");
185 s3c_fb_setname("s5p64x0-fb");
186 s3c64xx_spi_setname("s5p64x0-spi");
188 s5p64x0_default_sdhci0();
189 s5p64x0_default_sdhci1();
190 s5p6440_default_sdhci2();
192 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
195 void __init s5p6450_map_io(void)
197 /* initialize any device information early */
198 s3c_adc_setname("s3c64xx-adc");
199 s3c_fb_setname("s5p64x0-fb");
200 s3c64xx_spi_setname("s5p64x0-spi");
202 s5p64x0_default_sdhci0();
203 s5p64x0_default_sdhci1();
204 s5p6450_default_sdhci2();
206 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
210 * s5p64x0_init_clocks
212 * register and setup the CPU clocks
215 void __init s5p6440_init_clocks(int xtal)
217 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
219 s3c24xx_register_baseclocks(xtal);
220 s5p_register_clocks(xtal);
221 s5p6440_register_clocks();
222 s5p6440_setup_clocks();
225 void __init s5p6450_init_clocks(int xtal)
227 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
229 s3c24xx_register_baseclocks(xtal);
230 s5p_register_clocks(xtal);
231 s5p6450_register_clocks();
232 s5p6450_setup_clocks();
238 * register the CPU interrupts
241 void __init s5p6440_init_irq(void)
243 /* S5P6440 supports 2 VIC */
247 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
248 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
253 s5p_init_irq(vic, ARRAY_SIZE(vic));
256 void __init s5p6450_init_irq(void)
258 /* S5P6450 supports only 2 VIC */
262 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
263 * VIC1 is missing IRQ VIC1[12, 14, 23]
268 s5p_init_irq(vic, ARRAY_SIZE(vic));
271 struct bus_type s5p64x0_subsys = {
272 .name = "s5p64x0-core",
273 .dev_name = "s5p64x0-core",
276 static struct device s5p64x0_dev = {
277 .bus = &s5p64x0_subsys,
280 static int __init s5p64x0_core_init(void)
282 return subsys_system_register(&s5p64x0_subsys, NULL);
284 core_initcall(s5p64x0_core_init);
286 int __init s5p64x0_init(void)
288 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
290 /* set idle function */
291 arm_pm_idle = s5p64x0_idle;
293 return device_register(&s5p64x0_dev);
296 /* uart registration process */
297 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
301 for (uart = 0; uart < no; uart++) {
302 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
303 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
306 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
309 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
311 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
314 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
316 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
318 int offs = eint_offset(data->irq);
328 printk(KERN_WARNING "No edge setting!\n");
330 case IRQ_TYPE_EDGE_RISING:
331 newvalue = S3C2410_EXTINT_RISEEDGE;
333 case IRQ_TYPE_EDGE_FALLING:
334 newvalue = S3C2410_EXTINT_FALLEDGE;
336 case IRQ_TYPE_EDGE_BOTH:
337 newvalue = S3C2410_EXTINT_BOTHEDGE;
339 case IRQ_TYPE_LEVEL_LOW:
340 newvalue = S3C2410_EXTINT_LOWLEV;
342 case IRQ_TYPE_LEVEL_HIGH:
343 newvalue = S3C2410_EXTINT_HILEV;
346 printk(KERN_ERR "No such irq type %d", type);
350 shift = (offs / 2) * 4;
353 ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
354 ctrl |= newvalue << shift;
355 __raw_writel(ctrl, S5P64X0_EINT0CON0);
357 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
358 if (soc_is_s5p6450())
359 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
361 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
367 * s5p64x0_irq_demux_eint
369 * This function demuxes the IRQ from the group0 external interrupts,
370 * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
371 * the specific handlers s5p64x0_irq_demux_eintX_Y.
373 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
375 u32 status = __raw_readl(S5P64X0_EINT0PEND);
376 u32 mask = __raw_readl(S5P64X0_EINT0MASK);
381 status &= (1 << (end - start + 1)) - 1;
383 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
385 generic_handle_irq(irq);
390 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
392 s5p64x0_irq_demux_eint(0, 3);
395 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
397 s5p64x0_irq_demux_eint(4, 11);
400 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
401 struct irq_desc *desc)
403 s5p64x0_irq_demux_eint(12, 15);
406 static int s5p64x0_alloc_gc(void)
408 struct irq_chip_generic *gc;
409 struct irq_chip_type *ct;
411 gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
412 S5P_VA_GPIO, handle_level_irq);
414 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
415 "external interrupts failed\n", __func__);
420 ct->chip.irq_ack = irq_gc_ack_set_bit;
421 ct->chip.irq_mask = irq_gc_mask_set_bit;
422 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
423 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
424 ct->chip.irq_set_wake = s3c_irqext_wake;
425 ct->regs.ack = EINT0PEND_OFFSET;
426 ct->regs.mask = EINT0MASK_OFFSET;
427 irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
428 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
432 static int __init s5p64x0_init_irq_eint(void)
434 int ret = s5p64x0_alloc_gc();
435 irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
436 irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
437 irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
441 arch_initcall(s5p64x0_init_irq_eint);
443 void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
445 if (mode != REBOOT_SOFT)