Pileus Git - ~andy/linux/blob - arch/arm/mach-s3c24xx/mach-osiris.c

   1 /*
   2  * Copyright (c) 2005-2008 Simtec Electronics
   3  *      http://armlinux.simtec.co.uk/
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/list.h>
  15 #include <linux/timer.h>
  16 #include <linux/init.h>
  17 #include <linux/gpio.h>
  18 #include <linux/device.h>
  19 #include <linux/syscore_ops.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/clk.h>
  22 #include <linux/i2c.h>
  23 #include <linux/io.h>
  24 #include <linux/platform_device.h>
  25
  26 #include <linux/i2c/tps65010.h>
  27
  28 #include <asm/mach-types.h>
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/irq.h>
  32 #include <asm/irq.h>
  33
  34 #include <linux/platform_data/mtd-nand-s3c2410.h>
  35 #include <linux/platform_data/i2c-s3c2410.h>
  36
  37 #include <linux/mtd/mtd.h>
  38 #include <linux/mtd/nand.h>
  39 #include <linux/mtd/nand_ecc.h>
  40 #include <linux/mtd/partitions.h>
  41
  42 #include <plat/clock.h>
  43 #include <plat/cpu.h>
  44 #include <plat/cpu-freq.h>
  45 #include <plat/devs.h>
  46 #include <plat/gpio-cfg.h>
  47 #include <plat/regs-serial.h>
  48
  49 #include <mach/hardware.h>
  50 #include <mach/regs-gpio.h>
  51 #include <mach/regs-lcd.h>
  52
  53 #include "common.h"
  54 #include "osiris.h"
  55 #include "regs-mem.h"
  56
  57 /* onboard perihperal map */
  58
  59 static struct map_desc osiris_iodesc[] __initdata = {
  60   /* ISA IO areas (may be over-written later) */
  61
  62   {
  63           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  64           .pfn          = __phys_to_pfn(S3C2410_CS5),
  65           .length       = SZ_16M,
  66           .type         = MT_DEVICE,
  67   }, {
  68           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  69           .pfn          = __phys_to_pfn(S3C2410_CS5),
  70           .length       = SZ_16M,
  71           .type         = MT_DEVICE,
  72   },
  73
  74   /* CPLD control registers */
  75
  76   {
  77           .virtual      = (u32)OSIRIS_VA_CTRL0,
  78           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  79           .length       = SZ_16K,
  80           .type         = MT_DEVICE,
  81   }, {
  82           .virtual      = (u32)OSIRIS_VA_CTRL1,
  83           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  84           .length       = SZ_16K,
  85           .type         = MT_DEVICE,
  86   }, {
  87           .virtual      = (u32)OSIRIS_VA_CTRL2,
  88           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  89           .length       = SZ_16K,
  90           .type         = MT_DEVICE,
  91   }, {
  92           .virtual      = (u32)OSIRIS_VA_IDREG,
  93           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  94           .length       = SZ_16K,
  95           .type         = MT_DEVICE,
  96   },
  97 };
  98
  99 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 100 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 101 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 102
 103 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 104         [0] = {
 105                 .hwport      = 0,
 106                 .flags       = 0,
 107                 .ucon        = UCON,
 108                 .ulcon       = ULCON,
 109                 .ufcon       = UFCON,
 110                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 111         },
 112         [1] = {
 113                 .hwport      = 1,
 114                 .flags       = 0,
 115                 .ucon        = UCON,
 116                 .ulcon       = ULCON,
 117                 .ufcon       = UFCON,
 118                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 119         },
 120         [2] = {
 121                 .hwport      = 2,
 122                 .flags       = 0,
 123                 .ucon        = UCON,
 124                 .ulcon       = ULCON,
 125                 .ufcon       = UFCON,
 126                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 127         }
 128 };
 129
 130 /* NAND Flash on Osiris board */
 131
 132 static int external_map[]   = { 2 };
 133 static int chip0_map[]      = { 0 };
 134 static int chip1_map[]      = { 1 };
 135
 136 static struct mtd_partition __initdata osiris_default_nand_part[] = {
 137         [0] = {
 138                 .name   = "Boot Agent",
 139                 .size   = SZ_16K,
 140                 .offset = 0,
 141         },
 142         [1] = {
 143                 .name   = "/boot",
 144                 .size   = SZ_4M - SZ_16K,
 145                 .offset = SZ_16K,
 146         },
 147         [2] = {
 148                 .name   = "user1",
 149                 .offset = SZ_4M,
 150                 .size   = SZ_32M - SZ_4M,
 151         },
 152         [3] = {
 153                 .name   = "user2",
 154                 .offset = SZ_32M,
 155                 .size   = MTDPART_SIZ_FULL,
 156         }
 157 };
 158
 159 static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
 160         [0] = {
 161                 .name   = "Boot Agent",
 162                 .size   = SZ_128K,
 163                 .offset = 0,
 164         },
 165         [1] = {
 166                 .name   = "/boot",
 167                 .size   = SZ_4M - SZ_128K,
 168                 .offset = SZ_128K,
 169         },
 170         [2] = {
 171                 .name   = "user1",
 172                 .offset = SZ_4M,
 173                 .size   = SZ_32M - SZ_4M,
 174         },
 175         [3] = {
 176                 .name   = "user2",
 177                 .offset = SZ_32M,
 178                 .size   = MTDPART_SIZ_FULL,
 179         }
 180 };
 181
 182 /* the Osiris has 3 selectable slots for nand-flash, the two
 183  * on-board chip areas, as well as the external slot.
 184  *
 185  * Note, there is no current hot-plug support for the External
 186  * socket.
 187 */
 188
 189 static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
 190         [1] = {
 191                 .name           = "External",
 192                 .nr_chips       = 1,
 193                 .nr_map         = external_map,
 194                 .options        = NAND_SCAN_SILENT_NODEV,
 195                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 196                 .partitions     = osiris_default_nand_part,
 197         },
 198         [0] = {
 199                 .name           = "chip0",
 200                 .nr_chips       = 1,
 201                 .nr_map         = chip0_map,
 202                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 203                 .partitions     = osiris_default_nand_part,
 204         },
 205         [2] = {
 206                 .name           = "chip1",
 207                 .nr_chips       = 1,
 208                 .nr_map         = chip1_map,
 209                 .options        = NAND_SCAN_SILENT_NODEV,
 210                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 211                 .partitions     = osiris_default_nand_part,
 212         },
 213 };
 214
 215 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 216 {
 217         unsigned int tmp;
 218
 219         slot = set->nr_map[slot] & 3;
 220
 221         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 222                  slot, set, set->nr_map);
 223
 224         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 225         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 226         tmp |= slot;
 227
 228         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 229
 230         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 231 }
 232
 233 static struct s3c2410_platform_nand __initdata osiris_nand_info = {
 234         .tacls          = 25,
 235         .twrph0         = 60,
 236         .twrph1         = 60,
 237         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 238         .sets           = osiris_nand_sets,
 239         .select_chip    = osiris_nand_select,
 240 };
 241
 242 /* PCMCIA control and configuration */
 243
 244 static struct resource osiris_pcmcia_resource[] = {
 245         [0] = DEFINE_RES_MEM(0x0f000000, SZ_1M),
 246         [1] = DEFINE_RES_MEM(0x0c000000, SZ_1M),
 247 };
 248
 249 static struct platform_device osiris_pcmcia = {
 250         .name           = "osiris-pcmcia",
 251         .id             = -1,
 252         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 253         .resource       = osiris_pcmcia_resource,
 254 };
 255
 256 /* Osiris power management device */
 257
 258 #ifdef CONFIG_PM
 259 static unsigned char pm_osiris_ctrl0;
 260
 261 static int osiris_pm_suspend(void)
 262 {
 263         unsigned int tmp;
 264
 265         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
 266         tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
 267
 268         /* ensure correct NAND slot is selected on resume */
 269         if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
 270                 tmp |= 2;
 271
 272         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 273
 274         /* ensure that an nRESET is not generated on resume. */
 275         gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
 276         gpio_free(S3C2410_GPA(21));
 277
 278         return 0;
 279 }
 280
 281 static void osiris_pm_resume(void)
 282 {
 283         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
 284                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
 285
 286         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 287
 288         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 289 }
 290
 291 #else
 292 #define osiris_pm_suspend NULL
 293 #define osiris_pm_resume NULL
 294 #endif
 295
 296 static struct syscore_ops osiris_pm_syscore_ops = {
 297         .suspend        = osiris_pm_suspend,
 298         .resume         = osiris_pm_resume,
 299 };
 300
 301 /* Link for DVS driver to TPS65011 */
 302
 303 static void osiris_tps_release(struct device *dev)
 304 {
 305         /* static device, do not need to release anything */
 306 }
 307
 308 static struct platform_device osiris_tps_device = {
 309         .name   = "osiris-dvs",
 310         .id     = -1,
 311         .dev.release = osiris_tps_release,
 312 };
 313
 314 static int osiris_tps_setup(struct i2c_client *client, void *context)
 315 {
 316         osiris_tps_device.dev.parent = &client->dev;
 317         return platform_device_register(&osiris_tps_device);
 318 }
 319
 320 static int osiris_tps_remove(struct i2c_client *client, void *context)
 321 {
 322         platform_device_unregister(&osiris_tps_device);
 323         return 0;
 324 }
 325
 326 static struct tps65010_board osiris_tps_board = {
 327         .base           = -1,   /* GPIO can go anywhere at the moment */
 328         .setup          = osiris_tps_setup,
 329         .teardown       = osiris_tps_remove,
 330 };
 331
 332 /* I2C devices fitted. */
 333
 334 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 335         {
 336                 I2C_BOARD_INFO("tps65011", 0x48),
 337                 .irq    = IRQ_EINT20,
 338                 .platform_data = &osiris_tps_board,
 339         },
 340 };
 341
 342 /* Standard Osiris devices */
 343
 344 static struct platform_device *osiris_devices[] __initdata = {
 345         &s3c_device_i2c0,
 346         &s3c_device_wdt,
 347         &s3c_device_nand,
 348         &osiris_pcmcia,
 349 };
 350
 351 static struct clk *osiris_clocks[] __initdata = {
 352         &s3c24xx_dclk0,
 353         &s3c24xx_dclk1,
 354         &s3c24xx_clkout0,
 355         &s3c24xx_clkout1,
 356         &s3c24xx_uclk,
 357 };
 358
 359 static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
 360         .refresh        = 7800, /* refresh period is 7.8usec */
 361         .auto_io        = 1,
 362         .need_io        = 1,
 363 };
 364
 365 static void __init osiris_map_io(void)
 366 {
 367         unsigned long flags;
 368
 369         /* initialise the clocks */
 370
 371         s3c24xx_dclk0.parent = &clk_upll;
 372         s3c24xx_dclk0.rate   = 12*1000*1000;
 373
 374         s3c24xx_dclk1.parent = &clk_upll;
 375         s3c24xx_dclk1.rate   = 24*1000*1000;
 376
 377         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 378         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 379
 380         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 381
 382         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 383
 384         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 385         s3c24xx_init_clocks(0);
 386         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 387
 388         /* check for the newer revision boards with large page nand */
 389
 390         if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
 391                 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
 392                        __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
 393                 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
 394                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
 395         } else {
 396                 /* write-protect line to the NAND */
 397                 gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
 398                 gpio_free(S3C2410_GPA(0));
 399         }
 400
 401         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 402
 403         local_irq_save(flags);
 404         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 405         local_irq_restore(flags);
 406 }
 407
 408 static void __init osiris_init(void)
 409 {
 410         register_syscore_ops(&osiris_pm_syscore_ops);
 411
 412         s3c_i2c0_set_platdata(NULL);
 413         s3c_nand_set_platdata(&osiris_nand_info);
 414
 415         s3c_cpufreq_setboard(&osiris_cpufreq);
 416
 417         i2c_register_board_info(0, osiris_i2c_devs,
 418                                 ARRAY_SIZE(osiris_i2c_devs));
 419
 420         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 421 };
 422
 423 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 424         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 425         .atag_offset    = 0x100,
 426         .map_io         = osiris_map_io,
 427         .init_irq       = s3c24xx_init_irq,
 428         .init_machine   = osiris_init,
 429         .init_time      = s3c24xx_timer_init,
 430         .restart        = s3c244x_restart,
 431 MACHINE_END