Pileus Git - ~andy/linux/blob - arch/arm/mach-s3c24xx/irq-s3c2416.c

   1 /* linux/arch/arm/mach-s3c2416/irq.c
   2  *
   3  * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
   4  *      as part of OpenInkpot project
   5  * Copyright (c) 2009 Promwad Innovation Company
   6  *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  *
  22 */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/ioport.h>
  28 #include <linux/device.h>
  29 #include <linux/io.h>
  30 #include <linux/syscore_ops.h>
  31
  32 #include <mach/hardware.h>
  33 #include <asm/irq.h>
  34
  35 #include <asm/mach/irq.h>
  36
  37 #include <mach/regs-irq.h>
  38 #include <mach/regs-gpio.h>
  39
  40 #include <plat/cpu.h>
  41 #include <plat/pm.h>
  42 #include <plat/irq.h>
  43
  44 #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
  45
  46 static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
  47 {
  48         unsigned int subsrc, submsk;
  49         unsigned int end;
  50
  51         /* read the current pending interrupts, and the mask
  52          * for what it is available */
  53
  54         subsrc = __raw_readl(S3C2410_SUBSRCPND);
  55         submsk = __raw_readl(S3C2410_INTSUBMSK);
  56
  57         subsrc  &= ~submsk;
  58         subsrc >>= (irq - S3C2410_IRQSUB(0));
  59         subsrc  &= (1 << len)-1;
  60
  61         end = len + irq;
  62
  63         for (; irq < end && subsrc; irq++) {
  64                 if (subsrc & 1)
  65                         generic_handle_irq(irq);
  66
  67                 subsrc >>= 1;
  68         }
  69 }
  70
  71 /* WDT/AC97 sub interrupts */
  72
  73 static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
  74 {
  75         s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
  76 }
  77
  78 #define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
  79 #define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
  80
  81 static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
  82 {
  83         s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
  84 }
  85
  86 static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
  87 {
  88         s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
  89 }
  90
  91 static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
  92 {
  93         s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
  94 }
  95
  96 static struct irq_chip s3c2416_irq_wdtac97 = {
  97         .irq_mask       = s3c2416_irq_wdtac97_mask,
  98         .irq_unmask     = s3c2416_irq_wdtac97_unmask,
  99         .irq_ack        = s3c2416_irq_wdtac97_ack,
 100 };
 101
 102 /* LCD sub interrupts */
 103
 104 static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
 105 {
 106         s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
 107 }
 108
 109 #define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
 110 #define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
 111
 112 static void s3c2416_irq_lcd_mask(struct irq_data *data)
 113 {
 114         s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
 115 }
 116
 117 static void s3c2416_irq_lcd_unmask(struct irq_data *data)
 118 {
 119         s3c_irqsub_unmask(data->irq, INTMSK_LCD);
 120 }
 121
 122 static void s3c2416_irq_lcd_ack(struct irq_data *data)
 123 {
 124         s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
 125 }
 126
 127 static struct irq_chip s3c2416_irq_lcd = {
 128         .irq_mask       = s3c2416_irq_lcd_mask,
 129         .irq_unmask     = s3c2416_irq_lcd_unmask,
 130         .irq_ack        = s3c2416_irq_lcd_ack,
 131 };
 132
 133 /* DMA sub interrupts */
 134
 135 static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
 136 {
 137         s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
 138 }
 139
 140 #define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
 141 #define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
 142
 143
 144 static void s3c2416_irq_dma_mask(struct irq_data *data)
 145 {
 146         s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
 147 }
 148
 149 static void s3c2416_irq_dma_unmask(struct irq_data *data)
 150 {
 151         s3c_irqsub_unmask(data->irq, INTMSK_DMA);
 152 }
 153
 154 static void s3c2416_irq_dma_ack(struct irq_data *data)
 155 {
 156         s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
 157 }
 158
 159 static struct irq_chip s3c2416_irq_dma = {
 160         .irq_mask       = s3c2416_irq_dma_mask,
 161         .irq_unmask     = s3c2416_irq_dma_unmask,
 162         .irq_ack        = s3c2416_irq_dma_ack,
 163 };
 164
 165 /* UART3 sub interrupts */
 166
 167 static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
 168 {
 169         s3c2416_irq_demux(IRQ_S3C2443_RX3, 3);
 170 }
 171
 172 #define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
 173 #define SUBMSK_UART3    (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
 174
 175 static void s3c2416_irq_uart3_mask(struct irq_data *data)
 176 {
 177         s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
 178 }
 179
 180 static void s3c2416_irq_uart3_unmask(struct irq_data *data)
 181 {
 182         s3c_irqsub_unmask(data->irq, INTMSK_UART3);
 183 }
 184
 185 static void s3c2416_irq_uart3_ack(struct irq_data *data)
 186 {
 187         s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
 188 }
 189
 190 static struct irq_chip s3c2416_irq_uart3 = {
 191         .irq_mask       = s3c2416_irq_uart3_mask,
 192         .irq_unmask     = s3c2416_irq_uart3_unmask,
 193         .irq_ack        = s3c2416_irq_uart3_ack,
 194 };
 195
 196 /* second interrupt register */
 197
 198 static inline void s3c2416_irq_ack_second(struct irq_data *data)
 199 {
 200         unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
 201
 202         __raw_writel(bitval, S3C2416_SRCPND2);
 203         __raw_writel(bitval, S3C2416_INTPND2);
 204 }
 205
 206 static void s3c2416_irq_mask_second(struct irq_data *data)
 207 {
 208         unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
 209         unsigned long mask;
 210
 211         mask = __raw_readl(S3C2416_INTMSK2);
 212         mask |= bitval;
 213         __raw_writel(mask, S3C2416_INTMSK2);
 214 }
 215
 216 static void s3c2416_irq_unmask_second(struct irq_data *data)
 217 {
 218         unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
 219         unsigned long mask;
 220
 221         mask = __raw_readl(S3C2416_INTMSK2);
 222         mask &= ~bitval;
 223         __raw_writel(mask, S3C2416_INTMSK2);
 224 }
 225
 226 struct irq_chip s3c2416_irq_second = {
 227         .irq_ack        = s3c2416_irq_ack_second,
 228         .irq_mask       = s3c2416_irq_mask_second,
 229         .irq_unmask     = s3c2416_irq_unmask_second,
 230 };
 231
 232
 233 /* IRQ initialisation code */
 234
 235 static int __init s3c2416_add_sub(unsigned int base,
 236                                    void (*demux)(unsigned int,
 237                                                  struct irq_desc *),
 238                                    struct irq_chip *chip,
 239                                    unsigned int start, unsigned int end)
 240 {
 241         unsigned int irqno;
 242
 243         irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
 244         irq_set_chained_handler(base, demux);
 245
 246         for (irqno = start; irqno <= end; irqno++) {
 247                 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
 248                 set_irq_flags(irqno, IRQF_VALID);
 249         }
 250
 251         return 0;
 252 }
 253
 254 static void __init s3c2416_irq_add_second(void)
 255 {
 256         unsigned long pend;
 257         unsigned long last;
 258         int irqno;
 259         int i;
 260
 261         /* first, clear all interrupts pending... */
 262         last = 0;
 263         for (i = 0; i < 4; i++) {
 264                 pend = __raw_readl(S3C2416_INTPND2);
 265
 266                 if (pend == 0 || pend == last)
 267                         break;
 268
 269                 __raw_writel(pend, S3C2416_SRCPND2);
 270                 __raw_writel(pend, S3C2416_INTPND2);
 271                 printk(KERN_INFO "irq: clearing pending status %08x\n",
 272                        (int)pend);
 273                 last = pend;
 274         }
 275
 276         for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
 277                 switch (irqno) {
 278                 case IRQ_S3C2416_RESERVED2:
 279                 case IRQ_S3C2416_RESERVED3:
 280                         /* no IRQ here */
 281                         break;
 282                 default:
 283                         irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
 284                                                  handle_edge_irq);
 285                         set_irq_flags(irqno, IRQF_VALID);
 286                 }
 287         }
 288 }
 289
 290 static int __init s3c2416_irq_add(struct device *dev,
 291                                   struct subsys_interface *sif)
 292 {
 293         printk(KERN_INFO "S3C2416: IRQ Support\n");
 294
 295         s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
 296                         IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
 297
 298         s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
 299                         &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
 300
 301         s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
 302                         &s3c2416_irq_uart3,
 303                         IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
 304
 305         s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
 306                         &s3c2416_irq_wdtac97,
 307                         IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
 308
 309         s3c2416_irq_add_second();
 310
 311         return 0;
 312 }
 313
 314 static struct subsys_interface s3c2416_irq_interface = {
 315         .name           = "s3c2416_irq",
 316         .subsys         = &s3c2416_subsys,
 317         .add_dev        = s3c2416_irq_add,
 318 };
 319
 320 static int __init s3c2416_irq_init(void)
 321 {
 322         return subsys_interface_register(&s3c2416_irq_interface);
 323 }
 324
 325 arch_initcall(s3c2416_irq_init);
 326
 327 #ifdef CONFIG_PM
 328 static struct sleep_save irq_save[] = {
 329         SAVE_ITEM(S3C2416_INTMSK2),
 330 };
 331
 332 int s3c2416_irq_suspend(void)
 333 {
 334         s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
 335
 336         return 0;
 337 }
 338
 339 void s3c2416_irq_resume(void)
 340 {
 341         s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
 342 }
 343
 344 struct syscore_ops s3c2416_irq_syscore_ops = {
 345         .suspend        = s3c2416_irq_suspend,
 346         .resume         = s3c2416_irq_resume,
 347 };
 348 #endif