Pileus Git - ~andy/linux/blob - arch/arm/mach-s3c24xx/dma-s3c2440.c

   1 /* linux/arch/arm/mach-s3c2440/dma.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2440 DMA selection
   7  *
   8  * http://armlinux.simtec.co.uk/
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/serial_core.h>
  19
  20 #include <mach/map.h>
  21 #include <mach/dma.h>
  22
  23 #include <plat/dma-s3c24xx.h>
  24 #include <plat/cpu.h>
  25
  26 #include <plat/regs-serial.h>
  27 #include <mach/regs-gpio.h>
  28 #include <plat/regs-ac97.h>
  29 #include <plat/regs-dma.h>
  30 #include <mach/regs-lcd.h>
  31 #include <plat/regs-iis.h>
  32 #include <plat/regs-spi.h>
  33
  34 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
  35         [DMACH_XD0] = {
  36                 .name           = "xdreq0",
  37                 .channels[0]    = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
  38         },
  39         [DMACH_XD1] = {
  40                 .name           = "xdreq1",
  41                 .channels[1]    = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
  42         },
  43         [DMACH_SDI] = {
  44                 .name           = "sdi",
  45                 .channels[0]    = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
  46                 .channels[1]    = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
  47                 .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
  48                 .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
  49         },
  50         [DMACH_SPI0] = {
  51                 .name           = "spi0",
  52                 .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
  53         },
  54         [DMACH_SPI1] = {
  55                 .name           = "spi1",
  56                 .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
  57         },
  58         [DMACH_UART0] = {
  59                 .name           = "uart0",
  60                 .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
  61         },
  62         [DMACH_UART1] = {
  63                 .name           = "uart1",
  64                 .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
  65         },
  66         [DMACH_UART2] = {
  67                 .name           = "uart2",
  68                 .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
  69         },
  70         [DMACH_TIMER] = {
  71                 .name           = "timer",
  72                 .channels[0]    = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
  73                 .channels[2]    = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
  74                 .channels[3]    = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
  75         },
  76         [DMACH_I2S_IN] = {
  77                 .name           = "i2s-sdi",
  78                 .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
  79                 .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
  80         },
  81         [DMACH_I2S_OUT] = {
  82                 .name           = "i2s-sdo",
  83                 .channels[0]    = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
  84                 .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
  85         },
  86         [DMACH_PCM_IN] = {
  87                 .name           = "pcm-in",
  88                 .channels[0]    = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
  89                 .channels[2]    = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
  90         },
  91         [DMACH_PCM_OUT] = {
  92                 .name           = "pcm-out",
  93                 .channels[1]    = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
  94                 .channels[3]    = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
  95         },
  96         [DMACH_MIC_IN] = {
  97                 .name           = "mic-in",
  98                 .channels[2]    = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
  99                 .channels[3]    = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
 100         },
 101         [DMACH_USB_EP1] = {
 102                 .name           = "usb-ep1",
 103                 .channels[0]    = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
 104         },
 105         [DMACH_USB_EP2] = {
 106                 .name           = "usb-ep2",
 107                 .channels[1]    = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
 108         },
 109         [DMACH_USB_EP3] = {
 110                 .name           = "usb-ep3",
 111                 .channels[2]    = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
 112         },
 113         [DMACH_USB_EP4] = {
 114                 .name           = "usb-ep4",
 115                 .channels[3]    = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
 116         },
 117 };
 118
 119 static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
 120                                struct s3c24xx_dma_map *map)
 121 {
 122         chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
 123 }
 124
 125 static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
 126         .select         = s3c2440_dma_select,
 127         .dcon_mask      = 7 << 24,
 128         .map            = s3c2440_dma_mappings,
 129         .map_size       = ARRAY_SIZE(s3c2440_dma_mappings),
 130 };
 131
 132 static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
 133         .channels       = {
 134                 [DMACH_SDI]     = {
 135                         .list   = {
 136                                 [0]     = 3 | DMA_CH_VALID,
 137                                 [1]     = 2 | DMA_CH_VALID,
 138                                 [2]     = 1 | DMA_CH_VALID,
 139                                 [3]     = 0 | DMA_CH_VALID,
 140                         },
 141                 },
 142                 [DMACH_I2S_IN]  = {
 143                         .list   = {
 144                                 [0]     = 1 | DMA_CH_VALID,
 145                                 [1]     = 2 | DMA_CH_VALID,
 146                         },
 147                 },
 148                 [DMACH_I2S_OUT] = {
 149                         .list   = {
 150                                 [0]     = 2 | DMA_CH_VALID,
 151                                 [1]     = 1 | DMA_CH_VALID,
 152                         },
 153                 },
 154                 [DMACH_PCM_IN] = {
 155                         .list   = {
 156                                 [0]     = 2 | DMA_CH_VALID,
 157                                 [1]     = 1 | DMA_CH_VALID,
 158                         },
 159                 },
 160                 [DMACH_PCM_OUT] = {
 161                         .list   = {
 162                                 [0]     = 1 | DMA_CH_VALID,
 163                                 [1]     = 3 | DMA_CH_VALID,
 164                         },
 165                 },
 166                 [DMACH_MIC_IN] = {
 167                         .list   = {
 168                                 [0]     = 3 | DMA_CH_VALID,
 169                                 [1]     = 2 | DMA_CH_VALID,
 170                         },
 171                 },
 172         },
 173 };
 174
 175 static int __init s3c2440_dma_add(struct device *dev,
 176                                   struct subsys_interface *sif)
 177 {
 178         s3c2410_dma_init();
 179         s3c24xx_dma_order_set(&s3c2440_dma_order);
 180         return s3c24xx_dma_init_map(&s3c2440_dma_sel);
 181 }
 182
 183 static struct subsys_interface s3c2440_dma_interface = {
 184         .name           = "s3c2440_dma",
 185         .subsys         = &s3c2440_subsys,
 186         .add_dev        = s3c2440_dma_add,
 187 };
 188
 189 static int __init s3c2440_dma_init(void)
 190 {
 191         return subsys_interface_register(&s3c2440_dma_interface);
 192 }
 193
 194 arch_initcall(s3c2440_dma_init);
 195