Pileus Git - ~andy/linux/blob - arch/arm/mach-s3c2440/mach-osiris.c

   1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
   2  *
   3  * Copyright (c) 2005-2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/gpio.h>
  19 #include <linux/device.h>
  20 #include <linux/syscore_ops.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/clk.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25
  26 #include <linux/i2c/tps65010.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30 #include <asm/mach/irq.h>
  31
  32 #include <mach/osiris-map.h>
  33 #include <mach/osiris-cpld.h>
  34
  35 #include <mach/hardware.h>
  36 #include <asm/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <plat/cpu-freq.h>
  40 #include <plat/regs-serial.h>
  41 #include <mach/regs-gpio.h>
  42 #include <mach/regs-mem.h>
  43 #include <mach/regs-lcd.h>
  44 #include <plat/nand.h>
  45 #include <plat/iic.h>
  46
  47 #include <linux/mtd/mtd.h>
  48 #include <linux/mtd/nand.h>
  49 #include <linux/mtd/nand_ecc.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 #include <plat/gpio-cfg.h>
  53 #include <plat/clock.h>
  54 #include <plat/devs.h>
  55 #include <plat/cpu.h>
  56
  57 #include "common.h"
  58
  59 /* onboard perihperal map */
  60
  61 static struct map_desc osiris_iodesc[] __initdata = {
  62   /* ISA IO areas (may be over-written later) */
  63
  64   {
  65           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  66           .pfn          = __phys_to_pfn(S3C2410_CS5),
  67           .length       = SZ_16M,
  68           .type         = MT_DEVICE,
  69   }, {
  70           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  71           .pfn          = __phys_to_pfn(S3C2410_CS5),
  72           .length       = SZ_16M,
  73           .type         = MT_DEVICE,
  74   },
  75
  76   /* CPLD control registers */
  77
  78   {
  79           .virtual      = (u32)OSIRIS_VA_CTRL0,
  80           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  81           .length       = SZ_16K,
  82           .type         = MT_DEVICE,
  83   }, {
  84           .virtual      = (u32)OSIRIS_VA_CTRL1,
  85           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  86           .length       = SZ_16K,
  87           .type         = MT_DEVICE,
  88   }, {
  89           .virtual      = (u32)OSIRIS_VA_CTRL2,
  90           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  91           .length       = SZ_16K,
  92           .type         = MT_DEVICE,
  93   }, {
  94           .virtual      = (u32)OSIRIS_VA_IDREG,
  95           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  96           .length       = SZ_16K,
  97           .type         = MT_DEVICE,
  98   },
  99 };
 100
 101 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 102 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 103 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 104
 105 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 106         [0] = {
 107                 .hwport      = 0,
 108                 .flags       = 0,
 109                 .ucon        = UCON,
 110                 .ulcon       = ULCON,
 111                 .ufcon       = UFCON,
 112                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 113         },
 114         [1] = {
 115                 .hwport      = 1,
 116                 .flags       = 0,
 117                 .ucon        = UCON,
 118                 .ulcon       = ULCON,
 119                 .ufcon       = UFCON,
 120                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 121         },
 122         [2] = {
 123                 .hwport      = 2,
 124                 .flags       = 0,
 125                 .ucon        = UCON,
 126                 .ulcon       = ULCON,
 127                 .ufcon       = UFCON,
 128                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 129         }
 130 };
 131
 132 /* NAND Flash on Osiris board */
 133
 134 static int external_map[]   = { 2 };
 135 static int chip0_map[]      = { 0 };
 136 static int chip1_map[]      = { 1 };
 137
 138 static struct mtd_partition __initdata osiris_default_nand_part[] = {
 139         [0] = {
 140                 .name   = "Boot Agent",
 141                 .size   = SZ_16K,
 142                 .offset = 0,
 143         },
 144         [1] = {
 145                 .name   = "/boot",
 146                 .size   = SZ_4M - SZ_16K,
 147                 .offset = SZ_16K,
 148         },
 149         [2] = {
 150                 .name   = "user1",
 151                 .offset = SZ_4M,
 152                 .size   = SZ_32M - SZ_4M,
 153         },
 154         [3] = {
 155                 .name   = "user2",
 156                 .offset = SZ_32M,
 157                 .size   = MTDPART_SIZ_FULL,
 158         }
 159 };
 160
 161 static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
 162         [0] = {
 163                 .name   = "Boot Agent",
 164                 .size   = SZ_128K,
 165                 .offset = 0,
 166         },
 167         [1] = {
 168                 .name   = "/boot",
 169                 .size   = SZ_4M - SZ_128K,
 170                 .offset = SZ_128K,
 171         },
 172         [2] = {
 173                 .name   = "user1",
 174                 .offset = SZ_4M,
 175                 .size   = SZ_32M - SZ_4M,
 176         },
 177         [3] = {
 178                 .name   = "user2",
 179                 .offset = SZ_32M,
 180                 .size   = MTDPART_SIZ_FULL,
 181         }
 182 };
 183
 184 /* the Osiris has 3 selectable slots for nand-flash, the two
 185  * on-board chip areas, as well as the external slot.
 186  *
 187  * Note, there is no current hot-plug support for the External
 188  * socket.
 189 */
 190
 191 static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
 192         [1] = {
 193                 .name           = "External",
 194                 .nr_chips       = 1,
 195                 .nr_map         = external_map,
 196                 .options        = NAND_SCAN_SILENT_NODEV,
 197                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 198                 .partitions     = osiris_default_nand_part,
 199         },
 200         [0] = {
 201                 .name           = "chip0",
 202                 .nr_chips       = 1,
 203                 .nr_map         = chip0_map,
 204                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 205                 .partitions     = osiris_default_nand_part,
 206         },
 207         [2] = {
 208                 .name           = "chip1",
 209                 .nr_chips       = 1,
 210                 .nr_map         = chip1_map,
 211                 .options        = NAND_SCAN_SILENT_NODEV,
 212                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 213                 .partitions     = osiris_default_nand_part,
 214         },
 215 };
 216
 217 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 218 {
 219         unsigned int tmp;
 220
 221         slot = set->nr_map[slot] & 3;
 222
 223         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 224                  slot, set, set->nr_map);
 225
 226         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 227         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 228         tmp |= slot;
 229
 230         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 231
 232         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 233 }
 234
 235 static struct s3c2410_platform_nand __initdata osiris_nand_info = {
 236         .tacls          = 25,
 237         .twrph0         = 60,
 238         .twrph1         = 60,
 239         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 240         .sets           = osiris_nand_sets,
 241         .select_chip    = osiris_nand_select,
 242 };
 243
 244 /* PCMCIA control and configuration */
 245
 246 static struct resource osiris_pcmcia_resource[] = {
 247         [0] = {
 248                 .start  = 0x0f000000,
 249                 .end    = 0x0f100000,
 250                 .flags  = IORESOURCE_MEM,
 251         },
 252         [1] = {
 253                 .start  = 0x0c000000,
 254                 .end    = 0x0c100000,
 255                 .flags  = IORESOURCE_MEM,
 256         }
 257 };
 258
 259 static struct platform_device osiris_pcmcia = {
 260         .name           = "osiris-pcmcia",
 261         .id             = -1,
 262         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 263         .resource       = osiris_pcmcia_resource,
 264 };
 265
 266 /* Osiris power management device */
 267
 268 #ifdef CONFIG_PM
 269 static unsigned char pm_osiris_ctrl0;
 270
 271 static int osiris_pm_suspend(void)
 272 {
 273         unsigned int tmp;
 274
 275         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
 276         tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
 277
 278         /* ensure correct NAND slot is selected on resume */
 279         if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
 280                 tmp |= 2;
 281
 282         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 283
 284         /* ensure that an nRESET is not generated on resume. */
 285         s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
 286         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
 287
 288         return 0;
 289 }
 290
 291 static void osiris_pm_resume(void)
 292 {
 293         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
 294                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
 295
 296         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 297
 298         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 299 }
 300
 301 #else
 302 #define osiris_pm_suspend NULL
 303 #define osiris_pm_resume NULL
 304 #endif
 305
 306 static struct syscore_ops osiris_pm_syscore_ops = {
 307         .suspend        = osiris_pm_suspend,
 308         .resume         = osiris_pm_resume,
 309 };
 310
 311 /* Link for DVS driver to TPS65011 */
 312
 313 static void osiris_tps_release(struct device *dev)
 314 {
 315         /* static device, do not need to release anything */
 316 }
 317
 318 static struct platform_device osiris_tps_device = {
 319         .name   = "osiris-dvs",
 320         .id     = -1,
 321         .dev.release = osiris_tps_release,
 322 };
 323
 324 static int osiris_tps_setup(struct i2c_client *client, void *context)
 325 {
 326         osiris_tps_device.dev.parent = &client->dev;
 327         return platform_device_register(&osiris_tps_device);
 328 }
 329
 330 static int osiris_tps_remove(struct i2c_client *client, void *context)
 331 {
 332         platform_device_unregister(&osiris_tps_device);
 333         return 0;
 334 }
 335
 336 static struct tps65010_board osiris_tps_board = {
 337         .base           = -1,   /* GPIO can go anywhere at the moment */
 338         .setup          = osiris_tps_setup,
 339         .teardown       = osiris_tps_remove,
 340 };
 341
 342 /* I2C devices fitted. */
 343
 344 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 345         {
 346                 I2C_BOARD_INFO("tps65011", 0x48),
 347                 .irq    = IRQ_EINT20,
 348                 .platform_data = &osiris_tps_board,
 349         },
 350 };
 351
 352 /* Standard Osiris devices */
 353
 354 static struct platform_device *osiris_devices[] __initdata = {
 355         &s3c_device_i2c0,
 356         &s3c_device_wdt,
 357         &s3c_device_nand,
 358         &osiris_pcmcia,
 359 };
 360
 361 static struct clk *osiris_clocks[] __initdata = {
 362         &s3c24xx_dclk0,
 363         &s3c24xx_dclk1,
 364         &s3c24xx_clkout0,
 365         &s3c24xx_clkout1,
 366         &s3c24xx_uclk,
 367 };
 368
 369 static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
 370         .refresh        = 7800, /* refresh period is 7.8usec */
 371         .auto_io        = 1,
 372         .need_io        = 1,
 373 };
 374
 375 static void __init osiris_map_io(void)
 376 {
 377         unsigned long flags;
 378
 379         /* initialise the clocks */
 380
 381         s3c24xx_dclk0.parent = &clk_upll;
 382         s3c24xx_dclk0.rate   = 12*1000*1000;
 383
 384         s3c24xx_dclk1.parent = &clk_upll;
 385         s3c24xx_dclk1.rate   = 24*1000*1000;
 386
 387         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 388         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 389
 390         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 391
 392         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 393
 394         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 395         s3c24xx_init_clocks(0);
 396         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 397
 398         /* check for the newer revision boards with large page nand */
 399
 400         if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
 401                 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
 402                        __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
 403                 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
 404                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
 405         } else {
 406                 /* write-protect line to the NAND */
 407                 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
 408         }
 409
 410         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 411
 412         local_irq_save(flags);
 413         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 414         local_irq_restore(flags);
 415 }
 416
 417 static void __init osiris_init(void)
 418 {
 419         register_syscore_ops(&osiris_pm_syscore_ops);
 420
 421         s3c_i2c0_set_platdata(NULL);
 422         s3c_nand_set_platdata(&osiris_nand_info);
 423
 424         s3c_cpufreq_setboard(&osiris_cpufreq);
 425
 426         i2c_register_board_info(0, osiris_i2c_devs,
 427                                 ARRAY_SIZE(osiris_i2c_devs));
 428
 429         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 430 };
 431
 432 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 433         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 434         .atag_offset    = 0x100,
 435         .map_io         = osiris_map_io,
 436         .init_irq       = s3c24xx_init_irq,
 437         .init_machine   = osiris_init,
 438         .timer          = &s3c24xx_timer,
 439         .restart        = s3c2440_restart,
 440 MACHINE_END