Pileus Git - ~andy/linux/blob - arch/arm/mach-s3c2416/clock.c

   1 /* linux/arch/arm/mach-s3c2416/clock.c
   2  *
   3  * Copyright (c) 2010 Simtec Electronics
   4  * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
   5  *
   6  * S3C2416 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16
  17 #include <plat/s3c2416.h>
  18 #include <plat/s3c2443.h>
  19 #include <plat/clock.h>
  20 #include <plat/clock-clksrc.h>
  21 #include <plat/cpu.h>
  22
  23 #include <plat/cpu-freq.h>
  24 #include <plat/pll6553x.h>
  25 #include <plat/pll.h>
  26
  27 #include <asm/mach/map.h>
  28
  29 #include <mach/regs-clock.h>
  30 #include <mach/regs-s3c2443-clock.h>
  31
  32 static unsigned int armdiv[8] = {
  33         [0] = 1,
  34         [1] = 2,
  35         [2] = 3,
  36         [3] = 4,
  37         [5] = 6,
  38         [7] = 8,
  39 };
  40
  41 static struct clksrc_clk hsspi_eplldiv = {
  42         .clk = {
  43                 .name   = "hsspi-eplldiv",
  44                 .parent = &clk_esysclk.clk,
  45                 .ctrlbit = (1 << 14),
  46                 .enable = s3c2443_clkcon_enable_s,
  47         },
  48         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
  49 };
  50
  51 static struct clk *hsspi_sources[] = {
  52         [0] = &hsspi_eplldiv.clk,
  53         [1] = NULL, /* to fix */
  54 };
  55
  56 static struct clksrc_clk hsspi_mux = {
  57         .clk    = {
  58                 .name   = "hsspi-if",
  59         },
  60         .sources = &(struct clksrc_sources) {
  61                 .sources = hsspi_sources,
  62                 .nr_sources = ARRAY_SIZE(hsspi_sources),
  63         },
  64         .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
  65 };
  66
  67 static struct clksrc_clk hsmmc_div[] = {
  68         [0] = {
  69                 .clk = {
  70                         .name   = "hsmmc-div",
  71                         .devname        = "s3c-sdhci.0",
  72                         .parent = &clk_esysclk.clk,
  73                 },
  74                 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
  75         },
  76         [1] = {
  77                 .clk = {
  78                         .name   = "hsmmc-div",
  79                         .devname        = "s3c-sdhci.1",
  80                         .parent = &clk_esysclk.clk,
  81                 },
  82                 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
  83         },
  84 };
  85
  86 static struct clksrc_clk hsmmc_mux[] = {
  87         [0] = {
  88                 .clk    = {
  89                         .name   = "hsmmc-if",
  90                         .devname        = "s3c-sdhci.0",
  91                         .ctrlbit = (1 << 6),
  92                         .enable = s3c2443_clkcon_enable_s,
  93                 },
  94                 .sources = &(struct clksrc_sources) {
  95                         .nr_sources = 2,
  96                         .sources = (struct clk *[]) {
  97                                 [0] = &hsmmc_div[0].clk,
  98                                 [1] = NULL, /* to fix */
  99                         },
 100                 },
 101                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
 102         },
 103         [1] = {
 104                 .clk    = {
 105                         .name   = "hsmmc-if",
 106                         .devname        = "s3c-sdhci.1",
 107                         .ctrlbit = (1 << 12),
 108                         .enable = s3c2443_clkcon_enable_s,
 109                 },
 110                 .sources = &(struct clksrc_sources) {
 111                         .nr_sources = 2,
 112                         .sources = (struct clk *[]) {
 113                                 [0] = &hsmmc_div[1].clk,
 114                                 [1] = NULL, /* to fix */
 115                         },
 116                 },
 117                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
 118         },
 119 };
 120
 121 static struct clk hsmmc0_clk = {
 122         .name           = "hsmmc",
 123         .devname        = "s3c-sdhci.0",
 124         .parent         = &clk_h,
 125         .enable         = s3c2443_clkcon_enable_h,
 126         .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
 127 };
 128
 129 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
 130 {
 131         clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
 132
 133         return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
 134 }
 135
 136 void __init_or_cpufreq s3c2416_setup_clocks(void)
 137 {
 138         s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
 139 }
 140
 141
 142 static struct clksrc_clk *clksrcs[] __initdata = {
 143         &hsspi_eplldiv,
 144         &hsspi_mux,
 145         &hsmmc_div[0],
 146         &hsmmc_div[1],
 147         &hsmmc_mux[0],
 148         &hsmmc_mux[1],
 149 };
 150
 151 void __init s3c2416_init_clocks(int xtal)
 152 {
 153         u32 epllcon = __raw_readl(S3C2443_EPLLCON);
 154         u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
 155         int ptr;
 156
 157         /* s3c2416 EPLL compatible with s3c64xx */
 158         clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
 159
 160         clk_epll.parent = &clk_epllref.clk;
 161
 162         s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
 163
 164         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 165                 s3c_register_clksrc(clksrcs[ptr], 1);
 166
 167         s3c24xx_register_clock(&hsmmc0_clk);
 168
 169         s3c_pwmclk_init();
 170
 171 }