Pileus Git - ~andy/linux/blob - arch/arm/mach-s3c2416/clock.c

   1 /* linux/arch/arm/mach-s3c2416/clock.c
   2  *
   3  * Copyright (c) 2010 Simtec Electronics
   4  * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
   5  *
   6  * S3C2416 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16
  17 #include <plat/s3c2416.h>
  18 #include <plat/s3c2443.h>
  19 #include <plat/clock.h>
  20 #include <plat/clock-clksrc.h>
  21 #include <plat/cpu.h>
  22
  23 #include <plat/cpu-freq.h>
  24 #include <plat/pll.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <mach/regs-clock.h>
  29 #include <mach/regs-s3c2443-clock.h>
  30
  31 static unsigned int armdiv[8] = {
  32         [0] = 1,
  33         [1] = 2,
  34         [2] = 3,
  35         [3] = 4,
  36         [5] = 6,
  37         [7] = 8,
  38 };
  39
  40 static struct clksrc_clk hsspi_eplldiv = {
  41         .clk = {
  42                 .name   = "hsspi-eplldiv",
  43                 .parent = &clk_esysclk.clk,
  44                 .ctrlbit = (1 << 14),
  45                 .enable = s3c2443_clkcon_enable_s,
  46         },
  47         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
  48 };
  49
  50 static struct clk *hsspi_sources[] = {
  51         [0] = &hsspi_eplldiv.clk,
  52         [1] = NULL, /* to fix */
  53 };
  54
  55 static struct clksrc_clk hsspi_mux = {
  56         .clk    = {
  57                 .name   = "hsspi-if",
  58         },
  59         .sources = &(struct clksrc_sources) {
  60                 .sources = hsspi_sources,
  61                 .nr_sources = ARRAY_SIZE(hsspi_sources),
  62         },
  63         .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
  64 };
  65
  66 static struct clksrc_clk hsmmc_div[] = {
  67         [0] = {
  68                 .clk = {
  69                         .name   = "hsmmc-div",
  70                         .devname        = "s3c-sdhci.0",
  71                         .parent = &clk_esysclk.clk,
  72                 },
  73                 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
  74         },
  75         [1] = {
  76                 .clk = {
  77                         .name   = "hsmmc-div",
  78                         .devname        = "s3c-sdhci.1",
  79                         .parent = &clk_esysclk.clk,
  80                 },
  81                 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
  82         },
  83 };
  84
  85 static struct clksrc_clk hsmmc_mux[] = {
  86         [0] = {
  87                 .clk    = {
  88                         .name   = "hsmmc-if",
  89                         .devname        = "s3c-sdhci.0",
  90                         .ctrlbit = (1 << 6),
  91                         .enable = s3c2443_clkcon_enable_s,
  92                 },
  93                 .sources = &(struct clksrc_sources) {
  94                         .nr_sources = 2,
  95                         .sources = (struct clk *[]) {
  96                                 [0] = &hsmmc_div[0].clk,
  97                                 [1] = NULL, /* to fix */
  98                         },
  99                 },
 100                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
 101         },
 102         [1] = {
 103                 .clk    = {
 104                         .name   = "hsmmc-if",
 105                         .devname        = "s3c-sdhci.1",
 106                         .ctrlbit = (1 << 12),
 107                         .enable = s3c2443_clkcon_enable_s,
 108                 },
 109                 .sources = &(struct clksrc_sources) {
 110                         .nr_sources = 2,
 111                         .sources = (struct clk *[]) {
 112                                 [0] = &hsmmc_div[1].clk,
 113                                 [1] = NULL, /* to fix */
 114                         },
 115                 },
 116                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
 117         },
 118 };
 119
 120 static struct clk hsmmc0_clk = {
 121         .name           = "hsmmc",
 122         .devname        = "s3c-sdhci.0",
 123         .parent         = &clk_h,
 124         .enable         = s3c2443_clkcon_enable_h,
 125         .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
 126 };
 127
 128 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
 129 {
 130         clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
 131
 132         return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
 133 }
 134
 135 void __init_or_cpufreq s3c2416_setup_clocks(void)
 136 {
 137         s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
 138 }
 139
 140
 141 static struct clksrc_clk *clksrcs[] __initdata = {
 142         &hsspi_eplldiv,
 143         &hsspi_mux,
 144         &hsmmc_div[0],
 145         &hsmmc_div[1],
 146         &hsmmc_mux[0],
 147         &hsmmc_mux[1],
 148 };
 149
 150 void __init s3c2416_init_clocks(int xtal)
 151 {
 152         u32 epllcon = __raw_readl(S3C2443_EPLLCON);
 153         u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
 154         int ptr;
 155
 156         /* s3c2416 EPLL compatible with s3c64xx */
 157         clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
 158
 159         clk_epll.parent = &clk_epllref.clk;
 160
 161         s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
 162
 163         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 164                 s3c_register_clksrc(clksrcs[ptr], 1);
 165
 166         s3c24xx_register_clock(&hsmmc0_clk);
 167
 168         s3c_pwmclk_init();
 169
 170 }