1 /* linux/arch/arm/mach-s3c2416/clock.c
3 * Copyright (c) 2010 Simtec Electronics
4 * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
6 * S3C2416 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/clk.h>
17 #include <plat/s3c2416.h>
18 #include <plat/s3c2443.h>
19 #include <plat/clock.h>
20 #include <plat/clock-clksrc.h>
23 #include <plat/cpu-freq.h>
26 #include <asm/mach/map.h>
28 #include <mach/regs-clock.h>
29 #include <mach/regs-s3c2443-clock.h>
31 static unsigned int armdiv[8] = {
40 static struct clksrc_clk hsspi_eplldiv = {
42 .name = "hsspi-eplldiv",
43 .parent = &clk_esysclk.clk,
45 .enable = s3c2443_clkcon_enable_s,
47 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
50 static struct clk *hsspi_sources[] = {
51 [0] = &hsspi_eplldiv.clk,
52 [1] = NULL, /* to fix */
55 static struct clksrc_clk hsspi_mux = {
59 .sources = &(struct clksrc_sources) {
60 .sources = hsspi_sources,
61 .nr_sources = ARRAY_SIZE(hsspi_sources),
63 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
66 static struct clksrc_clk hsmmc_div[] = {
70 .devname = "s3c-sdhci.0",
71 .parent = &clk_esysclk.clk,
73 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
78 .devname = "s3c-sdhci.1",
79 .parent = &clk_esysclk.clk,
81 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
85 static struct clksrc_clk hsmmc_mux[] = {
89 .devname = "s3c-sdhci.0",
91 .enable = s3c2443_clkcon_enable_s,
93 .sources = &(struct clksrc_sources) {
95 .sources = (struct clk *[]) {
96 [0] = &hsmmc_div[0].clk,
97 [1] = NULL, /* to fix */
100 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
105 .devname = "s3c-sdhci.1",
106 .ctrlbit = (1 << 12),
107 .enable = s3c2443_clkcon_enable_s,
109 .sources = &(struct clksrc_sources) {
111 .sources = (struct clk *[]) {
112 [0] = &hsmmc_div[1].clk,
113 [1] = NULL, /* to fix */
116 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
120 static struct clk hsmmc0_clk = {
122 .devname = "s3c-sdhci.0",
124 .enable = s3c2443_clkcon_enable_h,
125 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
128 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
130 clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
132 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
135 void __init_or_cpufreq s3c2416_setup_clocks(void)
137 s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
141 static struct clksrc_clk *clksrcs[] __initdata = {
150 void __init s3c2416_init_clocks(int xtal)
152 u32 epllcon = __raw_readl(S3C2443_EPLLCON);
153 u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
156 /* s3c2416 EPLL compatible with s3c64xx */
157 clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
159 clk_epll.parent = &clk_epllref.clk;
161 s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
163 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
164 s3c_register_clksrc(clksrcs[ptr], 1);
166 s3c24xx_register_clock(&hsmmc0_clk);