Pileus Git - ~andy/linux/blob - arch/arm/mach-s3c2416/clock.c

   1 /* linux/arch/arm/mach-s3c2416/clock.c
   2  *
   3  * Copyright (c) 2010 Simtec Electronics
   4  * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
   5  *
   6  * S3C2416 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16
  17 #include <plat/s3c2416.h>
  18 #include <plat/s3c2443.h>
  19 #include <plat/clock.h>
  20 #include <plat/clock-clksrc.h>
  21 #include <plat/cpu.h>
  22
  23 #include <plat/cpu-freq.h>
  24 #include <plat/pll.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <mach/regs-clock.h>
  29 #include <mach/regs-s3c2443-clock.h>
  30
  31 static unsigned int armdiv[8] = {
  32         [0] = 1,
  33         [1] = 2,
  34         [2] = 3,
  35         [3] = 4,
  36         [5] = 6,
  37         [7] = 8,
  38 };
  39
  40 static struct clksrc_clk hsmmc_div[] = {
  41         [0] = {
  42                 .clk = {
  43                         .name   = "hsmmc-div",
  44                         .devname        = "s3c-sdhci.0",
  45                         .parent = &clk_esysclk.clk,
  46                 },
  47                 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
  48         },
  49         [1] = {
  50                 .clk = {
  51                         .name   = "hsmmc-div",
  52                         .devname        = "s3c-sdhci.1",
  53                         .parent = &clk_esysclk.clk,
  54                 },
  55                 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
  56         },
  57 };
  58
  59 static struct clksrc_clk hsmmc_mux[] = {
  60         [0] = {
  61                 .clk    = {
  62                         .name   = "hsmmc-if",
  63                         .devname        = "s3c-sdhci.0",
  64                         .ctrlbit = (1 << 6),
  65                         .enable = s3c2443_clkcon_enable_s,
  66                 },
  67                 .sources = &(struct clksrc_sources) {
  68                         .nr_sources = 2,
  69                         .sources = (struct clk *[]) {
  70                                 [0] = &hsmmc_div[0].clk,
  71                                 [1] = NULL, /* to fix */
  72                         },
  73                 },
  74                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
  75         },
  76         [1] = {
  77                 .clk    = {
  78                         .name   = "hsmmc-if",
  79                         .devname        = "s3c-sdhci.1",
  80                         .ctrlbit = (1 << 12),
  81                         .enable = s3c2443_clkcon_enable_s,
  82                 },
  83                 .sources = &(struct clksrc_sources) {
  84                         .nr_sources = 2,
  85                         .sources = (struct clk *[]) {
  86                                 [0] = &hsmmc_div[1].clk,
  87                                 [1] = NULL, /* to fix */
  88                         },
  89                 },
  90                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
  91         },
  92 };
  93
  94 static struct clk hsmmc0_clk = {
  95         .name           = "hsmmc",
  96         .devname        = "s3c-sdhci.0",
  97         .parent         = &clk_h,
  98         .enable         = s3c2443_clkcon_enable_h,
  99         .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
 100 };
 101
 102 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
 103 {
 104         clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
 105
 106         return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
 107 }
 108
 109 void __init_or_cpufreq s3c2416_setup_clocks(void)
 110 {
 111         s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
 112 }
 113
 114
 115 static struct clksrc_clk *clksrcs[] __initdata = {
 116         &hsmmc_div[0],
 117         &hsmmc_div[1],
 118         &hsmmc_mux[0],
 119         &hsmmc_mux[1],
 120 };
 121
 122 void __init s3c2416_init_clocks(int xtal)
 123 {
 124         u32 epllcon = __raw_readl(S3C2443_EPLLCON);
 125         u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
 126         int ptr;
 127
 128         /* s3c2416 EPLL compatible with s3c64xx */
 129         clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
 130
 131         clk_epll.parent = &clk_epllref.clk;
 132
 133         s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
 134
 135         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 136                 s3c_register_clksrc(clksrcs[ptr], 1);
 137
 138         s3c24xx_register_clock(&hsmmc0_clk);
 139
 140         s3c_pwmclk_init();
 141
 142 }