Pileus Git - ~andy/linux/blob - arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30 #include <linux/io.h>
  31
  32 #include <asm/system.h>
  33 #include <mach/hardware.h>
  34 #include <asm/irq.h>
  35 #include <asm/leds.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/hardware/arm_timer.h>
  38 #include <asm/hardware/icst307.h>
  39
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/flash.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/mmc.h>
  45
  46 #include <asm/hardware/gic.h>
  47
  48 #include "core.h"
  49 #include "clock.h"
  50
  51 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  52
  53 /* used by entry-macro.S */
  54 void __iomem *gic_cpu_base_addr;
  55
  56 /*
  57  * This is the RealView sched_clock implementation.  This has
  58  * a resolution of 41.7ns, and a maximum value of about 179s.
  59  */
  60 unsigned long long sched_clock(void)
  61 {
  62         unsigned long long v;
  63
  64         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  65         do_div(v, 3);
  66
  67         return v;
  68 }
  69
  70
  71 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  72
  73 static int realview_flash_init(void)
  74 {
  75         u32 val;
  76
  77         val = __raw_readl(REALVIEW_FLASHCTRL);
  78         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  79         __raw_writel(val, REALVIEW_FLASHCTRL);
  80
  81         return 0;
  82 }
  83
  84 static void realview_flash_exit(void)
  85 {
  86         u32 val;
  87
  88         val = __raw_readl(REALVIEW_FLASHCTRL);
  89         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  90         __raw_writel(val, REALVIEW_FLASHCTRL);
  91 }
  92
  93 static void realview_flash_set_vpp(int on)
  94 {
  95         u32 val;
  96
  97         val = __raw_readl(REALVIEW_FLASHCTRL);
  98         if (on)
  99                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 100         else
 101                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 102         __raw_writel(val, REALVIEW_FLASHCTRL);
 103 }
 104
 105 static struct flash_platform_data realview_flash_data = {
 106         .map_name               = "cfi_probe",
 107         .width                  = 4,
 108         .init                   = realview_flash_init,
 109         .exit                   = realview_flash_exit,
 110         .set_vpp                = realview_flash_set_vpp,
 111 };
 112
 113 struct platform_device realview_flash_device = {
 114         .name                   = "armflash",
 115         .id                     = 0,
 116         .dev                    = {
 117                 .platform_data  = &realview_flash_data,
 118         },
 119 };
 120
 121 int realview_flash_register(struct resource *res, u32 num)
 122 {
 123         realview_flash_device.resource = res;
 124         realview_flash_device.num_resources = num;
 125         return platform_device_register(&realview_flash_device);
 126 }
 127
 128 static struct resource realview_i2c_resource = {
 129         .start          = REALVIEW_I2C_BASE,
 130         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 131         .flags          = IORESOURCE_MEM,
 132 };
 133
 134 struct platform_device realview_i2c_device = {
 135         .name           = "versatile-i2c",
 136         .id             = -1,
 137         .num_resources  = 1,
 138         .resource       = &realview_i2c_resource,
 139 };
 140
 141 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 142
 143 static unsigned int realview_mmc_status(struct device *dev)
 144 {
 145         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 146         u32 mask;
 147
 148         if (adev->res.start == REALVIEW_MMCI0_BASE)
 149                 mask = 1;
 150         else
 151                 mask = 2;
 152
 153         return readl(REALVIEW_SYSMCI) & mask;
 154 }
 155
 156 struct mmc_platform_data realview_mmc0_plat_data = {
 157         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 158         .status         = realview_mmc_status,
 159 };
 160
 161 struct mmc_platform_data realview_mmc1_plat_data = {
 162         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 163         .status         = realview_mmc_status,
 164 };
 165
 166 /*
 167  * Clock handling
 168  */
 169 static const struct icst307_params realview_oscvco_params = {
 170         .ref            = 24000,
 171         .vco_max        = 200000,
 172         .vd_min         = 4 + 8,
 173         .vd_max         = 511 + 8,
 174         .rd_min         = 1 + 2,
 175         .rd_max         = 127 + 2,
 176 };
 177
 178 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 179 {
 180         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 181         void __iomem *sys_osc;
 182         u32 val;
 183
 184         if (machine_is_realview_pb1176())
 185                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 186         else
 187                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 188
 189         val = readl(sys_osc) & ~0x7ffff;
 190         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 191
 192         writel(0xa05f, sys_lock);
 193         writel(val, sys_osc);
 194         writel(0, sys_lock);
 195 }
 196
 197 struct clk realview_clcd_clk = {
 198         .name   = "CLCDCLK",
 199         .params = &realview_oscvco_params,
 200         .setvco = realview_oscvco_set,
 201 };
 202
 203 /*
 204  * CLCD support.
 205  */
 206 #define SYS_CLCD_NLCDIOON       (1 << 2)
 207 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 208 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 209 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 210 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 211 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 212 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 213 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 214 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 215
 216 static struct clcd_panel vga = {
 217         .mode           = {
 218                 .name           = "VGA",
 219                 .refresh        = 60,
 220                 .xres           = 640,
 221                 .yres           = 480,
 222                 .pixclock       = 39721,
 223                 .left_margin    = 40,
 224                 .right_margin   = 24,
 225                 .upper_margin   = 32,
 226                 .lower_margin   = 11,
 227                 .hsync_len      = 96,
 228                 .vsync_len      = 2,
 229                 .sync           = 0,
 230                 .vmode          = FB_VMODE_NONINTERLACED,
 231         },
 232         .width          = -1,
 233         .height         = -1,
 234         .tim2           = TIM2_BCD | TIM2_IPC,
 235         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 236         .bpp            = 16,
 237 };
 238
 239 static struct clcd_panel sanyo_3_8_in = {
 240         .mode           = {
 241                 .name           = "Sanyo QVGA",
 242                 .refresh        = 116,
 243                 .xres           = 320,
 244                 .yres           = 240,
 245                 .pixclock       = 100000,
 246                 .left_margin    = 6,
 247                 .right_margin   = 6,
 248                 .upper_margin   = 5,
 249                 .lower_margin   = 5,
 250                 .hsync_len      = 6,
 251                 .vsync_len      = 6,
 252                 .sync           = 0,
 253                 .vmode          = FB_VMODE_NONINTERLACED,
 254         },
 255         .width          = -1,
 256         .height         = -1,
 257         .tim2           = TIM2_BCD,
 258         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 259         .bpp            = 16,
 260 };
 261
 262 static struct clcd_panel sanyo_2_5_in = {
 263         .mode           = {
 264                 .name           = "Sanyo QVGA Portrait",
 265                 .refresh        = 116,
 266                 .xres           = 240,
 267                 .yres           = 320,
 268                 .pixclock       = 100000,
 269                 .left_margin    = 20,
 270                 .right_margin   = 10,
 271                 .upper_margin   = 2,
 272                 .lower_margin   = 2,
 273                 .hsync_len      = 10,
 274                 .vsync_len      = 2,
 275                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 276                 .vmode          = FB_VMODE_NONINTERLACED,
 277         },
 278         .width          = -1,
 279         .height         = -1,
 280         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 281         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 282         .bpp            = 16,
 283 };
 284
 285 static struct clcd_panel epson_2_2_in = {
 286         .mode           = {
 287                 .name           = "Epson QCIF",
 288                 .refresh        = 390,
 289                 .xres           = 176,
 290                 .yres           = 220,
 291                 .pixclock       = 62500,
 292                 .left_margin    = 3,
 293                 .right_margin   = 2,
 294                 .upper_margin   = 1,
 295                 .lower_margin   = 0,
 296                 .hsync_len      = 3,
 297                 .vsync_len      = 2,
 298                 .sync           = 0,
 299                 .vmode          = FB_VMODE_NONINTERLACED,
 300         },
 301         .width          = -1,
 302         .height         = -1,
 303         .tim2           = TIM2_BCD | TIM2_IPC,
 304         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 305         .bpp            = 16,
 306 };
 307
 308 /*
 309  * Detect which LCD panel is connected, and return the appropriate
 310  * clcd_panel structure.  Note: we do not have any information on
 311  * the required timings for the 8.4in panel, so we presently assume
 312  * VGA timings.
 313  */
 314 static struct clcd_panel *realview_clcd_panel(void)
 315 {
 316         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 317         struct clcd_panel *panel = &vga;
 318         u32 val;
 319
 320         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 321         if (val == SYS_CLCD_ID_SANYO_3_8)
 322                 panel = &sanyo_3_8_in;
 323         else if (val == SYS_CLCD_ID_SANYO_2_5)
 324                 panel = &sanyo_2_5_in;
 325         else if (val == SYS_CLCD_ID_EPSON_2_2)
 326                 panel = &epson_2_2_in;
 327         else if (val == SYS_CLCD_ID_VGA)
 328                 panel = &vga;
 329         else {
 330                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 331                         val);
 332                 panel = &vga;
 333         }
 334
 335         return panel;
 336 }
 337
 338 /*
 339  * Disable all display connectors on the interface module.
 340  */
 341 static void realview_clcd_disable(struct clcd_fb *fb)
 342 {
 343         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 344         u32 val;
 345
 346         val = readl(sys_clcd);
 347         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 348         writel(val, sys_clcd);
 349 }
 350
 351 /*
 352  * Enable the relevant connector on the interface module.
 353  */
 354 static void realview_clcd_enable(struct clcd_fb *fb)
 355 {
 356         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 357         u32 val;
 358
 359         /*
 360          * Enable the PSUs
 361          */
 362         val = readl(sys_clcd);
 363         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 364         writel(val, sys_clcd);
 365 }
 366
 367 static unsigned long framesize = SZ_1M;
 368
 369 static int realview_clcd_setup(struct clcd_fb *fb)
 370 {
 371         dma_addr_t dma;
 372
 373         fb->panel               = realview_clcd_panel();
 374
 375         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 376                                                     &dma, GFP_KERNEL);
 377         if (!fb->fb.screen_base) {
 378                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 379                 return -ENOMEM;
 380         }
 381
 382         fb->fb.fix.smem_start   = dma;
 383         fb->fb.fix.smem_len     = framesize;
 384
 385         return 0;
 386 }
 387
 388 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 389 {
 390         return dma_mmap_writecombine(&fb->dev->dev, vma,
 391                                      fb->fb.screen_base,
 392                                      fb->fb.fix.smem_start,
 393                                      fb->fb.fix.smem_len);
 394 }
 395
 396 static void realview_clcd_remove(struct clcd_fb *fb)
 397 {
 398         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 399                               fb->fb.screen_base, fb->fb.fix.smem_start);
 400 }
 401
 402 struct clcd_board clcd_plat_data = {
 403         .name           = "RealView",
 404         .check          = clcdfb_check,
 405         .decode         = clcdfb_decode,
 406         .disable        = realview_clcd_disable,
 407         .enable         = realview_clcd_enable,
 408         .setup          = realview_clcd_setup,
 409         .mmap           = realview_clcd_mmap,
 410         .remove         = realview_clcd_remove,
 411 };
 412
 413 #ifdef CONFIG_LEDS
 414 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 415
 416 void realview_leds_event(led_event_t ledevt)
 417 {
 418         unsigned long flags;
 419         u32 val;
 420
 421         local_irq_save(flags);
 422         val = readl(VA_LEDS_BASE);
 423
 424         switch (ledevt) {
 425         case led_idle_start:
 426                 val = val & ~REALVIEW_SYS_LED0;
 427                 break;
 428
 429         case led_idle_end:
 430                 val = val | REALVIEW_SYS_LED0;
 431                 break;
 432
 433         case led_timer:
 434                 val = val ^ REALVIEW_SYS_LED1;
 435                 break;
 436
 437         case led_halted:
 438                 val = 0;
 439                 break;
 440
 441         default:
 442                 break;
 443         }
 444
 445         writel(val, VA_LEDS_BASE);
 446         local_irq_restore(flags);
 447 }
 448 #endif  /* CONFIG_LEDS */
 449
 450 /*
 451  * Where is the timer (VA)?
 452  */
 453 void __iomem *timer0_va_base;
 454 void __iomem *timer1_va_base;
 455 void __iomem *timer2_va_base;
 456 void __iomem *timer3_va_base;
 457
 458 /*
 459  * How long is the timer interval?
 460  */
 461 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 462 #if TIMER_INTERVAL >= 0x100000
 463 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 464 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 465 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 466 #elif TIMER_INTERVAL >= 0x10000
 467 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 468 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 469 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 470 #else
 471 #define TIMER_RELOAD    (TIMER_INTERVAL)
 472 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 473 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 474 #endif
 475
 476 static void timer_set_mode(enum clock_event_mode mode,
 477                            struct clock_event_device *clk)
 478 {
 479         unsigned long ctrl;
 480
 481         switch(mode) {
 482         case CLOCK_EVT_MODE_PERIODIC:
 483                 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
 484
 485                 ctrl = TIMER_CTRL_PERIODIC;
 486                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
 487                 break;
 488         case CLOCK_EVT_MODE_ONESHOT:
 489                 /* period set, and timer enabled in 'next_event' hook */
 490                 ctrl = TIMER_CTRL_ONESHOT;
 491                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 492                 break;
 493         case CLOCK_EVT_MODE_UNUSED:
 494         case CLOCK_EVT_MODE_SHUTDOWN:
 495         default:
 496                 ctrl = 0;
 497         }
 498
 499         writel(ctrl, timer0_va_base + TIMER_CTRL);
 500 }
 501
 502 static int timer_set_next_event(unsigned long evt,
 503                                 struct clock_event_device *unused)
 504 {
 505         unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
 506
 507         writel(evt, timer0_va_base + TIMER_LOAD);
 508         writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
 509
 510         return 0;
 511 }
 512
 513 static struct clock_event_device timer0_clockevent =     {
 514         .name           = "timer0",
 515         .shift          = 32,
 516         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 517         .set_mode       = timer_set_mode,
 518         .set_next_event = timer_set_next_event,
 519         .rating         = 300,
 520         .cpumask        = CPU_MASK_ALL,
 521 };
 522
 523 static void __init realview_clockevents_init(unsigned int timer_irq)
 524 {
 525         timer0_clockevent.irq = timer_irq;
 526         timer0_clockevent.mult =
 527                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 528         timer0_clockevent.max_delta_ns =
 529                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 530         timer0_clockevent.min_delta_ns =
 531                 clockevent_delta2ns(0xf, &timer0_clockevent);
 532
 533         clockevents_register_device(&timer0_clockevent);
 534 }
 535
 536 /*
 537  * IRQ handler for the timer
 538  */
 539 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
 540 {
 541         struct clock_event_device *evt = &timer0_clockevent;
 542
 543         /* clear the interrupt */
 544         writel(1, timer0_va_base + TIMER_INTCLR);
 545
 546         evt->event_handler(evt);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 static struct irqaction realview_timer_irq = {
 552         .name           = "RealView Timer Tick",
 553         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 554         .handler        = realview_timer_interrupt,
 555 };
 556
 557 static cycle_t realview_get_cycles(void)
 558 {
 559         return ~readl(timer3_va_base + TIMER_VALUE);
 560 }
 561
 562 static struct clocksource clocksource_realview = {
 563         .name   = "timer3",
 564         .rating = 200,
 565         .read   = realview_get_cycles,
 566         .mask   = CLOCKSOURCE_MASK(32),
 567         .shift  = 20,
 568         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 569 };
 570
 571 static void __init realview_clocksource_init(void)
 572 {
 573         /* setup timer 0 as free-running clocksource */
 574         writel(0, timer3_va_base + TIMER_CTRL);
 575         writel(0xffffffff, timer3_va_base + TIMER_LOAD);
 576         writel(0xffffffff, timer3_va_base + TIMER_VALUE);
 577         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 578                 timer3_va_base + TIMER_CTRL);
 579
 580         clocksource_realview.mult =
 581                 clocksource_khz2mult(1000, clocksource_realview.shift);
 582         clocksource_register(&clocksource_realview);
 583 }
 584
 585 /*
 586  * Set up the clock source and clock events devices
 587  */
 588 void __init realview_timer_init(unsigned int timer_irq)
 589 {
 590         u32 val;
 591
 592 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 593         /*
 594          * The dummy clock device has to be registered before the main device
 595          * so that the latter will broadcast the clock events
 596          */
 597         local_timer_setup(smp_processor_id());
 598 #endif
 599
 600         /*
 601          * set clock frequency:
 602          *      REALVIEW_REFCLK is 32KHz
 603          *      REALVIEW_TIMCLK is 1MHz
 604          */
 605         val = readl(__io_address(REALVIEW_SCTL_BASE));
 606         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 607                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 608                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 609                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 610                __io_address(REALVIEW_SCTL_BASE));
 611
 612         /*
 613          * Initialise to a known state (all timers off)
 614          */
 615         writel(0, timer0_va_base + TIMER_CTRL);
 616         writel(0, timer1_va_base + TIMER_CTRL);
 617         writel(0, timer2_va_base + TIMER_CTRL);
 618         writel(0, timer3_va_base + TIMER_CTRL);
 619
 620         /*
 621          * Make irqs happen for the system timer
 622          */
 623         setup_irq(timer_irq, &realview_timer_irq);
 624
 625         realview_clocksource_init();
 626         realview_clockevents_init(timer_irq);
 627 }