2 * linux/arch/arm/mach-pxa/pxa25x.c
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * Code specific to PXA21x/25x/26x variants.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * Since this file should be linked before any other machine specific file,
15 * the __initcall() here will be executed first. This serves as default
16 * initialization stuff for PXA machines which can be overridden later if
19 #include <linux/gpio.h>
20 #include <linux/gpio-pxa.h>
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/platform_device.h>
25 #include <linux/suspend.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/irq.h>
28 #include <linux/gpio.h>
30 #include <asm/mach/map.h>
31 #include <asm/suspend.h>
32 #include <mach/hardware.h>
33 #include <mach/irqs.h>
34 #include <mach/pxa25x.h>
35 #include <mach/reset.h>
38 #include <mach/smemc.h>
45 * Various clock factors driven by the CCCR register.
48 /* Crystal Frequency to Memory Frequency Multiplier (L) */
49 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
51 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
52 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
54 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
55 /* Note: we store the value N * 2 here. */
56 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
59 #define BASE_CLK 3686400
62 * Get the clock frequency as reflected by CCCR and the turbo flag.
63 * We assume these values have been applied via a fcs.
64 * If info is not 0 we also display the current settings.
66 unsigned int pxa25x_get_clk_frequency_khz(int info)
68 unsigned long cccr, turbo;
69 unsigned int l, L, m, M, n2, N;
72 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
74 l = L_clk_mult[(cccr >> 0) & 0x1f];
75 m = M_clk_mult[(cccr >> 5) & 0x03];
76 n2 = N2_clk_mult[(cccr >> 7) & 0x07];
85 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
86 L / 1000000, (L % 1000000) / 10000, l );
88 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
89 M / 1000000, (M % 1000000) / 10000, m );
91 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
92 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
93 (turbo & 1) ? "" : "in" );
96 return (turbo & 1) ? (N/1000) : (M/1000);
99 static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
101 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
104 static const struct clkops clk_pxa25x_mem_ops = {
105 .enable = clk_dummy_enable,
106 .disable = clk_dummy_disable,
107 .getrate = clk_pxa25x_mem_getrate,
110 static const struct clkops clk_pxa25x_lcd_ops = {
111 .enable = clk_pxa2xx_cken_enable,
112 .disable = clk_pxa2xx_cken_disable,
113 .getrate = clk_pxa25x_mem_getrate,
116 static unsigned long gpio12_config_32k[] = {
120 static unsigned long gpio12_config_gpio[] = {
124 static void clk_gpio12_enable(struct clk *clk)
126 pxa2xx_mfp_config(gpio12_config_32k, 1);
129 static void clk_gpio12_disable(struct clk *clk)
131 pxa2xx_mfp_config(gpio12_config_gpio, 1);
134 static const struct clkops clk_pxa25x_gpio12_ops = {
135 .enable = clk_gpio12_enable,
136 .disable = clk_gpio12_disable,
139 static unsigned long gpio11_config_3m6[] = {
143 static unsigned long gpio11_config_gpio[] = {
147 static void clk_gpio11_enable(struct clk *clk)
149 pxa2xx_mfp_config(gpio11_config_3m6, 1);
152 static void clk_gpio11_disable(struct clk *clk)
154 pxa2xx_mfp_config(gpio11_config_gpio, 1);
157 static const struct clkops clk_pxa25x_gpio11_ops = {
158 .enable = clk_gpio11_enable,
159 .disable = clk_gpio11_disable,
163 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
164 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
165 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
169 * PXA 2xx clock declarations.
171 static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
172 static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
173 static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
174 static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
175 static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
176 static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
177 static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
178 static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
179 static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
180 static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
181 static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
182 static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
183 static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
184 static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
185 static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
187 static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
188 static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
189 static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
190 static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
192 static struct clk_lookup pxa25x_clkregs[] = {
193 INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
194 INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
195 INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
196 INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
197 INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
198 INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
199 INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
200 INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
201 INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
202 INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
203 INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
204 INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
205 INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
206 INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
207 INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
208 INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
209 INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
210 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
211 INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
212 INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
213 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
216 static struct clk_lookup pxa25x_hwuart_clkreg =
217 INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
221 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
222 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
225 * List of global PXA peripheral registers to preserve.
226 * More ones like CP and general purpose register values are preserved
227 * with the stack pointer in sleep.S.
235 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
240 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
245 static void pxa25x_cpu_pm_enter(suspend_state_t state)
247 /* Clear reset status */
248 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
252 cpu_suspend(PWRMODE_SLEEP, pxa25x_finish_suspend);
257 static int pxa25x_cpu_pm_prepare(void)
259 /* set resume return address */
260 PSPR = virt_to_phys(cpu_resume);
264 static void pxa25x_cpu_pm_finish(void)
266 /* ensure not to come back here if it wasn't intended */
270 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
271 .save_count = SLEEP_SAVE_COUNT,
272 .valid = suspend_valid_only_mem,
273 .save = pxa25x_cpu_pm_save,
274 .restore = pxa25x_cpu_pm_restore,
275 .enter = pxa25x_cpu_pm_enter,
276 .prepare = pxa25x_cpu_pm_prepare,
277 .finish = pxa25x_cpu_pm_finish,
280 static void __init pxa25x_init_pm(void)
282 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
285 static inline void pxa25x_init_pm(void) {}
288 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
291 static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
293 int gpio = pxa_irq_to_gpio(d->irq);
296 if (gpio >= 0 && gpio < 85)
297 return gpio_set_wake(gpio, on);
299 if (d->irq == IRQ_RTCAlrm) {
315 void __init pxa25x_init_irq(void)
317 pxa_init_irq(32, pxa25x_set_wake);
320 #ifdef CONFIG_CPU_PXA26x
321 void __init pxa26x_init_irq(void)
323 pxa_init_irq(32, pxa25x_set_wake);
327 static struct map_desc pxa25x_io_desc[] __initdata = {
329 .virtual = (unsigned long)SMEMC_VIRT,
330 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
331 .length = 0x00200000,
336 void __init pxa25x_map_io(void)
339 iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
340 pxa25x_get_clk_frequency_khz(1);
343 static struct platform_device *pxa25x_devices[] __initdata = {
353 &pxa_device_asoc_platform,
356 static int __init pxa25x_init(void)
360 if (cpu_is_pxa25x()) {
364 clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
366 if ((ret = pxa_init_dma(IRQ_DMA, 16)))
371 register_syscore_ops(&pxa_irq_syscore_ops);
372 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
373 register_syscore_ops(&pxa_gpio_syscore_ops);
374 register_syscore_ops(&pxa2xx_clock_syscore_ops);
376 ret = platform_add_devices(pxa25x_devices,
377 ARRAY_SIZE(pxa25x_devices));
382 /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
384 clkdev_add(&pxa25x_hwuart_clkreg);
389 postcore_initcall(pxa25x_init);