2 * System timer for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/kernel.h>
10 #include <linux/interrupt.h>
11 #include <linux/clockchips.h>
12 #include <linux/clocksource.h>
13 #include <linux/bitops.h>
14 #include <linux/irq.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/slab.h>
19 #include <linux/of_address.h>
21 #include <asm/sched_clock.h>
22 #include <asm/mach/time.h>
26 #define SIRFSOC_TIMER_COUNTER_LO 0x0000
27 #define SIRFSOC_TIMER_COUNTER_HI 0x0004
28 #define SIRFSOC_TIMER_MATCH_0 0x0008
29 #define SIRFSOC_TIMER_MATCH_1 0x000C
30 #define SIRFSOC_TIMER_MATCH_2 0x0010
31 #define SIRFSOC_TIMER_MATCH_3 0x0014
32 #define SIRFSOC_TIMER_MATCH_4 0x0018
33 #define SIRFSOC_TIMER_MATCH_5 0x001C
34 #define SIRFSOC_TIMER_STATUS 0x0020
35 #define SIRFSOC_TIMER_INT_EN 0x0024
36 #define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
37 #define SIRFSOC_TIMER_DIV 0x002C
38 #define SIRFSOC_TIMER_LATCH 0x0030
39 #define SIRFSOC_TIMER_LATCHED_LO 0x0034
40 #define SIRFSOC_TIMER_LATCHED_HI 0x0038
42 #define SIRFSOC_TIMER_WDT_INDEX 5
44 #define SIRFSOC_TIMER_LATCH_BIT BIT(0)
46 #define SIRFSOC_TIMER_REG_CNT 11
48 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
49 SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
50 SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
51 SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
52 SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
55 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
57 static void __iomem *sirfsoc_timer_base;
58 static void __init sirfsoc_of_timer_map(void);
60 /* timer0 interrupt handler */
61 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
63 struct clock_event_device *ce = dev_id;
65 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));
67 /* clear timer0 interrupt */
68 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
70 ce->event_handler(ce);
75 /* read 64-bit timer counter */
76 static cycle_t sirfsoc_timer_read(struct clocksource *cs)
80 /* latch the 64-bit timer counter */
81 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
82 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
83 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
88 static int sirfsoc_timer_set_next_event(unsigned long delta,
89 struct clock_event_device *ce)
91 unsigned long now, next;
93 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
94 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
96 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
97 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
98 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
100 return next - now > delta ? -ETIME : 0;
103 static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
104 struct clock_event_device *ce)
106 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
108 case CLOCK_EVT_MODE_PERIODIC:
111 case CLOCK_EVT_MODE_ONESHOT:
112 writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
114 case CLOCK_EVT_MODE_SHUTDOWN:
115 writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
117 case CLOCK_EVT_MODE_UNUSED:
118 case CLOCK_EVT_MODE_RESUME:
123 static void sirfsoc_clocksource_suspend(struct clocksource *cs)
127 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
129 for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
130 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
133 static void sirfsoc_clocksource_resume(struct clocksource *cs)
137 for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
138 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
140 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
141 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
144 static struct clock_event_device sirfsoc_clockevent = {
145 .name = "sirfsoc_clockevent",
147 .features = CLOCK_EVT_FEAT_ONESHOT,
148 .set_mode = sirfsoc_timer_set_mode,
149 .set_next_event = sirfsoc_timer_set_next_event,
152 static struct clocksource sirfsoc_clocksource = {
153 .name = "sirfsoc_clocksource",
155 .mask = CLOCKSOURCE_MASK(64),
156 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
157 .read = sirfsoc_timer_read,
158 .suspend = sirfsoc_clocksource_suspend,
159 .resume = sirfsoc_clocksource_resume,
162 static struct irqaction sirfsoc_timer_irq = {
163 .name = "sirfsoc_timer0",
166 .handler = sirfsoc_timer_interrupt,
167 .dev_id = &sirfsoc_clockevent,
170 /* Overwrite weak default sched_clock with more precise one */
171 static u32 notrace sirfsoc_read_sched_clock(void)
173 return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff);
176 static void __init sirfsoc_clockevent_init(void)
178 sirfsoc_clockevent.cpumask = cpumask_of(0);
179 clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE,
183 /* initialize the kernel jiffy timer source */
184 void __init sirfsoc_prima2_timer_init(void)
189 /* initialize clocking early, we want to set the OS timer */
190 sirfsoc_of_clk_init();
192 /* timer's input clock is io clock */
193 clk = clk_get_sys("io", NULL);
197 rate = clk_get_rate(clk);
199 BUG_ON(rate < CLOCK_TICK_RATE);
200 BUG_ON(rate % CLOCK_TICK_RATE);
202 sirfsoc_of_timer_map();
204 writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
205 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
206 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
207 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
209 BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
211 setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE);
213 BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
215 sirfsoc_clockevent_init();
218 static struct of_device_id timer_ids[] = {
219 { .compatible = "sirf,prima2-tick" },
223 static void __init sirfsoc_of_timer_map(void)
225 struct device_node *np;
226 const unsigned int *intspec;
228 np = of_find_matching_node(NULL, timer_ids);
231 sirfsoc_timer_base = of_iomap(np, 0);
232 if (!sirfsoc_timer_base)
233 panic("unable to map timer cpu registers\n");
235 /* Get the interrupts property */
236 intspec = of_get_property(np, "interrupts", NULL);
238 sirfsoc_timer_irq.irq = be32_to_cpup(intspec);