2 * System timer for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/kernel.h>
10 #include <linux/interrupt.h>
11 #include <linux/clockchips.h>
12 #include <linux/clocksource.h>
13 #include <linux/bitops.h>
14 #include <linux/irq.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/slab.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
22 #include <asm/sched_clock.h>
23 #include <asm/mach/time.h>
27 #define SIRFSOC_TIMER_COUNTER_LO 0x0000
28 #define SIRFSOC_TIMER_COUNTER_HI 0x0004
29 #define SIRFSOC_TIMER_MATCH_0 0x0008
30 #define SIRFSOC_TIMER_MATCH_1 0x000C
31 #define SIRFSOC_TIMER_MATCH_2 0x0010
32 #define SIRFSOC_TIMER_MATCH_3 0x0014
33 #define SIRFSOC_TIMER_MATCH_4 0x0018
34 #define SIRFSOC_TIMER_MATCH_5 0x001C
35 #define SIRFSOC_TIMER_STATUS 0x0020
36 #define SIRFSOC_TIMER_INT_EN 0x0024
37 #define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
38 #define SIRFSOC_TIMER_DIV 0x002C
39 #define SIRFSOC_TIMER_LATCH 0x0030
40 #define SIRFSOC_TIMER_LATCHED_LO 0x0034
41 #define SIRFSOC_TIMER_LATCHED_HI 0x0038
43 #define SIRFSOC_TIMER_WDT_INDEX 5
45 #define SIRFSOC_TIMER_LATCH_BIT BIT(0)
47 #define SIRFSOC_TIMER_REG_CNT 11
49 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
50 SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
51 SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
52 SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
53 SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
56 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
58 static void __iomem *sirfsoc_timer_base;
59 static void __init sirfsoc_of_timer_map(void);
61 /* timer0 interrupt handler */
62 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
64 struct clock_event_device *ce = dev_id;
66 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));
68 /* clear timer0 interrupt */
69 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
71 ce->event_handler(ce);
76 /* read 64-bit timer counter */
77 static cycle_t sirfsoc_timer_read(struct clocksource *cs)
81 /* latch the 64-bit timer counter */
82 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
83 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
84 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
89 static int sirfsoc_timer_set_next_event(unsigned long delta,
90 struct clock_event_device *ce)
92 unsigned long now, next;
94 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
95 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
97 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
98 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
99 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
101 return next - now > delta ? -ETIME : 0;
104 static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
105 struct clock_event_device *ce)
107 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
109 case CLOCK_EVT_MODE_PERIODIC:
112 case CLOCK_EVT_MODE_ONESHOT:
113 writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
115 case CLOCK_EVT_MODE_SHUTDOWN:
116 writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
118 case CLOCK_EVT_MODE_UNUSED:
119 case CLOCK_EVT_MODE_RESUME:
124 static void sirfsoc_clocksource_suspend(struct clocksource *cs)
128 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
130 for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
131 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
134 static void sirfsoc_clocksource_resume(struct clocksource *cs)
138 for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
139 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
141 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
142 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
145 static struct clock_event_device sirfsoc_clockevent = {
146 .name = "sirfsoc_clockevent",
148 .features = CLOCK_EVT_FEAT_ONESHOT,
149 .set_mode = sirfsoc_timer_set_mode,
150 .set_next_event = sirfsoc_timer_set_next_event,
153 static struct clocksource sirfsoc_clocksource = {
154 .name = "sirfsoc_clocksource",
156 .mask = CLOCKSOURCE_MASK(64),
157 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
158 .read = sirfsoc_timer_read,
159 .suspend = sirfsoc_clocksource_suspend,
160 .resume = sirfsoc_clocksource_resume,
163 static struct irqaction sirfsoc_timer_irq = {
164 .name = "sirfsoc_timer0",
167 .handler = sirfsoc_timer_interrupt,
168 .dev_id = &sirfsoc_clockevent,
171 /* Overwrite weak default sched_clock with more precise one */
172 static u32 notrace sirfsoc_read_sched_clock(void)
174 return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff);
177 static void __init sirfsoc_clockevent_init(void)
179 sirfsoc_clockevent.cpumask = cpumask_of(0);
180 clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE,
184 /* initialize the kernel jiffy timer source */
185 void __init sirfsoc_prima2_timer_init(void)
190 /* initialize clocking early, we want to set the OS timer */
191 sirfsoc_of_clk_init();
193 /* timer's input clock is io clock */
194 clk = clk_get_sys("io", NULL);
198 rate = clk_get_rate(clk);
200 BUG_ON(rate < CLOCK_TICK_RATE);
201 BUG_ON(rate % CLOCK_TICK_RATE);
203 sirfsoc_of_timer_map();
205 writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
206 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
207 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
208 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
210 BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
212 setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE);
214 BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
216 sirfsoc_clockevent_init();
219 static struct of_device_id timer_ids[] = {
220 { .compatible = "sirf,prima2-tick" },
224 static void __init sirfsoc_of_timer_map(void)
226 struct device_node *np;
228 np = of_find_matching_node(NULL, timer_ids);
231 sirfsoc_timer_base = of_iomap(np, 0);
232 if (!sirfsoc_timer_base)
233 panic("unable to map timer cpu registers\n");
235 /* Get the interrupts property */
236 sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);