2 * power management entry for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/kernel.h>
10 #include <linux/suspend.h>
11 #include <linux/slab.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_platform.h>
17 #include <linux/rtc/sirfsoc_rtciobrg.h>
18 #include <asm/suspend.h>
19 #include <asm/hardware/cache-l2x0.h>
24 * suspend asm codes will access these to make DRAM become self-refresh and
27 u32 sirfsoc_pwrc_base;
28 void __iomem *sirfsoc_memc_base;
30 static void sirfsoc_set_wakeup_source(void)
32 u32 pwr_trigger_en_reg;
33 pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
34 SIRFSOC_PWRC_TRIGGER_EN);
35 #define X_ON_KEY_B (1 << 0)
36 sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B,
37 sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
40 static void sirfsoc_set_sleep_mode(u32 mode)
42 u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
43 SIRFSOC_PWRC_PDN_CTRL);
44 sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1);
45 sleep_mode |= mode << 1;
46 sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base +
47 SIRFSOC_PWRC_PDN_CTRL);
50 static int sirfsoc_pre_suspend_power_off(void)
52 u32 wakeup_entry = virt_to_phys(cpu_resume);
54 sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
55 SIRFSOC_PWRC_SCRATCH_PAD1);
57 sirfsoc_set_wakeup_source();
59 sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE);
64 static int sirfsoc_pm_enter(suspend_state_t state)
68 sirfsoc_pre_suspend_power_off();
73 cpu_suspend(0, sirfsoc_finish_suspend);
82 static const struct platform_suspend_ops sirfsoc_pm_ops = {
83 .enter = sirfsoc_pm_enter,
84 .valid = suspend_valid_only_mem,
87 static int __init sirfsoc_pm_init(void)
89 suspend_set_ops(&sirfsoc_pm_ops);
92 late_initcall(sirfsoc_pm_init);
94 static const struct of_device_id pwrc_ids[] = {
95 { .compatible = "sirf,prima2-pwrc" },
99 static int __init sirfsoc_of_pwrc_init(void)
101 struct device_node *np;
103 np = of_find_matching_node(NULL, pwrc_ids);
105 panic("unable to find compatible pwrc node in dtb\n");
108 * pwrc behind rtciobrg is not located in memory space
109 * though the property is named reg. reg only means base
110 * offset for pwrc. then of_iomap is not suitable here.
112 if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base))
113 panic("unable to find base address of pwrc node in dtb\n");
119 postcore_initcall(sirfsoc_of_pwrc_init);
121 static const struct of_device_id memc_ids[] = {
122 { .compatible = "sirf,prima2-memc" },
126 static int __devinit sirfsoc_memc_probe(struct platform_device *op)
128 struct device_node *np = op->dev.of_node;
130 sirfsoc_memc_base = of_iomap(np, 0);
131 if (!sirfsoc_memc_base)
132 panic("unable to map memc registers\n");
137 static struct platform_driver sirfsoc_memc_driver = {
138 .probe = sirfsoc_memc_probe,
140 .name = "sirfsoc-memc",
141 .owner = THIS_MODULE,
142 .of_match_table = memc_ids,
146 static int __init sirfsoc_memc_init(void)
148 return platform_driver_register(&sirfsoc_memc_driver);
150 postcore_initcall(sirfsoc_memc_init);