2 * plat smp support for CSR Marco dual-core SMP SoCs
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/init.h>
10 #include <linux/smp.h>
11 #include <linux/delay.h>
13 #include <linux/of_address.h>
14 #include <linux/irqchip/arm-gic.h>
16 #include <asm/mach/map.h>
17 #include <asm/smp_plat.h>
18 #include <asm/smp_scu.h>
19 #include <asm/cacheflush.h>
20 #include <asm/cputype.h>
25 static void __iomem *scu_base;
26 static void __iomem *rsc_base;
28 static DEFINE_SPINLOCK(boot_lock);
30 static struct map_desc scu_io_desc __initdata = {
35 void __init sirfsoc_map_scu(void)
40 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
42 scu_io_desc.virtual = SIRFSOC_VA(base);
43 scu_io_desc.pfn = __phys_to_pfn(base);
44 iotable_init(&scu_io_desc, 1);
46 scu_base = (void __iomem *)SIRFSOC_VA(base);
49 static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
52 * if any interrupts are already enabled for the primary
53 * core (e.g. timer irq), then they will not have been enabled
56 gic_secondary_init(0);
59 * let the primary processor know we're out of the
60 * pen, then head off into the C entry point
66 * Synchronise with the boot thread.
68 spin_lock(&boot_lock);
69 spin_unlock(&boot_lock);
72 static struct of_device_id rsc_ids[] = {
73 { .compatible = "sirf,marco-rsc" },
77 static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
79 unsigned long timeout;
80 struct device_node *np;
82 np = of_find_matching_node(NULL, rsc_ids);
86 rsc_base = of_iomap(np, 0);
91 * write the address of secondary startup into the sram register
92 * at offset 0x2C, then write the magic number 0x3CAF5D62 to the
93 * RSC register at offset 0x28, which is what boot rom code is
94 * waiting for. This would wake up the secondary core from WFE
96 #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
97 __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
98 rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
100 #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
101 __raw_writel(0x3CAF5D62,
102 rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
104 /* make sure write buffer is drained */
107 spin_lock(&boot_lock);
110 * The secondary processor is waiting to be released from
111 * the holding pen - release it, then wait for it to flag
112 * that it has been released by resetting pen_release.
114 * Note that "pen_release" is the hardware CPU ID, whereas
115 * "cpu" is Linux's internal ID.
117 pen_release = cpu_logical_map(cpu);
118 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
119 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
122 * Send the secondary CPU SEV, thereby causing the boot monitor to read
123 * the JUMPADDR and WAKEMAGIC, and branch to the address found there.
127 timeout = jiffies + (1 * HZ);
128 while (time_before(jiffies, timeout)) {
130 if (pen_release == -1)
137 * now the secondary core is starting up let it run its
138 * calibrations, then wait for it to finish
140 spin_unlock(&boot_lock);
142 return pen_release != -1 ? -ENOSYS : 0;
145 static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
147 scu_enable(scu_base);
150 struct smp_operations sirfsoc_smp_ops __initdata = {
151 .smp_prepare_cpus = sirfsoc_smp_prepare_cpus,
152 .smp_secondary_init = sirfsoc_secondary_init,
153 .smp_boot_secondary = sirfsoc_boot_secondary,
154 #ifdef CONFIG_HOTPLUG_CPU
155 .cpu_die = sirfsoc_cpu_die,