2 * interrupt controller support for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/init.h>
11 #include <linux/irq.h>
13 #include <linux/of_address.h>
14 #include <linux/irqdomain.h>
15 #include <linux/syscore_ops.h>
16 #include <asm/mach/irq.h>
17 #include <asm/exception.h>
18 #include <mach/hardware.h>
20 #define SIRFSOC_INT_RISC_MASK0 0x0018
21 #define SIRFSOC_INT_RISC_MASK1 0x001C
22 #define SIRFSOC_INT_RISC_LEVEL0 0x0020
23 #define SIRFSOC_INT_RISC_LEVEL1 0x0024
24 #define SIRFSOC_INIT_IRQ_ID 0x0038
26 void __iomem *sirfsoc_intc_base;
29 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
31 struct irq_chip_generic *gc;
32 struct irq_chip_type *ct;
34 gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
37 ct->chip.irq_mask = irq_gc_mask_clr_bit;
38 ct->chip.irq_unmask = irq_gc_mask_set_bit;
39 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
41 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
44 static __init void sirfsoc_irq_init(void)
46 sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
47 sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
48 SIRFSOC_INTENAL_IRQ_END + 1 - 32);
50 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
51 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
53 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
54 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
57 asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
61 irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
62 irqnr = irqstat & 0xff;
64 handle_IRQ(irqnr, regs);
67 static struct of_device_id intc_ids[] = {
68 { .compatible = "sirf,prima2-intc" },
72 void __init sirfsoc_of_irq_init(void)
74 struct device_node *np;
76 np = of_find_matching_node(NULL, intc_ids);
80 sirfsoc_intc_base = of_iomap(np, 0);
81 if (!sirfsoc_intc_base)
82 panic("unable to map intc cpu registers\n");
84 irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
85 &irq_domain_simple_ops, NULL);
92 struct sirfsoc_irq_status {
99 static struct sirfsoc_irq_status sirfsoc_irq_st;
101 static int sirfsoc_irq_suspend(void)
103 sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
104 sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
105 sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
106 sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
111 static void sirfsoc_irq_resume(void)
113 writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
114 writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
115 writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
116 writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
119 static struct syscore_ops sirfsoc_irq_syscore_ops = {
120 .suspend = sirfsoc_irq_suspend,
121 .resume = sirfsoc_irq_resume,
124 static int __init sirfsoc_irq_pm_init(void)
126 register_syscore_ops(&sirfsoc_irq_syscore_ops);
129 device_initcall(sirfsoc_irq_pm_init);