Pileus Git - ~andy/linux/blob - arch/arm/mach-prima2/irq.c

   1 /*
   2  * interrupt controller support for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/io.h>
  11 #include <linux/irq.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/syscore_ops.h>
  16 #include <asm/mach/irq.h>
  17 #include <asm/exception.h>
  18 #include <mach/hardware.h>
  19
  20 #define SIRFSOC_INT_RISC_MASK0          0x0018
  21 #define SIRFSOC_INT_RISC_MASK1          0x001C
  22 #define SIRFSOC_INT_RISC_LEVEL0         0x0020
  23 #define SIRFSOC_INT_RISC_LEVEL1         0x0024
  24 #define SIRFSOC_INIT_IRQ_ID             0x0038
  25
  26 void __iomem *sirfsoc_intc_base;
  27
  28 static __init void
  29 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
  30 {
  31         struct irq_chip_generic *gc;
  32         struct irq_chip_type *ct;
  33
  34         gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
  35         ct = gc->chip_types;
  36
  37         ct->chip.irq_mask = irq_gc_mask_clr_bit;
  38         ct->chip.irq_unmask = irq_gc_mask_set_bit;
  39         ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
  40
  41         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
  42 }
  43
  44 static __init void sirfsoc_irq_init(void)
  45 {
  46         sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
  47         sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
  48                         SIRFSOC_INTENAL_IRQ_END + 1 - 32);
  49
  50         writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
  51         writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
  52
  53         writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
  54         writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
  55 }
  56
  57 asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
  58 {
  59         u32 irqstat, irqnr;
  60
  61         irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
  62         irqnr = irqstat & 0xff;
  63
  64         handle_IRQ(irqnr, regs);
  65 }
  66
  67 static struct of_device_id intc_ids[]  = {
  68         { .compatible = "sirf,prima2-intc" },
  69         {},
  70 };
  71
  72 void __init sirfsoc_of_irq_init(void)
  73 {
  74         struct device_node *np;
  75
  76         np = of_find_matching_node(NULL, intc_ids);
  77         if (!np)
  78                 return;
  79
  80         sirfsoc_intc_base = of_iomap(np, 0);
  81         if (!sirfsoc_intc_base)
  82                 panic("unable to map intc cpu registers\n");
  83
  84         irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
  85                 &irq_domain_simple_ops, NULL);
  86
  87         of_node_put(np);
  88
  89         sirfsoc_irq_init();
  90 }
  91
  92 struct sirfsoc_irq_status {
  93         u32 mask0;
  94         u32 mask1;
  95         u32 level0;
  96         u32 level1;
  97 };
  98
  99 static struct sirfsoc_irq_status sirfsoc_irq_st;
 100
 101 static int sirfsoc_irq_suspend(void)
 102 {
 103         sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
 104         sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
 105         sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
 106         sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
 107
 108         return 0;
 109 }
 110
 111 static void sirfsoc_irq_resume(void)
 112 {
 113         writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
 114         writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
 115         writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
 116         writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
 117 }
 118
 119 static struct syscore_ops sirfsoc_irq_syscore_ops = {
 120         .suspend        = sirfsoc_irq_suspend,
 121         .resume         = sirfsoc_irq_resume,
 122 };
 123
 124 static int __init sirfsoc_irq_pm_init(void)
 125 {
 126         register_syscore_ops(&sirfsoc_irq_syscore_ops);
 127         return 0;
 128 }
 129 device_initcall(sirfsoc_irq_pm_init);