Pileus Git - ~andy/linux/blob - arch/arm/mach-orion5x/ts78xx-setup.c

   1 /*
   2  * arch/arm/mach-orion5x/ts78xx-setup.c
   3  *
   4  * Maintainer: Alexander Clouter <alex@digriz.org.uk>
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/sysfs.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/mv643xx_eth.h>
  18 #include <linux/ata_platform.h>
  19 #include <linux/m48t86.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/timeriomem-rng.h>
  23 #include <asm/mach-types.h>
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/map.h>
  26 #include <mach/orion5x.h>
  27 #include "common.h"
  28 #include "mpp.h"
  29 #include "ts78xx-fpga.h"
  30
  31 /*****************************************************************************
  32  * TS-78xx Info
  33  ****************************************************************************/
  34
  35 /*
  36  * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
  37  */
  38 #define TS78XX_FPGA_REGS_PHYS_BASE      0xe8000000
  39 #define TS78XX_FPGA_REGS_VIRT_BASE      0xff900000
  40 #define TS78XX_FPGA_REGS_SIZE           SZ_1M
  41
  42 static struct ts78xx_fpga_data ts78xx_fpga = {
  43         .id             = 0,
  44         .state          = 1,
  45 /*      .supports       = ... - populated by ts78xx_fpga_supports() */
  46 };
  47
  48 /*****************************************************************************
  49  * I/O Address Mapping
  50  ****************************************************************************/
  51 static struct map_desc ts78xx_io_desc[] __initdata = {
  52         {
  53                 .virtual        = TS78XX_FPGA_REGS_VIRT_BASE,
  54                 .pfn            = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
  55                 .length         = TS78XX_FPGA_REGS_SIZE,
  56                 .type           = MT_DEVICE,
  57         },
  58 };
  59
  60 void __init ts78xx_map_io(void)
  61 {
  62         orion5x_map_io();
  63         iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
  64 }
  65
  66 /*****************************************************************************
  67  * Ethernet
  68  ****************************************************************************/
  69 static struct mv643xx_eth_platform_data ts78xx_eth_data = {
  70         .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
  71 };
  72
  73 /*****************************************************************************
  74  * SATA
  75  ****************************************************************************/
  76 static struct mv_sata_platform_data ts78xx_sata_data = {
  77         .n_ports        = 2,
  78 };
  79
  80 /*****************************************************************************
  81  * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
  82  ****************************************************************************/
  83 #define TS_RTC_CTRL     (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
  84 #define TS_RTC_DATA     (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
  85
  86 static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr)
  87 {
  88         writeb(addr, TS_RTC_CTRL);
  89         return readb(TS_RTC_DATA);
  90 }
  91
  92 static void ts78xx_ts_rtc_writebyte(unsigned char value, unsigned long addr)
  93 {
  94         writeb(addr, TS_RTC_CTRL);
  95         writeb(value, TS_RTC_DATA);
  96 }
  97
  98 static struct m48t86_ops ts78xx_ts_rtc_ops = {
  99         .readbyte       = ts78xx_ts_rtc_readbyte,
 100         .writebyte      = ts78xx_ts_rtc_writebyte,
 101 };
 102
 103 static struct platform_device ts78xx_ts_rtc_device = {
 104         .name           = "rtc-m48t86",
 105         .id             = -1,
 106         .dev            = {
 107                 .platform_data  = &ts78xx_ts_rtc_ops,
 108         },
 109         .num_resources  = 0,
 110 };
 111
 112 /*
 113  * TS uses some of the user storage space on the RTC chip so see if it is
 114  * present; as it's an optional feature at purchase time and not all boards
 115  * will have it present
 116  *
 117  * I've used the method TS use in their rtc7800.c example for the detection
 118  *
 119  * TODO: track down a guinea pig without an RTC to see if we can work out a
 120  *              better RTC detection routine
 121  */
 122 static int ts78xx_ts_rtc_load(void)
 123 {
 124         int rc;
 125         unsigned char tmp_rtc0, tmp_rtc1;
 126
 127         tmp_rtc0 = ts78xx_ts_rtc_readbyte(126);
 128         tmp_rtc1 = ts78xx_ts_rtc_readbyte(127);
 129
 130         ts78xx_ts_rtc_writebyte(0x00, 126);
 131         ts78xx_ts_rtc_writebyte(0x55, 127);
 132         if (ts78xx_ts_rtc_readbyte(127) == 0x55) {
 133                 ts78xx_ts_rtc_writebyte(0xaa, 127);
 134                 if (ts78xx_ts_rtc_readbyte(127) == 0xaa
 135                                 && ts78xx_ts_rtc_readbyte(126) == 0x00) {
 136                         ts78xx_ts_rtc_writebyte(tmp_rtc0, 126);
 137                         ts78xx_ts_rtc_writebyte(tmp_rtc1, 127);
 138
 139                         if (ts78xx_fpga.supports.ts_rtc.init == 0) {
 140                                 rc = platform_device_register(&ts78xx_ts_rtc_device);
 141                                 if (!rc)
 142                                         ts78xx_fpga.supports.ts_rtc.init = 1;
 143                         } else
 144                                 rc = platform_device_add(&ts78xx_ts_rtc_device);
 145
 146                         if (rc)
 147                                 pr_info("RTC could not be registered: %d\n",
 148                                         rc);
 149                         return rc;
 150                 }
 151         }
 152
 153         pr_info("RTC not found\n");
 154         return -ENODEV;
 155 };
 156
 157 static void ts78xx_ts_rtc_unload(void)
 158 {
 159         platform_device_del(&ts78xx_ts_rtc_device);
 160 }
 161
 162 /*****************************************************************************
 163  * NAND Flash
 164  ****************************************************************************/
 165 #define TS_NAND_CTRL    (TS78XX_FPGA_REGS_VIRT_BASE | 0x800)    /* VIRT */
 166 #define TS_NAND_DATA    (TS78XX_FPGA_REGS_PHYS_BASE | 0x804)    /* PHYS */
 167
 168 /*
 169  * hardware specific access to control-lines
 170  *
 171  * ctrl:
 172  * NAND_NCE: bit 0 -> bit 2
 173  * NAND_CLE: bit 1 -> bit 1
 174  * NAND_ALE: bit 2 -> bit 0
 175  */
 176 static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 177                         unsigned int ctrl)
 178 {
 179         struct nand_chip *this = mtd->priv;
 180
 181         if (ctrl & NAND_CTRL_CHANGE) {
 182                 unsigned char bits;
 183
 184                 bits = (ctrl & NAND_NCE) << 2;
 185                 bits |= ctrl & NAND_CLE;
 186                 bits |= (ctrl & NAND_ALE) >> 2;
 187
 188                 writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
 189         }
 190
 191         if (cmd != NAND_CMD_NONE)
 192                 writeb(cmd, this->IO_ADDR_W);
 193 }
 194
 195 static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
 196 {
 197         return readb(TS_NAND_CTRL) & 0x20;
 198 }
 199
 200 static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
 201                         const uint8_t *buf, int len)
 202 {
 203         struct nand_chip *chip = mtd->priv;
 204         void __iomem *io_base = chip->IO_ADDR_W;
 205         unsigned long off = ((unsigned long)buf & 3);
 206         int sz;
 207
 208         if (off) {
 209                 sz = min_t(int, 4 - off, len);
 210                 writesb(io_base, buf, sz);
 211                 buf += sz;
 212                 len -= sz;
 213         }
 214
 215         sz = len >> 2;
 216         if (sz) {
 217                 u32 *buf32 = (u32 *)buf;
 218                 writesl(io_base, buf32, sz);
 219                 buf += sz << 2;
 220                 len -= sz << 2;
 221         }
 222
 223         if (len)
 224                 writesb(io_base, buf, len);
 225 }
 226
 227 static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
 228                         uint8_t *buf, int len)
 229 {
 230         struct nand_chip *chip = mtd->priv;
 231         void __iomem *io_base = chip->IO_ADDR_R;
 232         unsigned long off = ((unsigned long)buf & 3);
 233         int sz;
 234
 235         if (off) {
 236                 sz = min_t(int, 4 - off, len);
 237                 readsb(io_base, buf, sz);
 238                 buf += sz;
 239                 len -= sz;
 240         }
 241
 242         sz = len >> 2;
 243         if (sz) {
 244                 u32 *buf32 = (u32 *)buf;
 245                 readsl(io_base, buf32, sz);
 246                 buf += sz << 2;
 247                 len -= sz << 2;
 248         }
 249
 250         if (len)
 251                 readsb(io_base, buf, len);
 252 }
 253
 254 const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
 255
 256 static struct mtd_partition ts78xx_ts_nand_parts[] = {
 257         {
 258                 .name           = "mbr",
 259                 .offset         = 0,
 260                 .size           = SZ_128K,
 261                 .mask_flags     = MTD_WRITEABLE,
 262         }, {
 263                 .name           = "kernel",
 264                 .offset         = MTDPART_OFS_APPEND,
 265                 .size           = SZ_4M,
 266         }, {
 267                 .name           = "initrd",
 268                 .offset         = MTDPART_OFS_APPEND,
 269                 .size           = SZ_4M,
 270         }, {
 271                 .name           = "rootfs",
 272                 .offset         = MTDPART_OFS_APPEND,
 273                 .size           = MTDPART_SIZ_FULL,
 274         }
 275 };
 276
 277 static struct platform_nand_data ts78xx_ts_nand_data = {
 278         .chip   = {
 279                 .nr_chips               = 1,
 280                 .part_probe_types       = ts_nand_part_probes,
 281                 .partitions             = ts78xx_ts_nand_parts,
 282                 .nr_partitions          = ARRAY_SIZE(ts78xx_ts_nand_parts),
 283                 .chip_delay             = 15,
 284                 .bbt_options            = NAND_BBT_USE_FLASH,
 285         },
 286         .ctrl   = {
 287                 /*
 288                  * The HW ECC offloading functions, used to give about a 9%
 289                  * performance increase for 'dd if=/dev/mtdblockX' and 5% for
 290                  * nanddump.  This all however was changed by git commit
 291                  * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
 292                  * no performance advantage to be had so we no longer bother
 293                  */
 294                 .cmd_ctrl               = ts78xx_ts_nand_cmd_ctrl,
 295                 .dev_ready              = ts78xx_ts_nand_dev_ready,
 296                 .write_buf              = ts78xx_ts_nand_write_buf,
 297                 .read_buf               = ts78xx_ts_nand_read_buf,
 298         },
 299 };
 300
 301 static struct resource ts78xx_ts_nand_resources
 302                         = DEFINE_RES_MEM(TS_NAND_DATA, 4);
 303
 304 static struct platform_device ts78xx_ts_nand_device = {
 305         .name           = "gen_nand",
 306         .id             = -1,
 307         .dev            = {
 308                 .platform_data  = &ts78xx_ts_nand_data,
 309         },
 310         .resource       = &ts78xx_ts_nand_resources,
 311         .num_resources  = 1,
 312 };
 313
 314 static int ts78xx_ts_nand_load(void)
 315 {
 316         int rc;
 317
 318         if (ts78xx_fpga.supports.ts_nand.init == 0) {
 319                 rc = platform_device_register(&ts78xx_ts_nand_device);
 320                 if (!rc)
 321                         ts78xx_fpga.supports.ts_nand.init = 1;
 322         } else
 323                 rc = platform_device_add(&ts78xx_ts_nand_device);
 324
 325         if (rc)
 326                 pr_info("NAND could not be registered: %d\n", rc);
 327         return rc;
 328 };
 329
 330 static void ts78xx_ts_nand_unload(void)
 331 {
 332         platform_device_del(&ts78xx_ts_nand_device);
 333 }
 334
 335 /*****************************************************************************
 336  * HW RNG
 337  ****************************************************************************/
 338 #define TS_RNG_DATA     (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
 339
 340 static struct resource ts78xx_ts_rng_resource
 341                         = DEFINE_RES_MEM(TS_RNG_DATA, 4);
 342
 343 static struct timeriomem_rng_data ts78xx_ts_rng_data = {
 344         .period         = 1000000, /* one second */
 345 };
 346
 347 static struct platform_device ts78xx_ts_rng_device = {
 348         .name           = "timeriomem_rng",
 349         .id             = -1,
 350         .dev            = {
 351                 .platform_data  = &ts78xx_ts_rng_data,
 352         },
 353         .resource       = &ts78xx_ts_rng_resource,
 354         .num_resources  = 1,
 355 };
 356
 357 static int ts78xx_ts_rng_load(void)
 358 {
 359         int rc;
 360
 361         if (ts78xx_fpga.supports.ts_rng.init == 0) {
 362                 rc = platform_device_register(&ts78xx_ts_rng_device);
 363                 if (!rc)
 364                         ts78xx_fpga.supports.ts_rng.init = 1;
 365         } else
 366                 rc = platform_device_add(&ts78xx_ts_rng_device);
 367
 368         if (rc)
 369                 pr_info("RNG could not be registered: %d\n", rc);
 370         return rc;
 371 };
 372
 373 static void ts78xx_ts_rng_unload(void)
 374 {
 375         platform_device_del(&ts78xx_ts_rng_device);
 376 }
 377
 378 /*****************************************************************************
 379  * FPGA 'hotplug' support code
 380  ****************************************************************************/
 381 static void ts78xx_fpga_devices_zero_init(void)
 382 {
 383         ts78xx_fpga.supports.ts_rtc.init = 0;
 384         ts78xx_fpga.supports.ts_nand.init = 0;
 385         ts78xx_fpga.supports.ts_rng.init = 0;
 386 }
 387
 388 static void ts78xx_fpga_supports(void)
 389 {
 390         /* TODO: put this 'table' into ts78xx-fpga.h */
 391         switch (ts78xx_fpga.id) {
 392         case TS7800_REV_1:
 393         case TS7800_REV_2:
 394         case TS7800_REV_3:
 395         case TS7800_REV_4:
 396         case TS7800_REV_5:
 397         case TS7800_REV_6:
 398         case TS7800_REV_7:
 399         case TS7800_REV_8:
 400         case TS7800_REV_9:
 401                 ts78xx_fpga.supports.ts_rtc.present = 1;
 402                 ts78xx_fpga.supports.ts_nand.present = 1;
 403                 ts78xx_fpga.supports.ts_rng.present = 1;
 404                 break;
 405         default:
 406                 /* enable devices if magic matches */
 407                 switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
 408                 case TS7800_FPGA_MAGIC:
 409                         pr_warning("unrecognised FPGA revision 0x%.2x\n",
 410                                         ts78xx_fpga.id & 0xff);
 411                         ts78xx_fpga.supports.ts_rtc.present = 1;
 412                         ts78xx_fpga.supports.ts_nand.present = 1;
 413                         ts78xx_fpga.supports.ts_rng.present = 1;
 414                         break;
 415                 default:
 416                         ts78xx_fpga.supports.ts_rtc.present = 0;
 417                         ts78xx_fpga.supports.ts_nand.present = 0;
 418                         ts78xx_fpga.supports.ts_rng.present = 0;
 419                 }
 420         }
 421 }
 422
 423 static int ts78xx_fpga_load_devices(void)
 424 {
 425         int tmp, ret = 0;
 426
 427         if (ts78xx_fpga.supports.ts_rtc.present == 1) {
 428                 tmp = ts78xx_ts_rtc_load();
 429                 if (tmp)
 430                         ts78xx_fpga.supports.ts_rtc.present = 0;
 431                 ret |= tmp;
 432         }
 433         if (ts78xx_fpga.supports.ts_nand.present == 1) {
 434                 tmp = ts78xx_ts_nand_load();
 435                 if (tmp)
 436                         ts78xx_fpga.supports.ts_nand.present = 0;
 437                 ret |= tmp;
 438         }
 439         if (ts78xx_fpga.supports.ts_rng.present == 1) {
 440                 tmp = ts78xx_ts_rng_load();
 441                 if (tmp)
 442                         ts78xx_fpga.supports.ts_rng.present = 0;
 443                 ret |= tmp;
 444         }
 445
 446         return ret;
 447 }
 448
 449 static int ts78xx_fpga_unload_devices(void)
 450 {
 451         int ret = 0;
 452
 453         if (ts78xx_fpga.supports.ts_rtc.present == 1)
 454                 ts78xx_ts_rtc_unload();
 455         if (ts78xx_fpga.supports.ts_nand.present == 1)
 456                 ts78xx_ts_nand_unload();
 457         if (ts78xx_fpga.supports.ts_rng.present == 1)
 458                 ts78xx_ts_rng_unload();
 459
 460         return ret;
 461 }
 462
 463 static int ts78xx_fpga_load(void)
 464 {
 465         ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
 466
 467         pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
 468                         (ts78xx_fpga.id >> 8) & 0xffffff,
 469                         ts78xx_fpga.id & 0xff);
 470
 471         ts78xx_fpga_supports();
 472
 473         if (ts78xx_fpga_load_devices()) {
 474                 ts78xx_fpga.state = -1;
 475                 return -EBUSY;
 476         }
 477
 478         return 0;
 479 };
 480
 481 static int ts78xx_fpga_unload(void)
 482 {
 483         unsigned int fpga_id;
 484
 485         fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
 486
 487         /*
 488          * There does not seem to be a feasible way to block access to the GPIO
 489          * pins from userspace (/dev/mem).  This if clause should hopefully warn
 490          * those foolish enough not to follow 'policy' :)
 491          *
 492          * UrJTAG SVN since r1381 can be used to reprogram the FPGA
 493          */
 494         if (ts78xx_fpga.id != fpga_id) {
 495                 pr_err("FPGA magic/rev mismatch\n"
 496                         "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
 497                         (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
 498                         (fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
 499                 ts78xx_fpga.state = -1;
 500                 return -EBUSY;
 501         }
 502
 503         if (ts78xx_fpga_unload_devices()) {
 504                 ts78xx_fpga.state = -1;
 505                 return -EBUSY;
 506         }
 507
 508         return 0;
 509 };
 510
 511 static ssize_t ts78xx_fpga_show(struct kobject *kobj,
 512                         struct kobj_attribute *attr, char *buf)
 513 {
 514         if (ts78xx_fpga.state < 0)
 515                 return sprintf(buf, "borked\n");
 516
 517         return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
 518 }
 519
 520 static ssize_t ts78xx_fpga_store(struct kobject *kobj,
 521                         struct kobj_attribute *attr, const char *buf, size_t n)
 522 {
 523         int value, ret;
 524
 525         if (ts78xx_fpga.state < 0) {
 526                 pr_err("FPGA borked, you must powercycle ASAP\n");
 527                 return -EBUSY;
 528         }
 529
 530         if (strncmp(buf, "online", sizeof("online") - 1) == 0)
 531                 value = 1;
 532         else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
 533                 value = 0;
 534         else
 535                 return -EINVAL;
 536
 537         if (ts78xx_fpga.state == value)
 538                 return n;
 539
 540         ret = (ts78xx_fpga.state == 0)
 541                 ? ts78xx_fpga_load()
 542                 : ts78xx_fpga_unload();
 543
 544         if (!(ret < 0))
 545                 ts78xx_fpga.state = value;
 546
 547         return n;
 548 }
 549
 550 static struct kobj_attribute ts78xx_fpga_attr =
 551         __ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
 552
 553 /*****************************************************************************
 554  * General Setup
 555  ****************************************************************************/
 556 static unsigned int ts78xx_mpp_modes[] __initdata = {
 557         MPP0_UNUSED,
 558         MPP1_GPIO,              /* JTAG Clock */
 559         MPP2_GPIO,              /* JTAG Data In */
 560         MPP3_GPIO,              /* Lat ECP2 256 FPGA - PB2B */
 561         MPP4_GPIO,              /* JTAG Data Out */
 562         MPP5_GPIO,              /* JTAG TMS */
 563         MPP6_GPIO,              /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
 564         MPP7_GPIO,              /* Lat ECP2 256 FPGA - PB22B */
 565         MPP8_UNUSED,
 566         MPP9_UNUSED,
 567         MPP10_UNUSED,
 568         MPP11_UNUSED,
 569         MPP12_UNUSED,
 570         MPP13_UNUSED,
 571         MPP14_UNUSED,
 572         MPP15_UNUSED,
 573         MPP16_UART,
 574         MPP17_UART,
 575         MPP18_UART,
 576         MPP19_UART,
 577         /*
 578          * MPP[20] PCI Clock Out 1
 579          * MPP[21] PCI Clock Out 0
 580          * MPP[22] Unused
 581          * MPP[23] Unused
 582          * MPP[24] Unused
 583          * MPP[25] Unused
 584          */
 585         0,
 586 };
 587
 588 static void __init ts78xx_init(void)
 589 {
 590         int ret;
 591
 592         /*
 593          * Setup basic Orion functions. Need to be called early.
 594          */
 595         orion5x_init();
 596
 597         orion5x_mpp_conf(ts78xx_mpp_modes);
 598
 599         /*
 600          * Configure peripherals.
 601          */
 602         orion5x_ehci0_init();
 603         orion5x_ehci1_init();
 604         orion5x_eth_init(&ts78xx_eth_data);
 605         orion5x_sata_init(&ts78xx_sata_data);
 606         orion5x_uart0_init();
 607         orion5x_uart1_init();
 608         orion5x_xor_init();
 609
 610         /* FPGA init */
 611         ts78xx_fpga_devices_zero_init();
 612         ret = ts78xx_fpga_load();
 613         ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
 614         if (ret)
 615                 pr_err("sysfs_create_file failed: %d\n", ret);
 616 }
 617
 618 MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
 619         /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
 620         .atag_offset    = 0x100,
 621         .init_machine   = ts78xx_init,
 622         .map_io         = ts78xx_map_io,
 623         .init_early     = orion5x_init_early,
 624         .init_irq       = orion5x_init_irq,
 625         .timer          = &orion5x_timer,
 626         .restart        = orion5x_restart,
 627 MACHINE_END