Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/vc.c

   1 /*
   2  * OMAP Voltage Controller (VC) interface
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13
  14 #include <plat/cpu.h>
  15
  16 #include "voltage.h"
  17 #include "vc.h"
  18 #include "prm-regbits-34xx.h"
  19 #include "prm-regbits-44xx.h"
  20 #include "prm44xx.h"
  21
  22 /**
  23  * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
  24  * @sa: bit for slave address
  25  * @rav: bit for voltage configuration register
  26  * @rac: bit for command configuration register
  27  * @racen: enable bit for RAC
  28  * @cmd: bit for command value set selection
  29  *
  30  * Channel configuration bits, common for OMAP3+
  31  * OMAP3 register: PRM_VC_CH_CONF
  32  * OMAP4 register: PRM_VC_CFG_CHANNEL
  33  * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
  34  */
  35 struct omap_vc_channel_cfg {
  36         u8 sa;
  37         u8 rav;
  38         u8 rac;
  39         u8 racen;
  40         u8 cmd;
  41 };
  42
  43 static struct omap_vc_channel_cfg vc_default_channel_cfg = {
  44         .sa    = BIT(0),
  45         .rav   = BIT(1),
  46         .rac   = BIT(2),
  47         .racen = BIT(3),
  48         .cmd   = BIT(4),
  49 };
  50
  51 /*
  52  * On OMAP3+, all VC channels have the above default bitfield
  53  * configuration, except the OMAP4 MPU channel.  This appears
  54  * to be a freak accident as every other VC channel has the
  55  * default configuration, thus creating a mutant channel config.
  56  */
  57 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
  58         .sa    = BIT(0),
  59         .rav   = BIT(2),
  60         .rac   = BIT(3),
  61         .racen = BIT(4),
  62         .cmd   = BIT(1),
  63 };
  64
  65 static struct omap_vc_channel_cfg *vc_cfg_bits;
  66 #define CFG_CHANNEL_MASK 0x1f
  67
  68 /**
  69  * omap_vc_config_channel - configure VC channel to PMIC mappings
  70  * @voltdm: pointer to voltagdomain defining the desired VC channel
  71  *
  72  * Configures the VC channel to PMIC mappings for the following
  73  * PMIC settings
  74  * - i2c slave address (SA)
  75  * - voltage configuration address (RAV)
  76  * - command configuration address (RAC) and enable bit (RACEN)
  77  * - command values for ON, ONLP, RET and OFF (CMD)
  78  *
  79  * This function currently only allows flexible configuration of the
  80  * non-default channel.  Starting with OMAP4, there are more than 2
  81  * channels, with one defined as the default (on OMAP4, it's MPU.)
  82  * Only the non-default channel can be configured.
  83  */
  84 static int omap_vc_config_channel(struct voltagedomain *voltdm)
  85 {
  86         struct omap_vc_channel *vc = voltdm->vc;
  87
  88         /*
  89          * For default channel, the only configurable bit is RACEN.
  90          * All others must stay at zero (see function comment above.)
  91          */
  92         if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
  93                 vc->cfg_channel &= vc_cfg_bits->racen;
  94
  95         voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
  96                     vc->cfg_channel << vc->cfg_channel_sa_shift,
  97                     vc->common->cfg_channel_reg);
  98
  99         return 0;
 100 }
 101
 102 /* Voltage scale and accessory APIs */
 103 int omap_vc_pre_scale(struct voltagedomain *voltdm,
 104                       unsigned long target_volt,
 105                       u8 *target_vsel, u8 *current_vsel)
 106 {
 107         struct omap_vc_channel *vc = voltdm->vc;
 108         u32 vc_cmdval;
 109
 110         /* Check if sufficient pmic info is available for this vdd */
 111         if (!voltdm->pmic) {
 112                 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
 113                         __func__, voltdm->name);
 114                 return -EINVAL;
 115         }
 116
 117         if (!voltdm->pmic->uv_to_vsel) {
 118                 pr_err("%s: PMIC function to convert voltage in uV to"
 119                         "vsel not registered. Hence unable to scale voltage"
 120                         "for vdd_%s\n", __func__, voltdm->name);
 121                 return -ENODATA;
 122         }
 123
 124         if (!voltdm->read || !voltdm->write) {
 125                 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 126                         __func__, voltdm->name);
 127                 return -EINVAL;
 128         }
 129
 130         *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
 131         *current_vsel = voltdm->pmic->uv_to_vsel(vdd->curr_volt);
 132
 133         /* Setting the ON voltage to the new target voltage */
 134         vc_cmdval = voltdm->read(vc->cmdval_reg);
 135         vc_cmdval &= ~vc->common->cmd_on_mask;
 136         vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
 137         voltdm->write(vc_cmdval, vc->cmdval_reg);
 138
 139         omap_vp_update_errorgain(voltdm, target_volt);
 140
 141         return 0;
 142 }
 143
 144 void omap_vc_post_scale(struct voltagedomain *voltdm,
 145                         unsigned long target_volt,
 146                         u8 target_vsel, u8 current_vsel)
 147 {
 148         struct omap_vdd_info *vdd = voltdm->vdd;
 149         u32 smps_steps = 0, smps_delay = 0;
 150
 151         smps_steps = abs(target_vsel - current_vsel);
 152         /* SMPS slew rate / step size. 2us added as buffer. */
 153         smps_delay = ((smps_steps * voltdm->pmic->step_size) /
 154                         voltdm->pmic->slew_rate) + 2;
 155         udelay(smps_delay);
 156
 157         vdd->curr_volt = target_volt;
 158 }
 159
 160 /* vc_bypass_scale - VC bypass method of voltage scaling */
 161 int omap_vc_bypass_scale(struct voltagedomain *voltdm,
 162                          unsigned long target_volt)
 163 {
 164         struct omap_vc_channel *vc = voltdm->vc;
 165         u32 loop_cnt = 0, retries_cnt = 0;
 166         u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
 167         u8 target_vsel, current_vsel;
 168         int ret;
 169
 170         ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
 171         if (ret)
 172                 return ret;
 173
 174         vc_valid = vc->common->valid;
 175         vc_bypass_val_reg = vc->common->bypass_val_reg;
 176         vc_bypass_value = (target_vsel << vc->common->data_shift) |
 177                 (vc->volt_reg_addr << vc->common->regaddr_shift) |
 178                 (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
 179
 180         voltdm->write(vc_bypass_value, vc_bypass_val_reg);
 181         voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
 182
 183         vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 184         /*
 185          * Loop till the bypass command is acknowledged from the SMPS.
 186          * NOTE: This is legacy code. The loop count and retry count needs
 187          * to be revisited.
 188          */
 189         while (!(vc_bypass_value & vc_valid)) {
 190                 loop_cnt++;
 191
 192                 if (retries_cnt > 10) {
 193                         pr_warning("%s: Retry count exceeded\n", __func__);
 194                         return -ETIMEDOUT;
 195                 }
 196
 197                 if (loop_cnt > 50) {
 198                         retries_cnt++;
 199                         loop_cnt = 0;
 200                         udelay(10);
 201                 }
 202                 vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 203         }
 204
 205         omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
 206         return 0;
 207 }
 208
 209 static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
 210 {
 211         /*
 212          * Voltage Manager FSM parameters init
 213          * XXX This data should be passed in from the board file
 214          */
 215         voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
 216         voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
 217         voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
 218 }
 219
 220 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
 221 {
 222         static bool is_initialized;
 223
 224         if (is_initialized)
 225                 return;
 226
 227         omap3_vfsm_init(voltdm);
 228
 229         is_initialized = true;
 230 }
 231
 232
 233 /* OMAP4 specific voltage init functions */
 234 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
 235 {
 236         static bool is_initialized;
 237         u32 vc_val;
 238
 239         if (is_initialized)
 240                 return;
 241
 242         /* XXX These are magic numbers and do not belong! */
 243         vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
 244         voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
 245
 246         is_initialized = true;
 247 }
 248
 249 /**
 250  * omap_vc_i2c_init - initialize I2C interface to PMIC
 251  * @voltdm: voltage domain containing VC data
 252  *
 253  * Use PMIC supplied seetings for I2C high-speed mode and
 254  * master code (if set) and program the VC I2C configuration
 255  * register.
 256  *
 257  * The VC I2C configuration is common to all VC channels,
 258  * so this function only configures I2C for the first VC
 259  * channel registers.  All other VC channels will use the
 260  * same configuration.
 261  */
 262 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
 263 {
 264         struct omap_vc_channel *vc = voltdm->vc;
 265         static bool initialized;
 266         static bool i2c_high_speed;
 267         u8 mcode;
 268
 269         if (initialized) {
 270                 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
 271                         pr_warn("%s: I2C config for all channels must match.",
 272                                 __func__);
 273                 return;
 274         }
 275
 276         i2c_high_speed = voltdm->pmic->i2c_high_speed;
 277         if (i2c_high_speed)
 278                 voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
 279                             vc->common->i2c_cfg_hsen_mask,
 280                             vc->common->i2c_cfg_reg);
 281
 282         mcode = voltdm->pmic->i2c_mcode;
 283         if (mcode)
 284                 voltdm->rmw(vc->common->i2c_mcode_mask,
 285                             mcode << __ffs(vc->common->i2c_mcode_mask),
 286                             vc->common->i2c_cfg_reg);
 287
 288         initialized = true;
 289 }
 290
 291 void __init omap_vc_init_channel(struct voltagedomain *voltdm)
 292 {
 293         struct omap_vc_channel *vc = voltdm->vc;
 294         u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
 295         u32 val;
 296
 297         if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
 298                 pr_err("%s: PMIC info requried to configure vc for"
 299                         "vdd_%s not populated.Hence cannot initialize vc\n",
 300                         __func__, voltdm->name);
 301                 return;
 302         }
 303
 304         if (!voltdm->read || !voltdm->write) {
 305                 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 306                         __func__, voltdm->name);
 307                 return;
 308         }
 309
 310         vc->cfg_channel = 0;
 311         if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
 312                 vc_cfg_bits = &vc_mutant_channel_cfg;
 313         else
 314                 vc_cfg_bits = &vc_default_channel_cfg;
 315
 316         /* get PMIC/board specific settings */
 317         vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
 318         vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
 319         vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
 320         vc->setup_time = voltdm->pmic->volt_setup_time;
 321
 322         /* Configure the i2c slave address for this VC */
 323         voltdm->rmw(vc->smps_sa_mask,
 324                     vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
 325                     vc->common->smps_sa_reg);
 326         vc->cfg_channel |= vc_cfg_bits->sa;
 327
 328         /*
 329          * Configure the PMIC register addresses.
 330          */
 331         voltdm->rmw(vc->smps_volra_mask,
 332                     vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
 333                     vc->common->smps_volra_reg);
 334         vc->cfg_channel |= vc_cfg_bits->rav;
 335
 336         if (vc->cmd_reg_addr) {
 337                 voltdm->rmw(vc->smps_cmdra_mask,
 338                             vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
 339                             vc->common->smps_cmdra_reg);
 340                 vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
 341         }
 342
 343         /* Set up the on, inactive, retention and off voltage */
 344         on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
 345         onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
 346         ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
 347         off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
 348         val = ((on_vsel << vc->common->cmd_on_shift) |
 349                (onlp_vsel << vc->common->cmd_onlp_shift) |
 350                (ret_vsel << vc->common->cmd_ret_shift) |
 351                (off_vsel << vc->common->cmd_off_shift));
 352         voltdm->write(val, vc->cmdval_reg);
 353         vc->cfg_channel |= vc_cfg_bits->cmd;
 354
 355         /* Channel configuration */
 356         omap_vc_config_channel(voltdm);
 357
 358         /* Configure the setup times */
 359         voltdm->rmw(voltdm->vfsm->voltsetup_mask,
 360                     vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
 361                     voltdm->vfsm->voltsetup_reg);
 362
 363         omap_vc_i2c_init(voltdm);
 364
 365         if (cpu_is_omap34xx())
 366                 omap3_vc_init_channel(voltdm);
 367         else if (cpu_is_omap44xx())
 368                 omap4_vc_init_channel(voltdm);
 369 }
 370