Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/vc.c

   1 /*
   2  * OMAP Voltage Controller (VC) interface
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/bug.h>
  14
  15 #include "soc.h"
  16 #include "voltage.h"
  17 #include "vc.h"
  18 #include "prm-regbits-34xx.h"
  19 #include "prm-regbits-44xx.h"
  20 #include "prm44xx.h"
  21
  22 /**
  23  * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
  24  * @sa: bit for slave address
  25  * @rav: bit for voltage configuration register
  26  * @rac: bit for command configuration register
  27  * @racen: enable bit for RAC
  28  * @cmd: bit for command value set selection
  29  *
  30  * Channel configuration bits, common for OMAP3+
  31  * OMAP3 register: PRM_VC_CH_CONF
  32  * OMAP4 register: PRM_VC_CFG_CHANNEL
  33  * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
  34  */
  35 struct omap_vc_channel_cfg {
  36         u8 sa;
  37         u8 rav;
  38         u8 rac;
  39         u8 racen;
  40         u8 cmd;
  41 };
  42
  43 static struct omap_vc_channel_cfg vc_default_channel_cfg = {
  44         .sa    = BIT(0),
  45         .rav   = BIT(1),
  46         .rac   = BIT(2),
  47         .racen = BIT(3),
  48         .cmd   = BIT(4),
  49 };
  50
  51 /*
  52  * On OMAP3+, all VC channels have the above default bitfield
  53  * configuration, except the OMAP4 MPU channel.  This appears
  54  * to be a freak accident as every other VC channel has the
  55  * default configuration, thus creating a mutant channel config.
  56  */
  57 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
  58         .sa    = BIT(0),
  59         .rav   = BIT(2),
  60         .rac   = BIT(3),
  61         .racen = BIT(4),
  62         .cmd   = BIT(1),
  63 };
  64
  65 static struct omap_vc_channel_cfg *vc_cfg_bits;
  66 #define CFG_CHANNEL_MASK 0x1f
  67
  68 /**
  69  * omap_vc_config_channel - configure VC channel to PMIC mappings
  70  * @voltdm: pointer to voltagdomain defining the desired VC channel
  71  *
  72  * Configures the VC channel to PMIC mappings for the following
  73  * PMIC settings
  74  * - i2c slave address (SA)
  75  * - voltage configuration address (RAV)
  76  * - command configuration address (RAC) and enable bit (RACEN)
  77  * - command values for ON, ONLP, RET and OFF (CMD)
  78  *
  79  * This function currently only allows flexible configuration of the
  80  * non-default channel.  Starting with OMAP4, there are more than 2
  81  * channels, with one defined as the default (on OMAP4, it's MPU.)
  82  * Only the non-default channel can be configured.
  83  */
  84 static int omap_vc_config_channel(struct voltagedomain *voltdm)
  85 {
  86         struct omap_vc_channel *vc = voltdm->vc;
  87
  88         /*
  89          * For default channel, the only configurable bit is RACEN.
  90          * All others must stay at zero (see function comment above.)
  91          */
  92         if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
  93                 vc->cfg_channel &= vc_cfg_bits->racen;
  94
  95         voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
  96                     vc->cfg_channel << vc->cfg_channel_sa_shift,
  97                     vc->cfg_channel_reg);
  98
  99         return 0;
 100 }
 101
 102 /* Voltage scale and accessory APIs */
 103 int omap_vc_pre_scale(struct voltagedomain *voltdm,
 104                       unsigned long target_volt,
 105                       u8 *target_vsel, u8 *current_vsel)
 106 {
 107         struct omap_vc_channel *vc = voltdm->vc;
 108         u32 vc_cmdval;
 109
 110         /* Check if sufficient pmic info is available for this vdd */
 111         if (!voltdm->pmic) {
 112                 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
 113                         __func__, voltdm->name);
 114                 return -EINVAL;
 115         }
 116
 117         if (!voltdm->pmic->uv_to_vsel) {
 118                 pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
 119                        __func__, voltdm->name);
 120                 return -ENODATA;
 121         }
 122
 123         if (!voltdm->read || !voltdm->write) {
 124                 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 125                         __func__, voltdm->name);
 126                 return -EINVAL;
 127         }
 128
 129         *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
 130         *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
 131
 132         /* Setting the ON voltage to the new target voltage */
 133         vc_cmdval = voltdm->read(vc->cmdval_reg);
 134         vc_cmdval &= ~vc->common->cmd_on_mask;
 135         vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
 136         voltdm->write(vc_cmdval, vc->cmdval_reg);
 137
 138         voltdm->vc_param->on = target_volt;
 139
 140         omap_vp_update_errorgain(voltdm, target_volt);
 141
 142         return 0;
 143 }
 144
 145 void omap_vc_post_scale(struct voltagedomain *voltdm,
 146                         unsigned long target_volt,
 147                         u8 target_vsel, u8 current_vsel)
 148 {
 149         u32 smps_steps = 0, smps_delay = 0;
 150
 151         smps_steps = abs(target_vsel - current_vsel);
 152         /* SMPS slew rate / step size. 2us added as buffer. */
 153         smps_delay = ((smps_steps * voltdm->pmic->step_size) /
 154                         voltdm->pmic->slew_rate) + 2;
 155         udelay(smps_delay);
 156 }
 157
 158 /* vc_bypass_scale - VC bypass method of voltage scaling */
 159 int omap_vc_bypass_scale(struct voltagedomain *voltdm,
 160                          unsigned long target_volt)
 161 {
 162         struct omap_vc_channel *vc = voltdm->vc;
 163         u32 loop_cnt = 0, retries_cnt = 0;
 164         u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
 165         u8 target_vsel, current_vsel;
 166         int ret;
 167
 168         ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
 169         if (ret)
 170                 return ret;
 171
 172         vc_valid = vc->common->valid;
 173         vc_bypass_val_reg = vc->common->bypass_val_reg;
 174         vc_bypass_value = (target_vsel << vc->common->data_shift) |
 175                 (vc->volt_reg_addr << vc->common->regaddr_shift) |
 176                 (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
 177
 178         voltdm->write(vc_bypass_value, vc_bypass_val_reg);
 179         voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
 180
 181         vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 182         /*
 183          * Loop till the bypass command is acknowledged from the SMPS.
 184          * NOTE: This is legacy code. The loop count and retry count needs
 185          * to be revisited.
 186          */
 187         while (!(vc_bypass_value & vc_valid)) {
 188                 loop_cnt++;
 189
 190                 if (retries_cnt > 10) {
 191                         pr_warning("%s: Retry count exceeded\n", __func__);
 192                         return -ETIMEDOUT;
 193                 }
 194
 195                 if (loop_cnt > 50) {
 196                         retries_cnt++;
 197                         loop_cnt = 0;
 198                         udelay(10);
 199                 }
 200                 vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 201         }
 202
 203         omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
 204         return 0;
 205 }
 206
 207 static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
 208 {
 209         /*
 210          * Voltage Manager FSM parameters init
 211          * XXX This data should be passed in from the board file
 212          */
 213         voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
 214         voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
 215         voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
 216 }
 217
 218 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
 219 {
 220         static bool is_initialized;
 221
 222         if (is_initialized)
 223                 return;
 224
 225         omap3_vfsm_init(voltdm);
 226
 227         is_initialized = true;
 228 }
 229
 230
 231 /* OMAP4 specific voltage init functions */
 232 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
 233 {
 234         static bool is_initialized;
 235         u32 vc_val;
 236
 237         if (is_initialized)
 238                 return;
 239
 240         /* XXX These are magic numbers and do not belong! */
 241         vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
 242         voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
 243
 244         is_initialized = true;
 245 }
 246
 247 /**
 248  * omap_vc_i2c_init - initialize I2C interface to PMIC
 249  * @voltdm: voltage domain containing VC data
 250  *
 251  * Use PMIC supplied settings for I2C high-speed mode and
 252  * master code (if set) and program the VC I2C configuration
 253  * register.
 254  *
 255  * The VC I2C configuration is common to all VC channels,
 256  * so this function only configures I2C for the first VC
 257  * channel registers.  All other VC channels will use the
 258  * same configuration.
 259  */
 260 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
 261 {
 262         struct omap_vc_channel *vc = voltdm->vc;
 263         static bool initialized;
 264         static bool i2c_high_speed;
 265         u8 mcode;
 266
 267         if (initialized) {
 268                 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
 269                         pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).",
 270                                 __func__, voltdm->name, i2c_high_speed);
 271                 return;
 272         }
 273
 274         i2c_high_speed = voltdm->pmic->i2c_high_speed;
 275         if (i2c_high_speed)
 276                 voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
 277                             vc->common->i2c_cfg_hsen_mask,
 278                             vc->common->i2c_cfg_reg);
 279
 280         mcode = voltdm->pmic->i2c_mcode;
 281         if (mcode)
 282                 voltdm->rmw(vc->common->i2c_mcode_mask,
 283                             mcode << __ffs(vc->common->i2c_mcode_mask),
 284                             vc->common->i2c_cfg_reg);
 285
 286         initialized = true;
 287 }
 288
 289 /**
 290  * omap_vc_calc_vsel - calculate vsel value for a channel
 291  * @voltdm: channel to calculate value for
 292  * @uvolt: microvolt value to convert to vsel
 293  *
 294  * Converts a microvolt value to vsel value for the used PMIC.
 295  * This checks whether the microvolt value is out of bounds, and
 296  * adjusts the value accordingly. If unsupported value detected,
 297  * warning is thrown.
 298  */
 299 static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
 300 {
 301         if (voltdm->pmic->vddmin > uvolt)
 302                 uvolt = voltdm->pmic->vddmin;
 303         if (voltdm->pmic->vddmax < uvolt) {
 304                 WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
 305                         __func__, uvolt, voltdm->pmic->vddmax);
 306                 /* Lets try maximum value anyway */
 307                 uvolt = voltdm->pmic->vddmax;
 308         }
 309
 310         return voltdm->pmic->uv_to_vsel(uvolt);
 311 }
 312
 313 void __init omap_vc_init_channel(struct voltagedomain *voltdm)
 314 {
 315         struct omap_vc_channel *vc = voltdm->vc;
 316         u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
 317         u32 val;
 318
 319         if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
 320                 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
 321                 return;
 322         }
 323
 324         if (!voltdm->read || !voltdm->write) {
 325                 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 326                         __func__, voltdm->name);
 327                 return;
 328         }
 329
 330         vc->cfg_channel = 0;
 331         if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
 332                 vc_cfg_bits = &vc_mutant_channel_cfg;
 333         else
 334                 vc_cfg_bits = &vc_default_channel_cfg;
 335
 336         /* get PMIC/board specific settings */
 337         vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
 338         vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
 339         vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
 340         vc->setup_time = voltdm->pmic->volt_setup_time;
 341
 342         /* Configure the i2c slave address for this VC */
 343         voltdm->rmw(vc->smps_sa_mask,
 344                     vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
 345                     vc->smps_sa_reg);
 346         vc->cfg_channel |= vc_cfg_bits->sa;
 347
 348         /*
 349          * Configure the PMIC register addresses.
 350          */
 351         voltdm->rmw(vc->smps_volra_mask,
 352                     vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
 353                     vc->smps_volra_reg);
 354         vc->cfg_channel |= vc_cfg_bits->rav;
 355
 356         if (vc->cmd_reg_addr) {
 357                 voltdm->rmw(vc->smps_cmdra_mask,
 358                             vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
 359                             vc->smps_cmdra_reg);
 360                 vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
 361         }
 362
 363         /* Set up the on, inactive, retention and off voltage */
 364         on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
 365         onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
 366         ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
 367         off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
 368
 369         val = ((on_vsel << vc->common->cmd_on_shift) |
 370                (onlp_vsel << vc->common->cmd_onlp_shift) |
 371                (ret_vsel << vc->common->cmd_ret_shift) |
 372                (off_vsel << vc->common->cmd_off_shift));
 373         voltdm->write(val, vc->cmdval_reg);
 374         vc->cfg_channel |= vc_cfg_bits->cmd;
 375
 376         /* Channel configuration */
 377         omap_vc_config_channel(voltdm);
 378
 379         /* Configure the setup times */
 380         voltdm->rmw(voltdm->vfsm->voltsetup_mask,
 381                     vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
 382                     voltdm->vfsm->voltsetup_reg);
 383
 384         omap_vc_i2c_init(voltdm);
 385
 386         if (cpu_is_omap34xx())
 387                 omap3_vc_init_channel(voltdm);
 388         else if (cpu_is_omap44xx())
 389                 omap4_vc_init_channel(voltdm);
 390 }
 391