Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/powerdomains54xx_data.c

   1 /*
   2  * OMAP54XX Power domains framework
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Abhijit Pagare (abhijitpagare@ti.com)
   7  * Benoit Cousson (b-cousson@ti.com)
   8  * Paul Walmsley (paul@pwsan.com)
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23
  24 #include "powerdomain.h"
  25
  26 #include "prcm-common.h"
  27 #include "prcm44xx.h"
  28 #include "prm-regbits-54xx.h"
  29 #include "prm54xx.h"
  30 #include "prcm_mpu54xx.h"
  31
  32 /* core_54xx_pwrdm: CORE power domain */
  33 static struct powerdomain core_54xx_pwrdm = {
  34         .name             = "core_pwrdm",
  35         .voltdm           = { .name = "core" },
  36         .prcm_offs        = OMAP54XX_PRM_CORE_INST,
  37         .prcm_partition   = OMAP54XX_PRM_PARTITION,
  38         .pwrsts           = PWRSTS_RET_ON,
  39         .pwrsts_logic_ret = PWRSTS_OFF_RET,
  40         .banks            = 5,
  41         .pwrsts_mem_ret = {
  42                 [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
  43                 [1] = PWRSTS_OFF_RET,   /* core_ocmram */
  44                 [2] = PWRSTS_OFF_RET,   /* core_other_bank */
  45                 [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
  46                 [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
  47         },
  48         .pwrsts_mem_on  = {
  49                 [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
  50                 [1] = PWRSTS_OFF_RET,   /* core_ocmram */
  51                 [2] = PWRSTS_OFF_RET,   /* core_other_bank */
  52                 [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
  53                 [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
  54         },
  55         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  56 };
  57
  58 /* abe_54xx_pwrdm: Audio back end power domain */
  59 static struct powerdomain abe_54xx_pwrdm = {
  60         .name             = "abe_pwrdm",
  61         .voltdm           = { .name = "core" },
  62         .prcm_offs        = OMAP54XX_PRM_ABE_INST,
  63         .prcm_partition   = OMAP54XX_PRM_PARTITION,
  64         .pwrsts           = PWRSTS_OFF_RET_ON,
  65         .pwrsts_logic_ret = PWRSTS_OFF,
  66         .banks            = 2,
  67         .pwrsts_mem_ret = {
  68                 [0] = PWRSTS_OFF_RET,   /* aessmem */
  69                 [1] = PWRSTS_OFF_RET,   /* periphmem */
  70         },
  71         .pwrsts_mem_on  = {
  72                 [0] = PWRSTS_OFF_RET,   /* aessmem */
  73                 [1] = PWRSTS_OFF_RET,   /* periphmem */
  74         },
  75         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  76 };
  77
  78 /* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
  79 static struct powerdomain coreaon_54xx_pwrdm = {
  80         .name             = "coreaon_pwrdm",
  81         .voltdm           = { .name = "core" },
  82         .prcm_offs        = OMAP54XX_PRM_COREAON_INST,
  83         .prcm_partition   = OMAP54XX_PRM_PARTITION,
  84         .pwrsts           = PWRSTS_ON,
  85 };
  86
  87 /* dss_54xx_pwrdm: Display subsystem power domain */
  88 static struct powerdomain dss_54xx_pwrdm = {
  89         .name             = "dss_pwrdm",
  90         .voltdm           = { .name = "core" },
  91         .prcm_offs        = OMAP54XX_PRM_DSS_INST,
  92         .prcm_partition   = OMAP54XX_PRM_PARTITION,
  93         .pwrsts           = PWRSTS_OFF_RET_ON,
  94         .pwrsts_logic_ret = PWRSTS_OFF,
  95         .banks            = 1,
  96         .pwrsts_mem_ret = {
  97                 [0] = PWRSTS_OFF_RET,   /* dss_mem */
  98         },
  99         .pwrsts_mem_on  = {
 100                 [0] = PWRSTS_OFF_RET,   /* dss_mem */
 101         },
 102         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 103 };
 104
 105 /* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
 106 static struct powerdomain cpu0_54xx_pwrdm = {
 107         .name             = "cpu0_pwrdm",
 108         .voltdm           = { .name = "mpu" },
 109         .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C0_INST,
 110         .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
 111         .pwrsts           = PWRSTS_OFF_RET_ON,
 112         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 113         .banks            = 1,
 114         .pwrsts_mem_ret = {
 115                 [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
 116         },
 117         .pwrsts_mem_on  = {
 118                 [0] = PWRSTS_ON,        /* cpu0_l1 */
 119         },
 120 };
 121
 122 /* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
 123 static struct powerdomain cpu1_54xx_pwrdm = {
 124         .name             = "cpu1_pwrdm",
 125         .voltdm           = { .name = "mpu" },
 126         .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C1_INST,
 127         .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
 128         .pwrsts           = PWRSTS_OFF_RET_ON,
 129         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 130         .banks            = 1,
 131         .pwrsts_mem_ret = {
 132                 [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
 133         },
 134         .pwrsts_mem_on  = {
 135                 [0] = PWRSTS_ON,        /* cpu1_l1 */
 136         },
 137 };
 138
 139 /* emu_54xx_pwrdm: Emulation power domain */
 140 static struct powerdomain emu_54xx_pwrdm = {
 141         .name             = "emu_pwrdm",
 142         .voltdm           = { .name = "wkup" },
 143         .prcm_offs        = OMAP54XX_PRM_EMU_INST,
 144         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 145         .pwrsts           = PWRSTS_OFF_ON,
 146         .banks            = 1,
 147         .pwrsts_mem_ret = {
 148                 [0] = PWRSTS_OFF_RET,   /* emu_bank */
 149         },
 150         .pwrsts_mem_on  = {
 151                 [0] = PWRSTS_OFF_RET,   /* emu_bank */
 152         },
 153 };
 154
 155 /* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
 156 static struct powerdomain mpu_54xx_pwrdm = {
 157         .name             = "mpu_pwrdm",
 158         .voltdm           = { .name = "mpu" },
 159         .prcm_offs        = OMAP54XX_PRM_MPU_INST,
 160         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 161         .pwrsts           = PWRSTS_RET_ON,
 162         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 163         .banks            = 2,
 164         .pwrsts_mem_ret = {
 165                 [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
 166                 [1] = PWRSTS_RET,       /* mpu_ram */
 167         },
 168         .pwrsts_mem_on  = {
 169                 [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
 170                 [1] = PWRSTS_OFF_RET,   /* mpu_ram */
 171         },
 172 };
 173
 174 /* custefuse_54xx_pwrdm: Customer efuse controller power domain */
 175 static struct powerdomain custefuse_54xx_pwrdm = {
 176         .name             = "custefuse_pwrdm",
 177         .voltdm           = { .name = "core" },
 178         .prcm_offs        = OMAP54XX_PRM_CUSTEFUSE_INST,
 179         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 180         .pwrsts           = PWRSTS_OFF_ON,
 181         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 182 };
 183
 184 /* dsp_54xx_pwrdm: Tesla processor power domain */
 185 static struct powerdomain dsp_54xx_pwrdm = {
 186         .name             = "dsp_pwrdm",
 187         .voltdm           = { .name = "mm" },
 188         .prcm_offs        = OMAP54XX_PRM_DSP_INST,
 189         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 190         .pwrsts           = PWRSTS_OFF_RET_ON,
 191         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 192         .banks            = 3,
 193         .pwrsts_mem_ret = {
 194                 [0] = PWRSTS_OFF_RET,   /* dsp_edma */
 195                 [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
 196                 [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
 197         },
 198         .pwrsts_mem_on  = {
 199                 [0] = PWRSTS_OFF_RET,   /* dsp_edma */
 200                 [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
 201                 [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
 202         },
 203         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 204 };
 205
 206 /* cam_54xx_pwrdm: Camera subsystem power domain */
 207 static struct powerdomain cam_54xx_pwrdm = {
 208         .name             = "cam_pwrdm",
 209         .voltdm           = { .name = "core" },
 210         .prcm_offs        = OMAP54XX_PRM_CAM_INST,
 211         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 212         .pwrsts           = PWRSTS_OFF_ON,
 213         .banks            = 1,
 214         .pwrsts_mem_ret = {
 215                 [0] = PWRSTS_OFF_RET,   /* cam_mem */
 216         },
 217         .pwrsts_mem_on  = {
 218                 [0] = PWRSTS_OFF_RET,   /* cam_mem */
 219         },
 220         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 221 };
 222
 223 /* l3init_54xx_pwrdm: L3 initators pheripherals power domain  */
 224 static struct powerdomain l3init_54xx_pwrdm = {
 225         .name             = "l3init_pwrdm",
 226         .voltdm           = { .name = "core" },
 227         .prcm_offs        = OMAP54XX_PRM_L3INIT_INST,
 228         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 229         .pwrsts           = PWRSTS_RET_ON,
 230         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 231         .banks            = 2,
 232         .pwrsts_mem_ret = {
 233                 [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
 234                 [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
 235         },
 236         .pwrsts_mem_on  = {
 237                 [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
 238                 [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
 239         },
 240         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 241 };
 242
 243 /* gpu_54xx_pwrdm: 3D accelerator power domain */
 244 static struct powerdomain gpu_54xx_pwrdm = {
 245         .name             = "gpu_pwrdm",
 246         .voltdm           = { .name = "mm" },
 247         .prcm_offs        = OMAP54XX_PRM_GPU_INST,
 248         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 249         .pwrsts           = PWRSTS_OFF_ON,
 250         .banks            = 1,
 251         .pwrsts_mem_ret = {
 252                 [0] = PWRSTS_OFF_RET,   /* gpu_mem */
 253         },
 254         .pwrsts_mem_on  = {
 255                 [0] = PWRSTS_OFF_RET,   /* gpu_mem */
 256         },
 257         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 258 };
 259
 260 /* wkupaon_54xx_pwrdm: Wake-up power domain */
 261 static struct powerdomain wkupaon_54xx_pwrdm = {
 262         .name             = "wkupaon_pwrdm",
 263         .voltdm           = { .name = "wkup" },
 264         .prcm_offs        = OMAP54XX_PRM_WKUPAON_INST,
 265         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 266         .pwrsts           = PWRSTS_ON,
 267         .banks            = 1,
 268         .pwrsts_mem_ret = {
 269         },
 270         .pwrsts_mem_on  = {
 271                 [0] = PWRSTS_ON,        /* wkup_bank */
 272         },
 273 };
 274
 275 /* iva_54xx_pwrdm: IVA-HD power domain */
 276 static struct powerdomain iva_54xx_pwrdm = {
 277         .name             = "iva_pwrdm",
 278         .voltdm           = { .name = "mm" },
 279         .prcm_offs        = OMAP54XX_PRM_IVA_INST,
 280         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 281         .pwrsts           = PWRSTS_OFF_RET_ON,
 282         .pwrsts_logic_ret = PWRSTS_OFF,
 283         .banks            = 4,
 284         .pwrsts_mem_ret = {
 285                 [0] = PWRSTS_OFF_RET,   /* hwa_mem */
 286                 [1] = PWRSTS_OFF_RET,   /* sl2_mem */
 287                 [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
 288                 [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
 289         },
 290         .pwrsts_mem_on  = {
 291                 [0] = PWRSTS_OFF_RET,   /* hwa_mem */
 292                 [1] = PWRSTS_OFF_RET,   /* sl2_mem */
 293                 [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
 294                 [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
 295         },
 296         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 297 };
 298
 299 /*
 300  * The following power domains are not under SW control
 301  *
 302  * mpuaon
 303  * mmaon
 304  */
 305
 306 /* As powerdomains are added or removed above, this list must also be changed */
 307 static struct powerdomain *powerdomains_omap54xx[] __initdata = {
 308         &core_54xx_pwrdm,
 309         &abe_54xx_pwrdm,
 310         &coreaon_54xx_pwrdm,
 311         &dss_54xx_pwrdm,
 312         &cpu0_54xx_pwrdm,
 313         &cpu1_54xx_pwrdm,
 314         &emu_54xx_pwrdm,
 315         &mpu_54xx_pwrdm,
 316         &custefuse_54xx_pwrdm,
 317         &dsp_54xx_pwrdm,
 318         &cam_54xx_pwrdm,
 319         &l3init_54xx_pwrdm,
 320         &gpu_54xx_pwrdm,
 321         &wkupaon_54xx_pwrdm,
 322         &iva_54xx_pwrdm,
 323         NULL
 324 };
 325
 326 void __init omap54xx_powerdomains_init(void)
 327 {
 328         pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
 329         pwrdm_register_pwrdms(powerdomains_omap54xx);
 330         pwrdm_complete_init();
 331 }