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Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211
[~andy/linux] / arch / arm / mach-omap2 / pm24xx.c
1 /*
2  * OMAP2 Power Management Routines
3  *
4  * Copyright (C) 2005 Texas Instruments, Inc.
5  * Copyright (C) 2006-2008 Nokia Corporation
6  *
7  * Written by:
8  * Richard Woodruff <r-woodruff2@ti.com>
9  * Tony Lindgren
10  * Juha Yrjola
11  * Amit Kucheria <amit.kucheria@nokia.com>
12  * Igor Stoppa <igor.stoppa@nokia.com>
13  *
14  * Based on pm.c for omap1
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk-provider.h>
29 #include <linux/irq.h>
30 #include <linux/time.h>
31 #include <linux/gpio.h>
32 #include <linux/platform_data/gpio-omap.h>
33
34 #include <asm/fncpy.h>
35
36 #include <asm/mach/time.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach-types.h>
39 #include <asm/system_misc.h>
40
41 #include <linux/omap-dma.h>
42
43 #include "soc.h"
44 #include "common.h"
45 #include "clock.h"
46 #include "prm2xxx.h"
47 #include "prm-regbits-24xx.h"
48 #include "cm2xxx.h"
49 #include "cm-regbits-24xx.h"
50 #include "sdrc.h"
51 #include "sram.h"
52 #include "pm.h"
53 #include "control.h"
54 #include "powerdomain.h"
55 #include "clockdomain.h"
56
57 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
58                                   void __iomem *sdrc_power);
59
60 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
61 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
62
63 static struct clk *osc_ck, *emul_ck;
64
65 static int omap2_fclks_active(void)
66 {
67         u32 f1, f2;
68
69         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
70         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
71
72         return (f1 | f2) ? 1 : 0;
73 }
74
75 static int omap2_enter_full_retention(void)
76 {
77         u32 l;
78
79         /* There is 1 reference hold for all children of the oscillator
80          * clock, the following will remove it. If no one else uses the
81          * oscillator itself it will be disabled if/when we enter retention
82          * mode.
83          */
84         clk_disable(osc_ck);
85
86         /* Clear old wake-up events */
87         /* REVISIT: These write to reserved bits? */
88         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
89         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
90         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
91
92         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
93         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
94
95         /* Workaround to kill USB */
96         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
97         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
98
99         omap2_gpio_prepare_for_idle(0);
100
101         /* One last check for pending IRQs to avoid extra latency due
102          * to sleeping unnecessarily. */
103         if (omap_irq_pending())
104                 goto no_sleep;
105
106         /* Jump to SRAM suspend code */
107         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
108                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
109                            OMAP_SDRC_REGADDR(SDRC_POWER));
110
111 no_sleep:
112         omap2_gpio_resume_after_idle();
113
114         clk_enable(osc_ck);
115
116         /* clear CORE wake-up events */
117         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
118         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
119
120         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
121         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
122
123         /* MPU domain wake events */
124         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
125         if (l & 0x01)
126                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
127                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
128         if (l & 0x20)
129                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
130                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
131
132         /* Mask future PRCM-to-MPU interrupts */
133         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
134
135         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
136         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
137
138         return 0;
139 }
140
141 static int sti_console_enabled;
142
143 static int omap2_allow_mpu_retention(void)
144 {
145         u32 l;
146
147         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
148         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
149         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
150                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
151                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
152                 return 0;
153         /* Check for UART3. */
154         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
155         if (l & OMAP24XX_EN_UART3_MASK)
156                 return 0;
157         if (sti_console_enabled)
158                 return 0;
159
160         return 1;
161 }
162
163 static void omap2_enter_mpu_retention(void)
164 {
165         const int zero = 0;
166
167         /* The peripherals seem not to be able to wake up the MPU when
168          * it is in retention mode. */
169         if (omap2_allow_mpu_retention()) {
170                 /* REVISIT: These write to reserved bits? */
171                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
172                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
173                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
174
175                 /* Try to enter MPU retention */
176                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
177
178         } else {
179                 /* Block MPU retention */
180                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
181         }
182
183         /* WFI */
184         asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
185
186         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
187 }
188
189 static int omap2_can_sleep(void)
190 {
191         if (omap2_fclks_active())
192                 return 0;
193         if (__clk_is_enabled(osc_ck))
194                 return 0;
195         if (omap_dma_running())
196                 return 0;
197
198         return 1;
199 }
200
201 static void omap2_pm_idle(void)
202 {
203         local_fiq_disable();
204
205         if (!omap2_can_sleep()) {
206                 if (omap_irq_pending())
207                         goto out;
208                 omap2_enter_mpu_retention();
209                 goto out;
210         }
211
212         if (omap_irq_pending())
213                 goto out;
214
215         omap2_enter_full_retention();
216
217 out:
218         local_fiq_enable();
219 }
220
221 static void __init prcm_setup_regs(void)
222 {
223         int i, num_mem_banks;
224         struct powerdomain *pwrdm;
225
226         /*
227          * Enable autoidle
228          * XXX This should be handled by hwmod code or PRCM init code
229          */
230         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
231                           OMAP2_PRCM_SYSCONFIG_OFFSET);
232
233         /*
234          * Set CORE powerdomain memory banks to retain their contents
235          * during RETENTION
236          */
237         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
238         for (i = 0; i < num_mem_banks; i++)
239                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
240
241         pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
242
243         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
244
245         /* Force-power down DSP, GFX powerdomains */
246
247         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
248         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
249
250         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
251         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
252
253         /* Enable hardware-supervised idle for all clkdms */
254         clkdm_for_each(omap_pm_clkdms_setup, NULL);
255         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
256
257 #ifdef CONFIG_SUSPEND
258         omap_pm_suspend = omap2_enter_full_retention;
259 #endif
260
261         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
262          * stabilisation */
263         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
264                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
265
266         /* Configure automatic voltage transition */
267         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
268                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
269         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
270                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
271                                 OMAP24XX_MEMRETCTRL_MASK |
272                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
273                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
274                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
275
276         /* Enable wake-up events */
277         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
278                                 WKUP_MOD, PM_WKEN);
279 }
280
281 int __init omap2_pm_init(void)
282 {
283         u32 l;
284
285         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
286         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
287         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
288
289         /* Look up important powerdomains */
290
291         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
292         if (!mpu_pwrdm)
293                 pr_err("PM: mpu_pwrdm not found\n");
294
295         core_pwrdm = pwrdm_lookup("core_pwrdm");
296         if (!core_pwrdm)
297                 pr_err("PM: core_pwrdm not found\n");
298
299         /* Look up important clockdomains */
300
301         mpu_clkdm = clkdm_lookup("mpu_clkdm");
302         if (!mpu_clkdm)
303                 pr_err("PM: mpu_clkdm not found\n");
304
305         wkup_clkdm = clkdm_lookup("wkup_clkdm");
306         if (!wkup_clkdm)
307                 pr_err("PM: wkup_clkdm not found\n");
308
309         dsp_clkdm = clkdm_lookup("dsp_clkdm");
310         if (!dsp_clkdm)
311                 pr_err("PM: dsp_clkdm not found\n");
312
313         gfx_clkdm = clkdm_lookup("gfx_clkdm");
314         if (!gfx_clkdm)
315                 pr_err("PM: gfx_clkdm not found\n");
316
317
318         osc_ck = clk_get(NULL, "osc_ck");
319         if (IS_ERR(osc_ck)) {
320                 printk(KERN_ERR "could not get osc_ck\n");
321                 return -ENODEV;
322         }
323
324         if (cpu_is_omap242x()) {
325                 emul_ck = clk_get(NULL, "emul_ck");
326                 if (IS_ERR(emul_ck)) {
327                         printk(KERN_ERR "could not get emul_ck\n");
328                         clk_put(osc_ck);
329                         return -ENODEV;
330                 }
331         }
332
333         prcm_setup_regs();
334
335         /*
336          * We copy the assembler sleep/wakeup routines to SRAM.
337          * These routines need to be in SRAM as that's the only
338          * memory the MPU can see when it wakes up after the entire
339          * chip enters idle.
340          */
341         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
342                                             omap24xx_cpu_suspend_sz);
343
344         arm_pm_idle = omap2_pm_idle;
345
346         return 0;
347 }