Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33 #include <linux/console.h>
  34
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <mach/irqs.h>
  40 #include <plat/clock.h>
  41 #include <plat/sram.h>
  42 #include <plat/dma.h>
  43 #include <plat/board.h>
  44
  45 #include "common.h"
  46 #include "prm2xxx_3xxx.h"
  47 #include "prm-regbits-24xx.h"
  48 #include "cm2xxx_3xxx.h"
  49 #include "cm-regbits-24xx.h"
  50 #include "sdrc.h"
  51 #include "pm.h"
  52 #include "control.h"
  53
  54 #include "powerdomain.h"
  55 #include "clockdomain.h"
  56
  57 #ifdef CONFIG_SUSPEND
  58 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  59 static inline bool is_suspending(void)
  60 {
  61         return (suspend_state != PM_SUSPEND_ON);
  62 }
  63 #else
  64 static inline bool is_suspending(void)
  65 {
  66         return false;
  67 }
  68 #endif
  69
  70 static void (*omap2_sram_idle)(void);
  71 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  72                                   void __iomem *sdrc_power);
  73
  74 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  75 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  76
  77 static struct clk *osc_ck, *emul_ck;
  78
  79 static int omap2_fclks_active(void)
  80 {
  81         u32 f1, f2;
  82
  83         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  84         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  85
  86         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
  87         f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
  88         f2 &= ~OMAP24XX_EN_UART3_MASK;
  89
  90         if (f1 | f2)
  91                 return 1;
  92         return 0;
  93 }
  94
  95 static void omap2_enter_full_retention(void)
  96 {
  97         u32 l;
  98
  99         /* There is 1 reference hold for all children of the oscillator
 100          * clock, the following will remove it. If no one else uses the
 101          * oscillator itself it will be disabled if/when we enter retention
 102          * mode.
 103          */
 104         clk_disable(osc_ck);
 105
 106         /* Clear old wake-up events */
 107         /* REVISIT: These write to reserved bits? */
 108         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 109         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 110         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 111
 112         /*
 113          * Set MPU powerdomain's next power state to RETENTION;
 114          * preserve logic state during retention
 115          */
 116         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 117         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 118
 119         /* Workaround to kill USB */
 120         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 121         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 122
 123         omap2_gpio_prepare_for_idle(0);
 124
 125         /* One last check for pending IRQs to avoid extra latency due
 126          * to sleeping unnecessarily. */
 127         if (omap_irq_pending())
 128                 goto no_sleep;
 129
 130         /* Block console output in case it is on one of the OMAP UARTs */
 131         if (!is_suspending())
 132                 if (!console_trylock())
 133                         goto no_sleep;
 134
 135         omap_uart_prepare_idle(0);
 136         omap_uart_prepare_idle(1);
 137         omap_uart_prepare_idle(2);
 138
 139         /* Jump to SRAM suspend code */
 140         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 141                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 142                            OMAP_SDRC_REGADDR(SDRC_POWER));
 143
 144         omap_uart_resume_idle(2);
 145         omap_uart_resume_idle(1);
 146         omap_uart_resume_idle(0);
 147
 148         if (!is_suspending())
 149                 console_unlock();
 150
 151 no_sleep:
 152         omap2_gpio_resume_after_idle();
 153
 154         clk_enable(osc_ck);
 155
 156         /* clear CORE wake-up events */
 157         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 158         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 159
 160         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 161         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 162
 163         /* MPU domain wake events */
 164         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 165         if (l & 0x01)
 166                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 167                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 168         if (l & 0x20)
 169                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 170                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 171
 172         /* Mask future PRCM-to-MPU interrupts */
 173         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 174 }
 175
 176 static int omap2_i2c_active(void)
 177 {
 178         u32 l;
 179
 180         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 181         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 182 }
 183
 184 static int sti_console_enabled;
 185
 186 static int omap2_allow_mpu_retention(void)
 187 {
 188         u32 l;
 189
 190         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 191         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 192         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 193                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 194                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 195                 return 0;
 196         /* Check for UART3. */
 197         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 198         if (l & OMAP24XX_EN_UART3_MASK)
 199                 return 0;
 200         if (sti_console_enabled)
 201                 return 0;
 202
 203         return 1;
 204 }
 205
 206 static void omap2_enter_mpu_retention(void)
 207 {
 208         int only_idle = 0;
 209
 210         /* Putting MPU into the WFI state while a transfer is active
 211          * seems to cause the I2C block to timeout. Why? Good question. */
 212         if (omap2_i2c_active())
 213                 return;
 214
 215         /* The peripherals seem not to be able to wake up the MPU when
 216          * it is in retention mode. */
 217         if (omap2_allow_mpu_retention()) {
 218                 /* REVISIT: These write to reserved bits? */
 219                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 220                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 221                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 222
 223                 /* Try to enter MPU retention */
 224                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 225                                   OMAP_LOGICRETSTATE_MASK,
 226                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 227         } else {
 228                 /* Block MPU retention */
 229
 230                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 231                                                  OMAP2_PM_PWSTCTRL);
 232                 only_idle = 1;
 233         }
 234
 235         omap2_sram_idle();
 236 }
 237
 238 static int omap2_can_sleep(void)
 239 {
 240         if (omap2_fclks_active())
 241                 return 0;
 242         if (!omap_uart_can_sleep())
 243                 return 0;
 244         if (osc_ck->usecount > 1)
 245                 return 0;
 246         if (omap_dma_running())
 247                 return 0;
 248
 249         return 1;
 250 }
 251
 252 static void omap2_pm_idle(void)
 253 {
 254         local_irq_disable();
 255         local_fiq_disable();
 256
 257         if (!omap2_can_sleep()) {
 258                 if (omap_irq_pending())
 259                         goto out;
 260                 omap2_enter_mpu_retention();
 261                 goto out;
 262         }
 263
 264         if (omap_irq_pending())
 265                 goto out;
 266
 267         omap2_enter_full_retention();
 268
 269 out:
 270         local_fiq_enable();
 271         local_irq_enable();
 272 }
 273
 274 #ifdef CONFIG_SUSPEND
 275 static int omap2_pm_begin(suspend_state_t state)
 276 {
 277         disable_hlt();
 278         suspend_state = state;
 279         return 0;
 280 }
 281
 282 static int omap2_pm_suspend(void)
 283 {
 284         u32 wken_wkup, mir1;
 285
 286         wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 287         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
 288         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 289
 290         /* Mask GPT1 */
 291         mir1 = omap_readl(0x480fe0a4);
 292         omap_writel(1 << 5, 0x480fe0ac);
 293
 294         omap_uart_prepare_suspend();
 295         omap2_enter_full_retention();
 296
 297         omap_writel(mir1, 0x480fe0a4);
 298         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 299
 300         return 0;
 301 }
 302
 303 static int omap2_pm_enter(suspend_state_t state)
 304 {
 305         int ret = 0;
 306
 307         switch (state) {
 308         case PM_SUSPEND_STANDBY:
 309         case PM_SUSPEND_MEM:
 310                 ret = omap2_pm_suspend();
 311                 break;
 312         default:
 313                 ret = -EINVAL;
 314         }
 315
 316         return ret;
 317 }
 318
 319 static void omap2_pm_end(void)
 320 {
 321         suspend_state = PM_SUSPEND_ON;
 322         enable_hlt();
 323 }
 324
 325 static const struct platform_suspend_ops omap_pm_ops = {
 326         .begin          = omap2_pm_begin,
 327         .enter          = omap2_pm_enter,
 328         .end            = omap2_pm_end,
 329         .valid          = suspend_valid_only_mem,
 330 };
 331 #else
 332 static const struct platform_suspend_ops __initdata omap_pm_ops;
 333 #endif /* CONFIG_SUSPEND */
 334
 335 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 336 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 337 {
 338         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 339                 clkdm_allow_idle(clkdm);
 340         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 341                  atomic_read(&clkdm->usecount) == 0)
 342                 clkdm_sleep(clkdm);
 343         return 0;
 344 }
 345
 346 static void __init prcm_setup_regs(void)
 347 {
 348         int i, num_mem_banks;
 349         struct powerdomain *pwrdm;
 350
 351         /*
 352          * Enable autoidle
 353          * XXX This should be handled by hwmod code or PRCM init code
 354          */
 355         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 356                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 357
 358         /*
 359          * Set CORE powerdomain memory banks to retain their contents
 360          * during RETENTION
 361          */
 362         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 363         for (i = 0; i < num_mem_banks; i++)
 364                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 365
 366         /* Set CORE powerdomain's next power state to RETENTION */
 367         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 368
 369         /*
 370          * Set MPU powerdomain's next power state to RETENTION;
 371          * preserve logic state during retention
 372          */
 373         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 374         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 375
 376         /* Force-power down DSP, GFX powerdomains */
 377
 378         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 379         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 380         clkdm_sleep(dsp_clkdm);
 381
 382         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 383         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 384         clkdm_sleep(gfx_clkdm);
 385
 386         /* Enable hardware-supervised idle for all clkdms */
 387         clkdm_for_each(clkdms_setup, NULL);
 388         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 389
 390         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 391          * stabilisation */
 392         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 393                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 394
 395         /* Configure automatic voltage transition */
 396         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 397                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 398         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 399                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 400                                 OMAP24XX_MEMRETCTRL_MASK |
 401                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 402                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 403                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 404
 405         /* Enable wake-up events */
 406         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 407                                 WKUP_MOD, PM_WKEN);
 408 }
 409
 410 static int __init omap2_pm_init(void)
 411 {
 412         u32 l;
 413
 414         if (!cpu_is_omap24xx())
 415                 return -ENODEV;
 416
 417         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 418         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 419         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 420
 421         /* Look up important powerdomains */
 422
 423         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 424         if (!mpu_pwrdm)
 425                 pr_err("PM: mpu_pwrdm not found\n");
 426
 427         core_pwrdm = pwrdm_lookup("core_pwrdm");
 428         if (!core_pwrdm)
 429                 pr_err("PM: core_pwrdm not found\n");
 430
 431         /* Look up important clockdomains */
 432
 433         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 434         if (!mpu_clkdm)
 435                 pr_err("PM: mpu_clkdm not found\n");
 436
 437         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 438         if (!wkup_clkdm)
 439                 pr_err("PM: wkup_clkdm not found\n");
 440
 441         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 442         if (!dsp_clkdm)
 443                 pr_err("PM: dsp_clkdm not found\n");
 444
 445         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 446         if (!gfx_clkdm)
 447                 pr_err("PM: gfx_clkdm not found\n");
 448
 449
 450         osc_ck = clk_get(NULL, "osc_ck");
 451         if (IS_ERR(osc_ck)) {
 452                 printk(KERN_ERR "could not get osc_ck\n");
 453                 return -ENODEV;
 454         }
 455
 456         if (cpu_is_omap242x()) {
 457                 emul_ck = clk_get(NULL, "emul_ck");
 458                 if (IS_ERR(emul_ck)) {
 459                         printk(KERN_ERR "could not get emul_ck\n");
 460                         clk_put(osc_ck);
 461                         return -ENODEV;
 462                 }
 463         }
 464
 465         prcm_setup_regs();
 466
 467         /* Hack to prevent MPU retention when STI console is enabled. */
 468         {
 469                 const struct omap_sti_console_config *sti;
 470
 471                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 472                                       struct omap_sti_console_config);
 473                 if (sti != NULL && sti->enable)
 474                         sti_console_enabled = 1;
 475         }
 476
 477         /*
 478          * We copy the assembler sleep/wakeup routines to SRAM.
 479          * These routines need to be in SRAM as that's the only
 480          * memory the MPU can see when it wakes up.
 481          */
 482         if (cpu_is_omap24xx()) {
 483                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 484                                                  omap24xx_idle_loop_suspend_sz);
 485
 486                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 487                                                     omap24xx_cpu_suspend_sz);
 488         }
 489
 490         suspend_set_ops(&omap_pm_ops);
 491         pm_idle = omap2_pm_idle;
 492
 493         return 0;
 494 }
 495
 496 late_initcall(omap2_pm_init);