Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/system_misc.h>
  38
  39 #include <mach/irqs.h>
  40 #include <plat/clock.h>
  41 #include <plat/sram.h>
  42 #include <plat/dma.h>
  43 #include <plat/board.h>
  44
  45 #include "common.h"
  46 #include "prm2xxx_3xxx.h"
  47 #include "prm-regbits-24xx.h"
  48 #include "cm2xxx_3xxx.h"
  49 #include "cm-regbits-24xx.h"
  50 #include "sdrc.h"
  51 #include "pm.h"
  52 #include "control.h"
  53
  54 #include "powerdomain.h"
  55 #include "clockdomain.h"
  56
  57 #ifdef CONFIG_SUSPEND
  58 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  59 static inline bool is_suspending(void)
  60 {
  61         return (suspend_state != PM_SUSPEND_ON);
  62 }
  63 #else
  64 static inline bool is_suspending(void)
  65 {
  66         return false;
  67 }
  68 #endif
  69
  70 static void (*omap2_sram_idle)(void);
  71 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  72                                   void __iomem *sdrc_power);
  73
  74 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  75 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  76
  77 static struct clk *osc_ck, *emul_ck;
  78
  79 static int omap2_fclks_active(void)
  80 {
  81         u32 f1, f2;
  82
  83         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  84         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  85
  86         return (f1 | f2) ? 1 : 0;
  87 }
  88
  89 static void omap2_enter_full_retention(void)
  90 {
  91         u32 l;
  92
  93         /* There is 1 reference hold for all children of the oscillator
  94          * clock, the following will remove it. If no one else uses the
  95          * oscillator itself it will be disabled if/when we enter retention
  96          * mode.
  97          */
  98         clk_disable(osc_ck);
  99
 100         /* Clear old wake-up events */
 101         /* REVISIT: These write to reserved bits? */
 102         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 103         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 104         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 105
 106         /*
 107          * Set MPU powerdomain's next power state to RETENTION;
 108          * preserve logic state during retention
 109          */
 110         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 111         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 112
 113         /* Workaround to kill USB */
 114         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 115         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 116
 117         omap2_gpio_prepare_for_idle(0);
 118
 119         /* One last check for pending IRQs to avoid extra latency due
 120          * to sleeping unnecessarily. */
 121         if (omap_irq_pending())
 122                 goto no_sleep;
 123
 124         /* Jump to SRAM suspend code */
 125         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 126                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 127                            OMAP_SDRC_REGADDR(SDRC_POWER));
 128
 129 no_sleep:
 130         omap2_gpio_resume_after_idle();
 131
 132         clk_enable(osc_ck);
 133
 134         /* clear CORE wake-up events */
 135         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 136         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 137
 138         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 139         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 140
 141         /* MPU domain wake events */
 142         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 143         if (l & 0x01)
 144                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 145                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 146         if (l & 0x20)
 147                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 148                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 149
 150         /* Mask future PRCM-to-MPU interrupts */
 151         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 152 }
 153
 154 static int omap2_i2c_active(void)
 155 {
 156         u32 l;
 157
 158         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 159         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 160 }
 161
 162 static int sti_console_enabled;
 163
 164 static int omap2_allow_mpu_retention(void)
 165 {
 166         u32 l;
 167
 168         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 169         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 170         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 171                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 172                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 173                 return 0;
 174         /* Check for UART3. */
 175         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 176         if (l & OMAP24XX_EN_UART3_MASK)
 177                 return 0;
 178         if (sti_console_enabled)
 179                 return 0;
 180
 181         return 1;
 182 }
 183
 184 static void omap2_enter_mpu_retention(void)
 185 {
 186         int only_idle = 0;
 187
 188         /* Putting MPU into the WFI state while a transfer is active
 189          * seems to cause the I2C block to timeout. Why? Good question. */
 190         if (omap2_i2c_active())
 191                 return;
 192
 193         /* The peripherals seem not to be able to wake up the MPU when
 194          * it is in retention mode. */
 195         if (omap2_allow_mpu_retention()) {
 196                 /* REVISIT: These write to reserved bits? */
 197                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 198                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 199                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 200
 201                 /* Try to enter MPU retention */
 202                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 203                                   OMAP_LOGICRETSTATE_MASK,
 204                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 205         } else {
 206                 /* Block MPU retention */
 207
 208                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 209                                                  OMAP2_PM_PWSTCTRL);
 210                 only_idle = 1;
 211         }
 212
 213         omap2_sram_idle();
 214 }
 215
 216 static int omap2_can_sleep(void)
 217 {
 218         if (omap2_fclks_active())
 219                 return 0;
 220         if (osc_ck->usecount > 1)
 221                 return 0;
 222         if (omap_dma_running())
 223                 return 0;
 224
 225         return 1;
 226 }
 227
 228 static void omap2_pm_idle(void)
 229 {
 230         local_irq_disable();
 231         local_fiq_disable();
 232
 233         if (!omap2_can_sleep()) {
 234                 if (omap_irq_pending())
 235                         goto out;
 236                 omap2_enter_mpu_retention();
 237                 goto out;
 238         }
 239
 240         if (omap_irq_pending())
 241                 goto out;
 242
 243         omap2_enter_full_retention();
 244
 245 out:
 246         local_fiq_enable();
 247         local_irq_enable();
 248 }
 249
 250 #ifdef CONFIG_SUSPEND
 251 static int omap2_pm_begin(suspend_state_t state)
 252 {
 253         disable_hlt();
 254         suspend_state = state;
 255         return 0;
 256 }
 257
 258 static int omap2_pm_suspend(void)
 259 {
 260         u32 wken_wkup, mir1;
 261
 262         wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 263         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
 264         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 265
 266         /* Mask GPT1 */
 267         mir1 = omap_readl(0x480fe0a4);
 268         omap_writel(1 << 5, 0x480fe0ac);
 269
 270         omap2_enter_full_retention();
 271
 272         omap_writel(mir1, 0x480fe0a4);
 273         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 274
 275         return 0;
 276 }
 277
 278 static int omap2_pm_enter(suspend_state_t state)
 279 {
 280         int ret = 0;
 281
 282         switch (state) {
 283         case PM_SUSPEND_STANDBY:
 284         case PM_SUSPEND_MEM:
 285                 ret = omap2_pm_suspend();
 286                 break;
 287         default:
 288                 ret = -EINVAL;
 289         }
 290
 291         return ret;
 292 }
 293
 294 static void omap2_pm_end(void)
 295 {
 296         suspend_state = PM_SUSPEND_ON;
 297         enable_hlt();
 298 }
 299
 300 static const struct platform_suspend_ops omap_pm_ops = {
 301         .begin          = omap2_pm_begin,
 302         .enter          = omap2_pm_enter,
 303         .end            = omap2_pm_end,
 304         .valid          = suspend_valid_only_mem,
 305 };
 306 #else
 307 static const struct platform_suspend_ops __initdata omap_pm_ops;
 308 #endif /* CONFIG_SUSPEND */
 309
 310 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 311 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 312 {
 313         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 314                 clkdm_allow_idle(clkdm);
 315         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 316                  atomic_read(&clkdm->usecount) == 0)
 317                 clkdm_sleep(clkdm);
 318         return 0;
 319 }
 320
 321 static void __init prcm_setup_regs(void)
 322 {
 323         int i, num_mem_banks;
 324         struct powerdomain *pwrdm;
 325
 326         /*
 327          * Enable autoidle
 328          * XXX This should be handled by hwmod code or PRCM init code
 329          */
 330         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 331                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 332
 333         /*
 334          * Set CORE powerdomain memory banks to retain their contents
 335          * during RETENTION
 336          */
 337         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 338         for (i = 0; i < num_mem_banks; i++)
 339                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 340
 341         /* Set CORE powerdomain's next power state to RETENTION */
 342         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 343
 344         /*
 345          * Set MPU powerdomain's next power state to RETENTION;
 346          * preserve logic state during retention
 347          */
 348         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 349         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 350
 351         /* Force-power down DSP, GFX powerdomains */
 352
 353         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 354         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 355         clkdm_sleep(dsp_clkdm);
 356
 357         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 358         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 359         clkdm_sleep(gfx_clkdm);
 360
 361         /* Enable hardware-supervised idle for all clkdms */
 362         clkdm_for_each(clkdms_setup, NULL);
 363         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 364
 365         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 366          * stabilisation */
 367         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 368                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 369
 370         /* Configure automatic voltage transition */
 371         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 372                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 373         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 374                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 375                                 OMAP24XX_MEMRETCTRL_MASK |
 376                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 377                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 378                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 379
 380         /* Enable wake-up events */
 381         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 382                                 WKUP_MOD, PM_WKEN);
 383 }
 384
 385 static int __init omap2_pm_init(void)
 386 {
 387         u32 l;
 388
 389         if (!cpu_is_omap24xx())
 390                 return -ENODEV;
 391
 392         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 393         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 394         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 395
 396         /* Look up important powerdomains */
 397
 398         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 399         if (!mpu_pwrdm)
 400                 pr_err("PM: mpu_pwrdm not found\n");
 401
 402         core_pwrdm = pwrdm_lookup("core_pwrdm");
 403         if (!core_pwrdm)
 404                 pr_err("PM: core_pwrdm not found\n");
 405
 406         /* Look up important clockdomains */
 407
 408         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 409         if (!mpu_clkdm)
 410                 pr_err("PM: mpu_clkdm not found\n");
 411
 412         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 413         if (!wkup_clkdm)
 414                 pr_err("PM: wkup_clkdm not found\n");
 415
 416         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 417         if (!dsp_clkdm)
 418                 pr_err("PM: dsp_clkdm not found\n");
 419
 420         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 421         if (!gfx_clkdm)
 422                 pr_err("PM: gfx_clkdm not found\n");
 423
 424
 425         osc_ck = clk_get(NULL, "osc_ck");
 426         if (IS_ERR(osc_ck)) {
 427                 printk(KERN_ERR "could not get osc_ck\n");
 428                 return -ENODEV;
 429         }
 430
 431         if (cpu_is_omap242x()) {
 432                 emul_ck = clk_get(NULL, "emul_ck");
 433                 if (IS_ERR(emul_ck)) {
 434                         printk(KERN_ERR "could not get emul_ck\n");
 435                         clk_put(osc_ck);
 436                         return -ENODEV;
 437                 }
 438         }
 439
 440         prcm_setup_regs();
 441
 442         /* Hack to prevent MPU retention when STI console is enabled. */
 443         {
 444                 const struct omap_sti_console_config *sti;
 445
 446                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 447                                       struct omap_sti_console_config);
 448                 if (sti != NULL && sti->enable)
 449                         sti_console_enabled = 1;
 450         }
 451
 452         /*
 453          * We copy the assembler sleep/wakeup routines to SRAM.
 454          * These routines need to be in SRAM as that's the only
 455          * memory the MPU can see when it wakes up.
 456          */
 457         if (cpu_is_omap24xx()) {
 458                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 459                                                  omap24xx_idle_loop_suspend_sz);
 460
 461                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 462                                                     omap24xx_cpu_suspend_sz);
 463         }
 464
 465         suspend_set_ops(&omap_pm_ops);
 466         pm_idle = omap2_pm_idle;
 467
 468         return 0;
 469 }
 470
 471 late_initcall(omap2_pm_init);