Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/irq.h>
  30 #include <linux/time.h>
  31 #include <linux/gpio.h>
  32
  33 #include <asm/mach/time.h>
  34 #include <asm/mach/irq.h>
  35 #include <asm/mach-types.h>
  36
  37 #include <plat/clock.h>
  38 #include <plat/sram.h>
  39 #include <plat/dma.h>
  40 #include <plat/board.h>
  41
  42 #include <mach/irqs.h>
  43
  44 #include "common.h"
  45 #include "prm2xxx_3xxx.h"
  46 #include "prm-regbits-24xx.h"
  47 #include "cm2xxx_3xxx.h"
  48 #include "cm-regbits-24xx.h"
  49 #include "sdrc.h"
  50 #include "pm.h"
  51 #include "control.h"
  52 #include "powerdomain.h"
  53 #include "clockdomain.h"
  54
  55 static void (*omap2_sram_idle)(void);
  56 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  57                                   void __iomem *sdrc_power);
  58
  59 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  60 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  61
  62 static struct clk *osc_ck, *emul_ck;
  63
  64 static int omap2_fclks_active(void)
  65 {
  66         u32 f1, f2;
  67
  68         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  69         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  70
  71         return (f1 | f2) ? 1 : 0;
  72 }
  73
  74 static int omap2_enter_full_retention(void)
  75 {
  76         u32 l;
  77
  78         /* There is 1 reference hold for all children of the oscillator
  79          * clock, the following will remove it. If no one else uses the
  80          * oscillator itself it will be disabled if/when we enter retention
  81          * mode.
  82          */
  83         clk_disable(osc_ck);
  84
  85         /* Clear old wake-up events */
  86         /* REVISIT: These write to reserved bits? */
  87         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  88         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  89         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  90
  91         /*
  92          * Set MPU powerdomain's next power state to RETENTION;
  93          * preserve logic state during retention
  94          */
  95         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
  96         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
  97
  98         /* Workaround to kill USB */
  99         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 100         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 101
 102         omap2_gpio_prepare_for_idle(0);
 103
 104         /* One last check for pending IRQs to avoid extra latency due
 105          * to sleeping unnecessarily. */
 106         if (omap_irq_pending())
 107                 goto no_sleep;
 108
 109         /* Jump to SRAM suspend code */
 110         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 111                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 112                            OMAP_SDRC_REGADDR(SDRC_POWER));
 113
 114 no_sleep:
 115         omap2_gpio_resume_after_idle();
 116
 117         clk_enable(osc_ck);
 118
 119         /* clear CORE wake-up events */
 120         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 121         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 122
 123         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 124         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 125
 126         /* MPU domain wake events */
 127         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 128         if (l & 0x01)
 129                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 130                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 131         if (l & 0x20)
 132                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 133                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 134
 135         /* Mask future PRCM-to-MPU interrupts */
 136         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 137
 138         return 0;
 139 }
 140
 141 static int omap2_i2c_active(void)
 142 {
 143         u32 l;
 144
 145         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 146         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 147 }
 148
 149 static int sti_console_enabled;
 150
 151 static int omap2_allow_mpu_retention(void)
 152 {
 153         u32 l;
 154
 155         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 156         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 157         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 158                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 159                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 160                 return 0;
 161         /* Check for UART3. */
 162         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 163         if (l & OMAP24XX_EN_UART3_MASK)
 164                 return 0;
 165         if (sti_console_enabled)
 166                 return 0;
 167
 168         return 1;
 169 }
 170
 171 static void omap2_enter_mpu_retention(void)
 172 {
 173         int only_idle = 0;
 174
 175         /* Putting MPU into the WFI state while a transfer is active
 176          * seems to cause the I2C block to timeout. Why? Good question. */
 177         if (omap2_i2c_active())
 178                 return;
 179
 180         /* The peripherals seem not to be able to wake up the MPU when
 181          * it is in retention mode. */
 182         if (omap2_allow_mpu_retention()) {
 183                 /* REVISIT: These write to reserved bits? */
 184                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 185                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 186                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 187
 188                 /* Try to enter MPU retention */
 189                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 190                                   OMAP_LOGICRETSTATE_MASK,
 191                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 192         } else {
 193                 /* Block MPU retention */
 194
 195                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 196                                                  OMAP2_PM_PWSTCTRL);
 197                 only_idle = 1;
 198         }
 199
 200         omap2_sram_idle();
 201 }
 202
 203 static int omap2_can_sleep(void)
 204 {
 205         if (omap2_fclks_active())
 206                 return 0;
 207         if (osc_ck->usecount > 1)
 208                 return 0;
 209         if (omap_dma_running())
 210                 return 0;
 211
 212         return 1;
 213 }
 214
 215 static void omap2_pm_idle(void)
 216 {
 217         local_fiq_disable();
 218
 219         if (!omap2_can_sleep()) {
 220                 if (omap_irq_pending())
 221                         goto out;
 222                 omap2_enter_mpu_retention();
 223                 goto out;
 224         }
 225
 226         if (omap_irq_pending())
 227                 goto out;
 228
 229         omap2_enter_full_retention();
 230
 231 out:
 232         local_fiq_enable();
 233 }
 234
 235 static void __init prcm_setup_regs(void)
 236 {
 237         int i, num_mem_banks;
 238         struct powerdomain *pwrdm;
 239
 240         /*
 241          * Enable autoidle
 242          * XXX This should be handled by hwmod code or PRCM init code
 243          */
 244         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 245                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 246
 247         /*
 248          * Set CORE powerdomain memory banks to retain their contents
 249          * during RETENTION
 250          */
 251         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 252         for (i = 0; i < num_mem_banks; i++)
 253                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 254
 255         /* Set CORE powerdomain's next power state to RETENTION */
 256         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 257
 258         /*
 259          * Set MPU powerdomain's next power state to RETENTION;
 260          * preserve logic state during retention
 261          */
 262         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 263         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 264
 265         /* Force-power down DSP, GFX powerdomains */
 266
 267         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 268         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 269         clkdm_sleep(dsp_clkdm);
 270
 271         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 272         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 273         clkdm_sleep(gfx_clkdm);
 274
 275         /* Enable hardware-supervised idle for all clkdms */
 276         clkdm_for_each(omap_pm_clkdms_setup, NULL);
 277         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 278
 279 #ifdef CONFIG_SUSPEND
 280         omap_pm_suspend = omap2_enter_full_retention;
 281 #endif
 282
 283         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 284          * stabilisation */
 285         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 286                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 287
 288         /* Configure automatic voltage transition */
 289         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 290                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 291         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 292                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 293                                 OMAP24XX_MEMRETCTRL_MASK |
 294                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 295                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 296                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 297
 298         /* Enable wake-up events */
 299         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 300                                 WKUP_MOD, PM_WKEN);
 301 }
 302
 303 static int __init omap2_pm_init(void)
 304 {
 305         u32 l;
 306
 307         if (!cpu_is_omap24xx())
 308                 return -ENODEV;
 309
 310         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 311         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 312         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 313
 314         /* Look up important powerdomains */
 315
 316         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 317         if (!mpu_pwrdm)
 318                 pr_err("PM: mpu_pwrdm not found\n");
 319
 320         core_pwrdm = pwrdm_lookup("core_pwrdm");
 321         if (!core_pwrdm)
 322                 pr_err("PM: core_pwrdm not found\n");
 323
 324         /* Look up important clockdomains */
 325
 326         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 327         if (!mpu_clkdm)
 328                 pr_err("PM: mpu_clkdm not found\n");
 329
 330         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 331         if (!wkup_clkdm)
 332                 pr_err("PM: wkup_clkdm not found\n");
 333
 334         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 335         if (!dsp_clkdm)
 336                 pr_err("PM: dsp_clkdm not found\n");
 337
 338         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 339         if (!gfx_clkdm)
 340                 pr_err("PM: gfx_clkdm not found\n");
 341
 342
 343         osc_ck = clk_get(NULL, "osc_ck");
 344         if (IS_ERR(osc_ck)) {
 345                 printk(KERN_ERR "could not get osc_ck\n");
 346                 return -ENODEV;
 347         }
 348
 349         if (cpu_is_omap242x()) {
 350                 emul_ck = clk_get(NULL, "emul_ck");
 351                 if (IS_ERR(emul_ck)) {
 352                         printk(KERN_ERR "could not get emul_ck\n");
 353                         clk_put(osc_ck);
 354                         return -ENODEV;
 355                 }
 356         }
 357
 358         prcm_setup_regs();
 359
 360         /* Hack to prevent MPU retention when STI console is enabled. */
 361         {
 362                 const struct omap_sti_console_config *sti;
 363
 364                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 365                                       struct omap_sti_console_config);
 366                 if (sti != NULL && sti->enable)
 367                         sti_console_enabled = 1;
 368         }
 369
 370         /*
 371          * We copy the assembler sleep/wakeup routines to SRAM.
 372          * These routines need to be in SRAM as that's the only
 373          * memory the MPU can see when it wakes up.
 374          */
 375         if (cpu_is_omap24xx()) {
 376                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 377                                                  omap24xx_idle_loop_suspend_sz);
 378
 379                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 380                                                     omap24xx_cpu_suspend_sz);
 381         }
 382
 383         arm_pm_idle = omap2_pm_idle;
 384
 385         return 0;
 386 }
 387
 388 late_initcall(omap2_pm_init);