Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_twl.c

   1 /**
   2  * OMAP and TWL PMIC specific intializations.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated.
   5  * Thara Gopinath
   6  * Copyright (C) 2009 Texas Instruments Incorporated.
   7  * Nishanth Menon
   8  * Copyright (C) 2009 Nokia Corporation
   9  * Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/i2c/twl.h>
  20
  21 #include "voltage.h"
  22
  23 #include "pm.h"
  24
  25 #define OMAP3_SRI2C_SLAVE_ADDR          0x12
  26 #define OMAP3_VDD_MPU_SR_CONTROL_REG    0x00
  27 #define OMAP3_VDD_CORE_SR_CONTROL_REG   0x01
  28 #define OMAP3_VP_CONFIG_ERROROFFSET     0x00
  29 #define OMAP3_VP_VSTEPMIN_VSTEPMIN      0x1
  30 #define OMAP3_VP_VSTEPMAX_VSTEPMAX      0x04
  31 #define OMAP3_VP_VLIMITTO_TIMEOUT_US    200
  32
  33 #define OMAP4_SRI2C_SLAVE_ADDR          0x12
  34 #define OMAP4_VDD_MPU_SR_VOLT_REG       0x55
  35 #define OMAP4_VDD_MPU_SR_CMD_REG        0x56
  36 #define OMAP4_VDD_IVA_SR_VOLT_REG       0x5B
  37 #define OMAP4_VDD_IVA_SR_CMD_REG        0x5C
  38 #define OMAP4_VDD_CORE_SR_VOLT_REG      0x61
  39 #define OMAP4_VDD_CORE_SR_CMD_REG       0x62
  40
  41 #define OMAP4_VP_CONFIG_ERROROFFSET     0x00
  42 #define OMAP4_VP_VSTEPMIN_VSTEPMIN      0x01
  43 #define OMAP4_VP_VSTEPMAX_VSTEPMAX      0x04
  44 #define OMAP4_VP_VLIMITTO_TIMEOUT_US    200
  45
  46 static bool is_offset_valid;
  47 static u8 smps_offset;
  48 /*
  49  * Flag to ensure Smartreflex bit in TWL
  50  * being cleared in board file is not overwritten.
  51  */
  52 static bool __initdata twl_sr_enable_autoinit;
  53
  54 #define TWL4030_DCDC_GLOBAL_CFG        0x06
  55 #define REG_SMPS_OFFSET         0xE0
  56 #define SMARTREFLEX_ENABLE     BIT(3)
  57
  58 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
  59 {
  60         return (((vsel * 125) + 6000)) * 100;
  61 }
  62
  63 static u8 twl4030_uv_to_vsel(unsigned long uv)
  64 {
  65         return DIV_ROUND_UP(uv - 600000, 12500);
  66 }
  67
  68 static unsigned long twl6030_vsel_to_uv(const u8 vsel)
  69 {
  70         /*
  71          * In TWL6030 depending on the value of SMPS_OFFSET
  72          * efuse register the voltage range supported in
  73          * standard mode can be either between 0.6V - 1.3V or
  74          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
  75          * is programmed to all 0's where as starting from
  76          * TWL6030 ES1.1 the efuse is programmed to 1
  77          */
  78         if (!is_offset_valid) {
  79                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
  80                                 REG_SMPS_OFFSET);
  81                 is_offset_valid = true;
  82         }
  83
  84         if (!vsel)
  85                 return 0;
  86         /*
  87          * There is no specific formula for voltage to vsel
  88          * conversion above 1.3V. There are special hardcoded
  89          * values for voltages above 1.3V. Currently we are
  90          * hardcoding only for 1.35 V which is used for 1GH OPP for
  91          * OMAP4430.
  92          */
  93         if (vsel == 0x3A)
  94                 return 1350000;
  95
  96         if (smps_offset & 0x8)
  97                 return ((((vsel - 1) * 1266) + 70900)) * 10;
  98         else
  99                 return ((((vsel - 1) * 1266) + 60770)) * 10;
 100 }
 101
 102 static u8 twl6030_uv_to_vsel(unsigned long uv)
 103 {
 104         /*
 105          * In TWL6030 depending on the value of SMPS_OFFSET
 106          * efuse register the voltage range supported in
 107          * standard mode can be either between 0.6V - 1.3V or
 108          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
 109          * is programmed to all 0's where as starting from
 110          * TWL6030 ES1.1 the efuse is programmed to 1
 111          */
 112         if (!is_offset_valid) {
 113                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
 114                                 REG_SMPS_OFFSET);
 115                 is_offset_valid = true;
 116         }
 117
 118         if (!uv)
 119                 return 0x00;
 120         /*
 121          * There is no specific formula for voltage to vsel
 122          * conversion above 1.3V. There are special hardcoded
 123          * values for voltages above 1.3V. Currently we are
 124          * hardcoding only for 1.35 V which is used for 1GH OPP for
 125          * OMAP4430.
 126          */
 127         if (uv > twl6030_vsel_to_uv(0x39)) {
 128                 if (uv == 1350000)
 129                         return 0x3A;
 130                 pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
 131                         __func__, uv, twl6030_vsel_to_uv(0x39));
 132                 return 0x3A;
 133         }
 134
 135         if (smps_offset & 0x8)
 136                 return DIV_ROUND_UP(uv - 709000, 12660) + 1;
 137         else
 138                 return DIV_ROUND_UP(uv - 607700, 12660) + 1;
 139 }
 140
 141 static struct omap_voltdm_pmic omap3_mpu_pmic = {
 142         .slew_rate              = 4000,
 143         .step_size              = 12500,
 144         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 145         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 146         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 147         .vddmin                 = 600000,
 148         .vddmax                 = 1450000,
 149         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 150         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 151         .volt_reg_addr          = OMAP3_VDD_MPU_SR_CONTROL_REG,
 152         .i2c_high_speed         = true,
 153         .vsel_to_uv             = twl4030_vsel_to_uv,
 154         .uv_to_vsel             = twl4030_uv_to_vsel,
 155 };
 156
 157 static struct omap_voltdm_pmic omap3_core_pmic = {
 158         .slew_rate              = 4000,
 159         .step_size              = 12500,
 160         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 161         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 162         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 163         .vddmin                 = 600000,
 164         .vddmax                 = 1450000,
 165         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 166         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 167         .volt_reg_addr          = OMAP3_VDD_CORE_SR_CONTROL_REG,
 168         .i2c_high_speed         = true,
 169         .vsel_to_uv             = twl4030_vsel_to_uv,
 170         .uv_to_vsel             = twl4030_uv_to_vsel,
 171 };
 172
 173 static struct omap_voltdm_pmic omap4_mpu_pmic = {
 174         .slew_rate              = 4000,
 175         .step_size              = 12660,
 176         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 177         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 178         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 179         .vddmin                 = 0,
 180         .vddmax                 = 2100000,
 181         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 182         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 183         .volt_reg_addr          = OMAP4_VDD_MPU_SR_VOLT_REG,
 184         .cmd_reg_addr           = OMAP4_VDD_MPU_SR_CMD_REG,
 185         .i2c_high_speed         = true,
 186         .i2c_pad_load           = 3,
 187         .vsel_to_uv             = twl6030_vsel_to_uv,
 188         .uv_to_vsel             = twl6030_uv_to_vsel,
 189 };
 190
 191 static struct omap_voltdm_pmic omap4_iva_pmic = {
 192         .slew_rate              = 4000,
 193         .step_size              = 12660,
 194         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 195         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 196         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 197         .vddmin                 = 0,
 198         .vddmax                 = 2100000,
 199         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 200         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 201         .volt_reg_addr          = OMAP4_VDD_IVA_SR_VOLT_REG,
 202         .cmd_reg_addr           = OMAP4_VDD_IVA_SR_CMD_REG,
 203         .i2c_high_speed         = true,
 204         .i2c_pad_load           = 3,
 205         .vsel_to_uv             = twl6030_vsel_to_uv,
 206         .uv_to_vsel             = twl6030_uv_to_vsel,
 207 };
 208
 209 static struct omap_voltdm_pmic omap4_core_pmic = {
 210         .slew_rate              = 4000,
 211         .step_size              = 12660,
 212         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 213         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 214         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 215         .vddmin                 = 0,
 216         .vddmax                 = 2100000,
 217         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 218         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 219         .volt_reg_addr          = OMAP4_VDD_CORE_SR_VOLT_REG,
 220         .cmd_reg_addr           = OMAP4_VDD_CORE_SR_CMD_REG,
 221         .i2c_pad_load           = 3,
 222         .vsel_to_uv             = twl6030_vsel_to_uv,
 223         .uv_to_vsel             = twl6030_uv_to_vsel,
 224 };
 225
 226 int __init omap4_twl_init(void)
 227 {
 228         struct voltagedomain *voltdm;
 229
 230         if (!cpu_is_omap44xx())
 231                 return -ENODEV;
 232
 233         voltdm = voltdm_lookup("mpu");
 234         omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
 235
 236         voltdm = voltdm_lookup("iva");
 237         omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
 238
 239         voltdm = voltdm_lookup("core");
 240         omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
 241
 242         return 0;
 243 }
 244
 245 int __init omap3_twl_init(void)
 246 {
 247         struct voltagedomain *voltdm;
 248
 249         if (!cpu_is_omap34xx())
 250                 return -ENODEV;
 251
 252         /*
 253          * The smartreflex bit on twl4030 specifies if the setting of voltage
 254          * is done over the I2C_SR path. Since this setting is independent of
 255          * the actual usage of smartreflex AVS module, we enable TWL SR bit
 256          * by default irrespective of whether smartreflex AVS module is enabled
 257          * on the OMAP side or not. This is because without this bit enabled,
 258          * the voltage scaling through vp forceupdate/bypass mechanism of
 259          * voltage scaling will not function on TWL over I2C_SR.
 260          */
 261         if (!twl_sr_enable_autoinit)
 262                 omap3_twl_set_sr_bit(true);
 263
 264         voltdm = voltdm_lookup("mpu_iva");
 265         omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
 266
 267         voltdm = voltdm_lookup("core");
 268         omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
 269
 270         return 0;
 271 }
 272
 273 /**
 274  * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
 275  * @enable: enable SR mode in twl or not
 276  *
 277  * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
 278  * voltage scaling through OMAP SR works. Else, the smartreflex bit
 279  * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
 280  * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
 281  * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
 282  * in those scenarios this bit is to be cleared (enable = false).
 283  *
 284  * Returns 0 on success, error is returned if I2C read/write fails.
 285  */
 286 int __init omap3_twl_set_sr_bit(bool enable)
 287 {
 288         u8 temp;
 289         int ret;
 290         if (twl_sr_enable_autoinit)
 291                 pr_warning("%s: unexpected multiple calls\n", __func__);
 292
 293         ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
 294                                         TWL4030_DCDC_GLOBAL_CFG);
 295         if (ret)
 296                 goto err;
 297
 298         if (enable)
 299                 temp |= SMARTREFLEX_ENABLE;
 300         else
 301                 temp &= ~SMARTREFLEX_ENABLE;
 302
 303         ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
 304                                 TWL4030_DCDC_GLOBAL_CFG);
 305         if (!ret) {
 306                 twl_sr_enable_autoinit = true;
 307                 return 0;
 308         }
 309 err:
 310         pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
 311         return ret;
 312 }