Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "smartreflex.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /*
  54  * 'c2c_target_fw' class
  55  * instance(s): c2c_target_fw
  56  */
  57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58         .name   = "c2c_target_fw",
  59 };
  60
  61 /* c2c_target_fw */
  62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63         .name           = "c2c_target_fw",
  64         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  65         .clkdm_name     = "d2d_clkdm",
  66         .prcm = {
  67                 .omap4 = {
  68                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm */
  83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85         { .irq = -1 }
  86 };
  87
  88 static struct omap_hwmod omap44xx_dmm_hwmod = {
  89         .name           = "dmm",
  90         .class          = &omap44xx_dmm_hwmod_class,
  91         .clkdm_name     = "l3_emif_clkdm",
  92         .mpu_irqs       = omap44xx_dmm_irqs,
  93         .prcm = {
  94                 .omap4 = {
  95                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97                 },
  98         },
  99 };
 100
 101 /*
 102  * 'emif_fw' class
 103  * instance(s): emif_fw
 104  */
 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106         .name   = "emif_fw",
 107 };
 108
 109 /* emif_fw */
 110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111         .name           = "emif_fw",
 112         .class          = &omap44xx_emif_fw_hwmod_class,
 113         .clkdm_name     = "l3_emif_clkdm",
 114         .prcm = {
 115                 .omap4 = {
 116                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'l3' class
 124  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125  */
 126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127         .name   = "l3",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &omap44xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_instr_clkdm",
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139                         .modulemode   = MODULEMODE_HWCTRL,
 140                 },
 141         },
 142 };
 143
 144 /* l3_main_1 */
 145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148         { .irq = -1 }
 149 };
 150
 151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152         .name           = "l3_main_1",
 153         .class          = &omap44xx_l3_hwmod_class,
 154         .clkdm_name     = "l3_1_clkdm",
 155         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160                 },
 161         },
 162 };
 163
 164 /* l3_main_2 */
 165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166         .name           = "l3_main_2",
 167         .class          = &omap44xx_l3_hwmod_class,
 168         .clkdm_name     = "l3_2_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173                 },
 174         },
 175 };
 176
 177 /* l3_main_3 */
 178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179         .name           = "l3_main_3",
 180         .class          = &omap44xx_l3_hwmod_class,
 181         .clkdm_name     = "l3_instr_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186                         .modulemode   = MODULEMODE_HWCTRL,
 187                 },
 188         },
 189 };
 190
 191 /*
 192  * 'l4' class
 193  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194  */
 195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196         .name   = "l4",
 197 };
 198
 199 /* l4_abe */
 200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201         .name           = "l4_abe",
 202         .class          = &omap44xx_l4_hwmod_class,
 203         .clkdm_name     = "abe_clkdm",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207                 },
 208         },
 209 };
 210
 211 /* l4_cfg */
 212 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 213         .name           = "l4_cfg",
 214         .class          = &omap44xx_l4_hwmod_class,
 215         .clkdm_name     = "l4_cfg_clkdm",
 216         .prcm = {
 217                 .omap4 = {
 218                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 219                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 220                 },
 221         },
 222 };
 223
 224 /* l4_per */
 225 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 226         .name           = "l4_per",
 227         .class          = &omap44xx_l4_hwmod_class,
 228         .clkdm_name     = "l4_per_clkdm",
 229         .prcm = {
 230                 .omap4 = {
 231                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 232                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 233                 },
 234         },
 235 };
 236
 237 /* l4_wkup */
 238 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 239         .name           = "l4_wkup",
 240         .class          = &omap44xx_l4_hwmod_class,
 241         .clkdm_name     = "l4_wkup_clkdm",
 242         .prcm = {
 243                 .omap4 = {
 244                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 245                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 246                 },
 247         },
 248 };
 249
 250 /*
 251  * 'mpu_bus' class
 252  * instance(s): mpu_private
 253  */
 254 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 255         .name   = "mpu_bus",
 256 };
 257
 258 /* mpu_private */
 259 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 260         .name           = "mpu_private",
 261         .class          = &omap44xx_mpu_bus_hwmod_class,
 262         .clkdm_name     = "mpuss_clkdm",
 263 };
 264
 265 /*
 266  * 'ocp_wp_noc' class
 267  * instance(s): ocp_wp_noc
 268  */
 269 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 270         .name   = "ocp_wp_noc",
 271 };
 272
 273 /* ocp_wp_noc */
 274 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 275         .name           = "ocp_wp_noc",
 276         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 277         .clkdm_name     = "l3_instr_clkdm",
 278         .prcm = {
 279                 .omap4 = {
 280                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 281                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 282                         .modulemode   = MODULEMODE_HWCTRL,
 283                 },
 284         },
 285 };
 286
 287 /*
 288  * Modules omap_hwmod structures
 289  *
 290  * The following IPs are excluded for the moment because:
 291  * - They do not need an explicit SW control using omap_hwmod API.
 292  * - They still need to be validated with the driver
 293  *   properly adapted to omap_hwmod / omap_device
 294  *
 295  * usim
 296  */
 297
 298 /*
 299  * 'aess' class
 300  * audio engine sub system
 301  */
 302
 303 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 304         .rev_offs       = 0x0000,
 305         .sysc_offs      = 0x0010,
 306         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 308                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 309                            MSTANDBY_SMART_WKUP),
 310         .sysc_fields    = &omap_hwmod_sysc_type2,
 311 };
 312
 313 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 314         .name   = "aess",
 315         .sysc   = &omap44xx_aess_sysc,
 316 };
 317
 318 /* aess */
 319 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 320         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 321         { .irq = -1 }
 322 };
 323
 324 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 325         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 326         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 327         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 328         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 329         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 330         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 331         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 332         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 333         { .dma_req = -1 }
 334 };
 335
 336 static struct omap_hwmod omap44xx_aess_hwmod = {
 337         .name           = "aess",
 338         .class          = &omap44xx_aess_hwmod_class,
 339         .clkdm_name     = "abe_clkdm",
 340         .mpu_irqs       = omap44xx_aess_irqs,
 341         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 342         .main_clk       = "aess_fck",
 343         .prcm = {
 344                 .omap4 = {
 345                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 346                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 347                         .modulemode   = MODULEMODE_SWCTRL,
 348                 },
 349         },
 350 };
 351
 352 /*
 353  * 'c2c' class
 354  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 355  * soc
 356  */
 357
 358 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 359         .name   = "c2c",
 360 };
 361
 362 /* c2c */
 363 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 364         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 365         { .irq = -1 }
 366 };
 367
 368 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 369         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 370         { .dma_req = -1 }
 371 };
 372
 373 static struct omap_hwmod omap44xx_c2c_hwmod = {
 374         .name           = "c2c",
 375         .class          = &omap44xx_c2c_hwmod_class,
 376         .clkdm_name     = "d2d_clkdm",
 377         .mpu_irqs       = omap44xx_c2c_irqs,
 378         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 382                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 383                 },
 384         },
 385 };
 386
 387 /*
 388  * 'counter' class
 389  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 390  */
 391
 392 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 393         .rev_offs       = 0x0000,
 394         .sysc_offs      = 0x0004,
 395         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 396         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 397                            SIDLE_SMART_WKUP),
 398         .sysc_fields    = &omap_hwmod_sysc_type1,
 399 };
 400
 401 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 402         .name   = "counter",
 403         .sysc   = &omap44xx_counter_sysc,
 404 };
 405
 406 /* counter_32k */
 407 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 408         .name           = "counter_32k",
 409         .class          = &omap44xx_counter_hwmod_class,
 410         .clkdm_name     = "l4_wkup_clkdm",
 411         .flags          = HWMOD_SWSUP_SIDLE,
 412         .main_clk       = "sys_32k_ck",
 413         .prcm = {
 414                 .omap4 = {
 415                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 416                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 417                 },
 418         },
 419 };
 420
 421 /*
 422  * 'ctrl_module' class
 423  * attila core control module + core pad control module + wkup pad control
 424  * module + attila wkup control module
 425  */
 426
 427 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 428         .rev_offs       = 0x0000,
 429         .sysc_offs      = 0x0010,
 430         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 432                            SIDLE_SMART_WKUP),
 433         .sysc_fields    = &omap_hwmod_sysc_type2,
 434 };
 435
 436 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 437         .name   = "ctrl_module",
 438         .sysc   = &omap44xx_ctrl_module_sysc,
 439 };
 440
 441 /* ctrl_module_core */
 442 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 443         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 444         { .irq = -1 }
 445 };
 446
 447 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 448         .name           = "ctrl_module_core",
 449         .class          = &omap44xx_ctrl_module_hwmod_class,
 450         .clkdm_name     = "l4_cfg_clkdm",
 451         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 452 };
 453
 454 /* ctrl_module_pad_core */
 455 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 456         .name           = "ctrl_module_pad_core",
 457         .class          = &omap44xx_ctrl_module_hwmod_class,
 458         .clkdm_name     = "l4_cfg_clkdm",
 459 };
 460
 461 /* ctrl_module_wkup */
 462 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 463         .name           = "ctrl_module_wkup",
 464         .class          = &omap44xx_ctrl_module_hwmod_class,
 465         .clkdm_name     = "l4_wkup_clkdm",
 466 };
 467
 468 /* ctrl_module_pad_wkup */
 469 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 470         .name           = "ctrl_module_pad_wkup",
 471         .class          = &omap44xx_ctrl_module_hwmod_class,
 472         .clkdm_name     = "l4_wkup_clkdm",
 473 };
 474
 475 /*
 476  * 'debugss' class
 477  * debug and emulation sub system
 478  */
 479
 480 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 481         .name   = "debugss",
 482 };
 483
 484 /* debugss */
 485 static struct omap_hwmod omap44xx_debugss_hwmod = {
 486         .name           = "debugss",
 487         .class          = &omap44xx_debugss_hwmod_class,
 488         .clkdm_name     = "emu_sys_clkdm",
 489         .main_clk       = "trace_clk_div_ck",
 490         .prcm = {
 491                 .omap4 = {
 492                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 493                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 494                 },
 495         },
 496 };
 497
 498 /*
 499  * 'dma' class
 500  * dma controller for data exchange between memory to memory (i.e. internal or
 501  * external memory) and gp peripherals to memory or memory to gp peripherals
 502  */
 503
 504 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 505         .rev_offs       = 0x0000,
 506         .sysc_offs      = 0x002c,
 507         .syss_offs      = 0x0028,
 508         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 509                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 510                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 511                            SYSS_HAS_RESET_STATUS),
 512         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 513                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 514         .sysc_fields    = &omap_hwmod_sysc_type1,
 515 };
 516
 517 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 518         .name   = "dma",
 519         .sysc   = &omap44xx_dma_sysc,
 520 };
 521
 522 /* dma dev_attr */
 523 static struct omap_dma_dev_attr dma_dev_attr = {
 524         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 525                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 526         .lch_count      = 32,
 527 };
 528
 529 /* dma_system */
 530 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 531         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 532         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 533         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 534         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 535         { .irq = -1 }
 536 };
 537
 538 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 539         .name           = "dma_system",
 540         .class          = &omap44xx_dma_hwmod_class,
 541         .clkdm_name     = "l3_dma_clkdm",
 542         .mpu_irqs       = omap44xx_dma_system_irqs,
 543         .main_clk       = "l3_div_ck",
 544         .prcm = {
 545                 .omap4 = {
 546                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 547                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 548                 },
 549         },
 550         .dev_attr       = &dma_dev_attr,
 551 };
 552
 553 /*
 554  * 'dmic' class
 555  * digital microphone controller
 556  */
 557
 558 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 559         .rev_offs       = 0x0000,
 560         .sysc_offs      = 0x0010,
 561         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 562                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 564                            SIDLE_SMART_WKUP),
 565         .sysc_fields    = &omap_hwmod_sysc_type2,
 566 };
 567
 568 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 569         .name   = "dmic",
 570         .sysc   = &omap44xx_dmic_sysc,
 571 };
 572
 573 /* dmic */
 574 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 575         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 576         { .irq = -1 }
 577 };
 578
 579 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 580         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 581         { .dma_req = -1 }
 582 };
 583
 584 static struct omap_hwmod omap44xx_dmic_hwmod = {
 585         .name           = "dmic",
 586         .class          = &omap44xx_dmic_hwmod_class,
 587         .clkdm_name     = "abe_clkdm",
 588         .mpu_irqs       = omap44xx_dmic_irqs,
 589         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 590         .main_clk       = "dmic_fck",
 591         .prcm = {
 592                 .omap4 = {
 593                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 594                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 595                         .modulemode   = MODULEMODE_SWCTRL,
 596                 },
 597         },
 598 };
 599
 600 /*
 601  * 'dsp' class
 602  * dsp sub-system
 603  */
 604
 605 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 606         .name   = "dsp",
 607 };
 608
 609 /* dsp */
 610 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 611         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 612         { .irq = -1 }
 613 };
 614
 615 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 616         { .name = "dsp", .rst_shift = 0 },
 617         { .name = "mmu_cache", .rst_shift = 1 },
 618 };
 619
 620 static struct omap_hwmod omap44xx_dsp_hwmod = {
 621         .name           = "dsp",
 622         .class          = &omap44xx_dsp_hwmod_class,
 623         .clkdm_name     = "tesla_clkdm",
 624         .mpu_irqs       = omap44xx_dsp_irqs,
 625         .rst_lines      = omap44xx_dsp_resets,
 626         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 627         .main_clk       = "dsp_fck",
 628         .prcm = {
 629                 .omap4 = {
 630                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 631                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 632                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 633                         .modulemode   = MODULEMODE_HWCTRL,
 634                 },
 635         },
 636 };
 637
 638 /*
 639  * 'dss' class
 640  * display sub-system
 641  */
 642
 643 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 644         .rev_offs       = 0x0000,
 645         .syss_offs      = 0x0014,
 646         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 647 };
 648
 649 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 650         .name   = "dss",
 651         .sysc   = &omap44xx_dss_sysc,
 652         .reset  = omap_dss_reset,
 653 };
 654
 655 /* dss */
 656 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 657         { .role = "sys_clk", .clk = "dss_sys_clk" },
 658         { .role = "tv_clk", .clk = "dss_tv_clk" },
 659         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 660 };
 661
 662 static struct omap_hwmod omap44xx_dss_hwmod = {
 663         .name           = "dss_core",
 664         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 665         .class          = &omap44xx_dss_hwmod_class,
 666         .clkdm_name     = "l3_dss_clkdm",
 667         .main_clk       = "dss_dss_clk",
 668         .prcm = {
 669                 .omap4 = {
 670                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 671                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 672                 },
 673         },
 674         .opt_clks       = dss_opt_clks,
 675         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 676 };
 677
 678 /*
 679  * 'dispc' class
 680  * display controller
 681  */
 682
 683 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 684         .rev_offs       = 0x0000,
 685         .sysc_offs      = 0x0010,
 686         .syss_offs      = 0x0014,
 687         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 688                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 689                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 690                            SYSS_HAS_RESET_STATUS),
 691         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 692                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 693         .sysc_fields    = &omap_hwmod_sysc_type1,
 694 };
 695
 696 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 697         .name   = "dispc",
 698         .sysc   = &omap44xx_dispc_sysc,
 699 };
 700
 701 /* dss_dispc */
 702 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 703         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 704         { .irq = -1 }
 705 };
 706
 707 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 708         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 709         { .dma_req = -1 }
 710 };
 711
 712 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 713         .manager_count          = 3,
 714         .has_framedonetv_irq    = 1
 715 };
 716
 717 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 718         .name           = "dss_dispc",
 719         .class          = &omap44xx_dispc_hwmod_class,
 720         .clkdm_name     = "l3_dss_clkdm",
 721         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 722         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 723         .main_clk       = "dss_dss_clk",
 724         .prcm = {
 725                 .omap4 = {
 726                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 727                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 728                 },
 729         },
 730         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 731 };
 732
 733 /*
 734  * 'dsi' class
 735  * display serial interface controller
 736  */
 737
 738 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 739         .rev_offs       = 0x0000,
 740         .sysc_offs      = 0x0010,
 741         .syss_offs      = 0x0014,
 742         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 743                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 744                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 745         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 746         .sysc_fields    = &omap_hwmod_sysc_type1,
 747 };
 748
 749 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 750         .name   = "dsi",
 751         .sysc   = &omap44xx_dsi_sysc,
 752 };
 753
 754 /* dss_dsi1 */
 755 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 756         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 757         { .irq = -1 }
 758 };
 759
 760 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 761         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 762         { .dma_req = -1 }
 763 };
 764
 765 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 766         { .role = "sys_clk", .clk = "dss_sys_clk" },
 767 };
 768
 769 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 770         .name           = "dss_dsi1",
 771         .class          = &omap44xx_dsi_hwmod_class,
 772         .clkdm_name     = "l3_dss_clkdm",
 773         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 774         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 775         .main_clk       = "dss_dss_clk",
 776         .prcm = {
 777                 .omap4 = {
 778                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 779                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 780                 },
 781         },
 782         .opt_clks       = dss_dsi1_opt_clks,
 783         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 784 };
 785
 786 /* dss_dsi2 */
 787 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 788         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 789         { .irq = -1 }
 790 };
 791
 792 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 793         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 794         { .dma_req = -1 }
 795 };
 796
 797 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 798         { .role = "sys_clk", .clk = "dss_sys_clk" },
 799 };
 800
 801 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 802         .name           = "dss_dsi2",
 803         .class          = &omap44xx_dsi_hwmod_class,
 804         .clkdm_name     = "l3_dss_clkdm",
 805         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 806         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 807         .main_clk       = "dss_dss_clk",
 808         .prcm = {
 809                 .omap4 = {
 810                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 811                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 812                 },
 813         },
 814         .opt_clks       = dss_dsi2_opt_clks,
 815         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 816 };
 817
 818 /*
 819  * 'hdmi' class
 820  * hdmi controller
 821  */
 822
 823 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 824         .rev_offs       = 0x0000,
 825         .sysc_offs      = 0x0010,
 826         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 827                            SYSC_HAS_SOFTRESET),
 828         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 829                            SIDLE_SMART_WKUP),
 830         .sysc_fields    = &omap_hwmod_sysc_type2,
 831 };
 832
 833 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 834         .name   = "hdmi",
 835         .sysc   = &omap44xx_hdmi_sysc,
 836 };
 837
 838 /* dss_hdmi */
 839 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 840         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 841         { .irq = -1 }
 842 };
 843
 844 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 845         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 846         { .dma_req = -1 }
 847 };
 848
 849 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 850         { .role = "sys_clk", .clk = "dss_sys_clk" },
 851 };
 852
 853 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 854         .name           = "dss_hdmi",
 855         .class          = &omap44xx_hdmi_hwmod_class,
 856         .clkdm_name     = "l3_dss_clkdm",
 857         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 858         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 859         .main_clk       = "dss_48mhz_clk",
 860         .prcm = {
 861                 .omap4 = {
 862                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 863                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 864                 },
 865         },
 866         .opt_clks       = dss_hdmi_opt_clks,
 867         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 868 };
 869
 870 /*
 871  * 'rfbi' class
 872  * remote frame buffer interface
 873  */
 874
 875 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 876         .rev_offs       = 0x0000,
 877         .sysc_offs      = 0x0010,
 878         .syss_offs      = 0x0014,
 879         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 880                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 881         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 882         .sysc_fields    = &omap_hwmod_sysc_type1,
 883 };
 884
 885 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 886         .name   = "rfbi",
 887         .sysc   = &omap44xx_rfbi_sysc,
 888 };
 889
 890 /* dss_rfbi */
 891 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 892         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 893         { .dma_req = -1 }
 894 };
 895
 896 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 897         { .role = "ick", .clk = "dss_fck" },
 898 };
 899
 900 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 901         .name           = "dss_rfbi",
 902         .class          = &omap44xx_rfbi_hwmod_class,
 903         .clkdm_name     = "l3_dss_clkdm",
 904         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 905         .main_clk       = "dss_dss_clk",
 906         .prcm = {
 907                 .omap4 = {
 908                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 909                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 910                 },
 911         },
 912         .opt_clks       = dss_rfbi_opt_clks,
 913         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 914 };
 915
 916 /*
 917  * 'venc' class
 918  * video encoder
 919  */
 920
 921 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 922         .name   = "venc",
 923 };
 924
 925 /* dss_venc */
 926 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 927         .name           = "dss_venc",
 928         .class          = &omap44xx_venc_hwmod_class,
 929         .clkdm_name     = "l3_dss_clkdm",
 930         .main_clk       = "dss_tv_clk",
 931         .prcm = {
 932                 .omap4 = {
 933                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 934                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 935                 },
 936         },
 937 };
 938
 939 /*
 940  * 'elm' class
 941  * bch error location module
 942  */
 943
 944 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 945         .rev_offs       = 0x0000,
 946         .sysc_offs      = 0x0010,
 947         .syss_offs      = 0x0014,
 948         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 949                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 950                            SYSS_HAS_RESET_STATUS),
 951         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 952         .sysc_fields    = &omap_hwmod_sysc_type1,
 953 };
 954
 955 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 956         .name   = "elm",
 957         .sysc   = &omap44xx_elm_sysc,
 958 };
 959
 960 /* elm */
 961 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 962         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 963         { .irq = -1 }
 964 };
 965
 966 static struct omap_hwmod omap44xx_elm_hwmod = {
 967         .name           = "elm",
 968         .class          = &omap44xx_elm_hwmod_class,
 969         .clkdm_name     = "l4_per_clkdm",
 970         .mpu_irqs       = omap44xx_elm_irqs,
 971         .prcm = {
 972                 .omap4 = {
 973                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 974                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 975                 },
 976         },
 977 };
 978
 979 /*
 980  * 'emif' class
 981  * external memory interface no1
 982  */
 983
 984 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 985         .rev_offs       = 0x0000,
 986 };
 987
 988 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 989         .name   = "emif",
 990         .sysc   = &omap44xx_emif_sysc,
 991 };
 992
 993 /* emif1 */
 994 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
 995         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
 996         { .irq = -1 }
 997 };
 998
 999 static struct omap_hwmod omap44xx_emif1_hwmod = {
1000         .name           = "emif1",
1001         .class          = &omap44xx_emif_hwmod_class,
1002         .clkdm_name     = "l3_emif_clkdm",
1003         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1004         .mpu_irqs       = omap44xx_emif1_irqs,
1005         .main_clk       = "ddrphy_ck",
1006         .prcm = {
1007                 .omap4 = {
1008                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1009                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1010                         .modulemode   = MODULEMODE_HWCTRL,
1011                 },
1012         },
1013 };
1014
1015 /* emif2 */
1016 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1017         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1018         { .irq = -1 }
1019 };
1020
1021 static struct omap_hwmod omap44xx_emif2_hwmod = {
1022         .name           = "emif2",
1023         .class          = &omap44xx_emif_hwmod_class,
1024         .clkdm_name     = "l3_emif_clkdm",
1025         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1026         .mpu_irqs       = omap44xx_emif2_irqs,
1027         .main_clk       = "ddrphy_ck",
1028         .prcm = {
1029                 .omap4 = {
1030                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1031                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1032                         .modulemode   = MODULEMODE_HWCTRL,
1033                 },
1034         },
1035 };
1036
1037 /*
1038  * 'fdif' class
1039  * face detection hw accelerator module
1040  */
1041
1042 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1043         .rev_offs       = 0x0000,
1044         .sysc_offs      = 0x0010,
1045         /*
1046          * FDIF needs 100 OCP clk cycles delay after a softreset before
1047          * accessing sysconfig again.
1048          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1049          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1050          *
1051          * TODO: Indicate errata when available.
1052          */
1053         .srst_udelay    = 2,
1054         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1055                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1056         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1057                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1058         .sysc_fields    = &omap_hwmod_sysc_type2,
1059 };
1060
1061 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1062         .name   = "fdif",
1063         .sysc   = &omap44xx_fdif_sysc,
1064 };
1065
1066 /* fdif */
1067 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1068         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1069         { .irq = -1 }
1070 };
1071
1072 static struct omap_hwmod omap44xx_fdif_hwmod = {
1073         .name           = "fdif",
1074         .class          = &omap44xx_fdif_hwmod_class,
1075         .clkdm_name     = "iss_clkdm",
1076         .mpu_irqs       = omap44xx_fdif_irqs,
1077         .main_clk       = "fdif_fck",
1078         .prcm = {
1079                 .omap4 = {
1080                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1081                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1082                         .modulemode   = MODULEMODE_SWCTRL,
1083                 },
1084         },
1085 };
1086
1087 /*
1088  * 'gpio' class
1089  * general purpose io module
1090  */
1091
1092 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1093         .rev_offs       = 0x0000,
1094         .sysc_offs      = 0x0010,
1095         .syss_offs      = 0x0114,
1096         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1097                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1098                            SYSS_HAS_RESET_STATUS),
1099         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1100                            SIDLE_SMART_WKUP),
1101         .sysc_fields    = &omap_hwmod_sysc_type1,
1102 };
1103
1104 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1105         .name   = "gpio",
1106         .sysc   = &omap44xx_gpio_sysc,
1107         .rev    = 2,
1108 };
1109
1110 /* gpio dev_attr */
1111 static struct omap_gpio_dev_attr gpio_dev_attr = {
1112         .bank_width     = 32,
1113         .dbck_flag      = true,
1114 };
1115
1116 /* gpio1 */
1117 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1118         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1119         { .irq = -1 }
1120 };
1121
1122 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1123         { .role = "dbclk", .clk = "gpio1_dbclk" },
1124 };
1125
1126 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1127         .name           = "gpio1",
1128         .class          = &omap44xx_gpio_hwmod_class,
1129         .clkdm_name     = "l4_wkup_clkdm",
1130         .mpu_irqs       = omap44xx_gpio1_irqs,
1131         .main_clk       = "gpio1_ick",
1132         .prcm = {
1133                 .omap4 = {
1134                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1135                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1136                         .modulemode   = MODULEMODE_HWCTRL,
1137                 },
1138         },
1139         .opt_clks       = gpio1_opt_clks,
1140         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1141         .dev_attr       = &gpio_dev_attr,
1142 };
1143
1144 /* gpio2 */
1145 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1146         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1147         { .irq = -1 }
1148 };
1149
1150 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1151         { .role = "dbclk", .clk = "gpio2_dbclk" },
1152 };
1153
1154 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1155         .name           = "gpio2",
1156         .class          = &omap44xx_gpio_hwmod_class,
1157         .clkdm_name     = "l4_per_clkdm",
1158         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1159         .mpu_irqs       = omap44xx_gpio2_irqs,
1160         .main_clk       = "gpio2_ick",
1161         .prcm = {
1162                 .omap4 = {
1163                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1164                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1165                         .modulemode   = MODULEMODE_HWCTRL,
1166                 },
1167         },
1168         .opt_clks       = gpio2_opt_clks,
1169         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1170         .dev_attr       = &gpio_dev_attr,
1171 };
1172
1173 /* gpio3 */
1174 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1175         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1176         { .irq = -1 }
1177 };
1178
1179 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1180         { .role = "dbclk", .clk = "gpio3_dbclk" },
1181 };
1182
1183 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1184         .name           = "gpio3",
1185         .class          = &omap44xx_gpio_hwmod_class,
1186         .clkdm_name     = "l4_per_clkdm",
1187         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1188         .mpu_irqs       = omap44xx_gpio3_irqs,
1189         .main_clk       = "gpio3_ick",
1190         .prcm = {
1191                 .omap4 = {
1192                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1193                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1194                         .modulemode   = MODULEMODE_HWCTRL,
1195                 },
1196         },
1197         .opt_clks       = gpio3_opt_clks,
1198         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1199         .dev_attr       = &gpio_dev_attr,
1200 };
1201
1202 /* gpio4 */
1203 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1204         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1205         { .irq = -1 }
1206 };
1207
1208 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1209         { .role = "dbclk", .clk = "gpio4_dbclk" },
1210 };
1211
1212 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1213         .name           = "gpio4",
1214         .class          = &omap44xx_gpio_hwmod_class,
1215         .clkdm_name     = "l4_per_clkdm",
1216         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1217         .mpu_irqs       = omap44xx_gpio4_irqs,
1218         .main_clk       = "gpio4_ick",
1219         .prcm = {
1220                 .omap4 = {
1221                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1222                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1223                         .modulemode   = MODULEMODE_HWCTRL,
1224                 },
1225         },
1226         .opt_clks       = gpio4_opt_clks,
1227         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1228         .dev_attr       = &gpio_dev_attr,
1229 };
1230
1231 /* gpio5 */
1232 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1233         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1234         { .irq = -1 }
1235 };
1236
1237 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1238         { .role = "dbclk", .clk = "gpio5_dbclk" },
1239 };
1240
1241 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1242         .name           = "gpio5",
1243         .class          = &omap44xx_gpio_hwmod_class,
1244         .clkdm_name     = "l4_per_clkdm",
1245         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1246         .mpu_irqs       = omap44xx_gpio5_irqs,
1247         .main_clk       = "gpio5_ick",
1248         .prcm = {
1249                 .omap4 = {
1250                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1251                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1252                         .modulemode   = MODULEMODE_HWCTRL,
1253                 },
1254         },
1255         .opt_clks       = gpio5_opt_clks,
1256         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1257         .dev_attr       = &gpio_dev_attr,
1258 };
1259
1260 /* gpio6 */
1261 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1262         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1263         { .irq = -1 }
1264 };
1265
1266 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1267         { .role = "dbclk", .clk = "gpio6_dbclk" },
1268 };
1269
1270 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1271         .name           = "gpio6",
1272         .class          = &omap44xx_gpio_hwmod_class,
1273         .clkdm_name     = "l4_per_clkdm",
1274         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1275         .mpu_irqs       = omap44xx_gpio6_irqs,
1276         .main_clk       = "gpio6_ick",
1277         .prcm = {
1278                 .omap4 = {
1279                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1280                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1281                         .modulemode   = MODULEMODE_HWCTRL,
1282                 },
1283         },
1284         .opt_clks       = gpio6_opt_clks,
1285         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1286         .dev_attr       = &gpio_dev_attr,
1287 };
1288
1289 /*
1290  * 'gpmc' class
1291  * general purpose memory controller
1292  */
1293
1294 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1295         .rev_offs       = 0x0000,
1296         .sysc_offs      = 0x0010,
1297         .syss_offs      = 0x0014,
1298         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1299                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1300         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1301         .sysc_fields    = &omap_hwmod_sysc_type1,
1302 };
1303
1304 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1305         .name   = "gpmc",
1306         .sysc   = &omap44xx_gpmc_sysc,
1307 };
1308
1309 /* gpmc */
1310 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1311         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1312         { .irq = -1 }
1313 };
1314
1315 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1316         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1317         { .dma_req = -1 }
1318 };
1319
1320 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1321         .name           = "gpmc",
1322         .class          = &omap44xx_gpmc_hwmod_class,
1323         .clkdm_name     = "l3_2_clkdm",
1324         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1325         .mpu_irqs       = omap44xx_gpmc_irqs,
1326         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1327         .prcm = {
1328                 .omap4 = {
1329                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1330                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1331                         .modulemode   = MODULEMODE_HWCTRL,
1332                 },
1333         },
1334 };
1335
1336 /*
1337  * 'gpu' class
1338  * 2d/3d graphics accelerator
1339  */
1340
1341 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1342         .rev_offs       = 0x1fc00,
1343         .sysc_offs      = 0x1fc10,
1344         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1345         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1346                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1347                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1348         .sysc_fields    = &omap_hwmod_sysc_type2,
1349 };
1350
1351 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1352         .name   = "gpu",
1353         .sysc   = &omap44xx_gpu_sysc,
1354 };
1355
1356 /* gpu */
1357 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1358         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1359         { .irq = -1 }
1360 };
1361
1362 static struct omap_hwmod omap44xx_gpu_hwmod = {
1363         .name           = "gpu",
1364         .class          = &omap44xx_gpu_hwmod_class,
1365         .clkdm_name     = "l3_gfx_clkdm",
1366         .mpu_irqs       = omap44xx_gpu_irqs,
1367         .main_clk       = "gpu_fck",
1368         .prcm = {
1369                 .omap4 = {
1370                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1371                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1372                         .modulemode   = MODULEMODE_SWCTRL,
1373                 },
1374         },
1375 };
1376
1377 /*
1378  * 'hdq1w' class
1379  * hdq / 1-wire serial interface controller
1380  */
1381
1382 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1383         .rev_offs       = 0x0000,
1384         .sysc_offs      = 0x0014,
1385         .syss_offs      = 0x0018,
1386         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1387                            SYSS_HAS_RESET_STATUS),
1388         .sysc_fields    = &omap_hwmod_sysc_type1,
1389 };
1390
1391 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1392         .name   = "hdq1w",
1393         .sysc   = &omap44xx_hdq1w_sysc,
1394 };
1395
1396 /* hdq1w */
1397 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1398         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1399         { .irq = -1 }
1400 };
1401
1402 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1403         .name           = "hdq1w",
1404         .class          = &omap44xx_hdq1w_hwmod_class,
1405         .clkdm_name     = "l4_per_clkdm",
1406         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1407         .mpu_irqs       = omap44xx_hdq1w_irqs,
1408         .main_clk       = "hdq1w_fck",
1409         .prcm = {
1410                 .omap4 = {
1411                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1412                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_SWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'hsi' class
1420  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1421  * serial if)
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0010,
1427         .syss_offs      = 0x0014,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1429                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1430                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1432                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1433                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1434         .sysc_fields    = &omap_hwmod_sysc_type1,
1435 };
1436
1437 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1438         .name   = "hsi",
1439         .sysc   = &omap44xx_hsi_sysc,
1440 };
1441
1442 /* hsi */
1443 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1444         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1445         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1446         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1447         { .irq = -1 }
1448 };
1449
1450 static struct omap_hwmod omap44xx_hsi_hwmod = {
1451         .name           = "hsi",
1452         .class          = &omap44xx_hsi_hwmod_class,
1453         .clkdm_name     = "l3_init_clkdm",
1454         .mpu_irqs       = omap44xx_hsi_irqs,
1455         .main_clk       = "hsi_fck",
1456         .prcm = {
1457                 .omap4 = {
1458                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1459                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1460                         .modulemode   = MODULEMODE_HWCTRL,
1461                 },
1462         },
1463 };
1464
1465 /*
1466  * 'i2c' class
1467  * multimaster high-speed i2c controller
1468  */
1469
1470 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1471         .sysc_offs      = 0x0010,
1472         .syss_offs      = 0x0090,
1473         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1474                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1475                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1476         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1477                            SIDLE_SMART_WKUP),
1478         .clockact       = CLOCKACT_TEST_ICLK,
1479         .sysc_fields    = &omap_hwmod_sysc_type1,
1480 };
1481
1482 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1483         .name   = "i2c",
1484         .sysc   = &omap44xx_i2c_sysc,
1485         .rev    = OMAP_I2C_IP_VERSION_2,
1486         .reset  = &omap_i2c_reset,
1487 };
1488
1489 static struct omap_i2c_dev_attr i2c_dev_attr = {
1490         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1491                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1492 };
1493
1494 /* i2c1 */
1495 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1496         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1497         { .irq = -1 }
1498 };
1499
1500 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1501         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1502         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1503         { .dma_req = -1 }
1504 };
1505
1506 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1507         .name           = "i2c1",
1508         .class          = &omap44xx_i2c_hwmod_class,
1509         .clkdm_name     = "l4_per_clkdm",
1510         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1511         .mpu_irqs       = omap44xx_i2c1_irqs,
1512         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1513         .main_clk       = "i2c1_fck",
1514         .prcm = {
1515                 .omap4 = {
1516                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1517                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1518                         .modulemode   = MODULEMODE_SWCTRL,
1519                 },
1520         },
1521         .dev_attr       = &i2c_dev_attr,
1522 };
1523
1524 /* i2c2 */
1525 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1526         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1527         { .irq = -1 }
1528 };
1529
1530 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1531         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1532         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1533         { .dma_req = -1 }
1534 };
1535
1536 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1537         .name           = "i2c2",
1538         .class          = &omap44xx_i2c_hwmod_class,
1539         .clkdm_name     = "l4_per_clkdm",
1540         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1541         .mpu_irqs       = omap44xx_i2c2_irqs,
1542         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1543         .main_clk       = "i2c2_fck",
1544         .prcm = {
1545                 .omap4 = {
1546                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1547                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1548                         .modulemode   = MODULEMODE_SWCTRL,
1549                 },
1550         },
1551         .dev_attr       = &i2c_dev_attr,
1552 };
1553
1554 /* i2c3 */
1555 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1556         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1557         { .irq = -1 }
1558 };
1559
1560 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1561         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1562         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1563         { .dma_req = -1 }
1564 };
1565
1566 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1567         .name           = "i2c3",
1568         .class          = &omap44xx_i2c_hwmod_class,
1569         .clkdm_name     = "l4_per_clkdm",
1570         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1571         .mpu_irqs       = omap44xx_i2c3_irqs,
1572         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1573         .main_clk       = "i2c3_fck",
1574         .prcm = {
1575                 .omap4 = {
1576                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1577                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1578                         .modulemode   = MODULEMODE_SWCTRL,
1579                 },
1580         },
1581         .dev_attr       = &i2c_dev_attr,
1582 };
1583
1584 /* i2c4 */
1585 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1586         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1587         { .irq = -1 }
1588 };
1589
1590 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1591         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1592         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1593         { .dma_req = -1 }
1594 };
1595
1596 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1597         .name           = "i2c4",
1598         .class          = &omap44xx_i2c_hwmod_class,
1599         .clkdm_name     = "l4_per_clkdm",
1600         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1601         .mpu_irqs       = omap44xx_i2c4_irqs,
1602         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1603         .main_clk       = "i2c4_fck",
1604         .prcm = {
1605                 .omap4 = {
1606                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1607                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1608                         .modulemode   = MODULEMODE_SWCTRL,
1609                 },
1610         },
1611         .dev_attr       = &i2c_dev_attr,
1612 };
1613
1614 /*
1615  * 'ipu' class
1616  * imaging processor unit
1617  */
1618
1619 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1620         .name   = "ipu",
1621 };
1622
1623 /* ipu */
1624 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1625         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1626         { .irq = -1 }
1627 };
1628
1629 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1630         { .name = "cpu0", .rst_shift = 0 },
1631         { .name = "cpu1", .rst_shift = 1 },
1632         { .name = "mmu_cache", .rst_shift = 2 },
1633 };
1634
1635 static struct omap_hwmod omap44xx_ipu_hwmod = {
1636         .name           = "ipu",
1637         .class          = &omap44xx_ipu_hwmod_class,
1638         .clkdm_name     = "ducati_clkdm",
1639         .mpu_irqs       = omap44xx_ipu_irqs,
1640         .rst_lines      = omap44xx_ipu_resets,
1641         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1642         .main_clk       = "ipu_fck",
1643         .prcm = {
1644                 .omap4 = {
1645                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1646                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1648                         .modulemode   = MODULEMODE_HWCTRL,
1649                 },
1650         },
1651 };
1652
1653 /*
1654  * 'iss' class
1655  * external images sensor pixel data processor
1656  */
1657
1658 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1659         .rev_offs       = 0x0000,
1660         .sysc_offs      = 0x0010,
1661         /*
1662          * ISS needs 100 OCP clk cycles delay after a softreset before
1663          * accessing sysconfig again.
1664          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1665          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1666          *
1667          * TODO: Indicate errata when available.
1668          */
1669         .srst_udelay    = 2,
1670         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1671                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1672         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1673                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1674                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1675         .sysc_fields    = &omap_hwmod_sysc_type2,
1676 };
1677
1678 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1679         .name   = "iss",
1680         .sysc   = &omap44xx_iss_sysc,
1681 };
1682
1683 /* iss */
1684 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1685         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1686         { .irq = -1 }
1687 };
1688
1689 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1690         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1691         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1692         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1693         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1694         { .dma_req = -1 }
1695 };
1696
1697 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1698         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1699 };
1700
1701 static struct omap_hwmod omap44xx_iss_hwmod = {
1702         .name           = "iss",
1703         .class          = &omap44xx_iss_hwmod_class,
1704         .clkdm_name     = "iss_clkdm",
1705         .mpu_irqs       = omap44xx_iss_irqs,
1706         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1707         .main_clk       = "iss_fck",
1708         .prcm = {
1709                 .omap4 = {
1710                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1711                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1712                         .modulemode   = MODULEMODE_SWCTRL,
1713                 },
1714         },
1715         .opt_clks       = iss_opt_clks,
1716         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1717 };
1718
1719 /*
1720  * 'iva' class
1721  * multi-standard video encoder/decoder hardware accelerator
1722  */
1723
1724 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1725         .name   = "iva",
1726 };
1727
1728 /* iva */
1729 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1730         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1731         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1732         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1733         { .irq = -1 }
1734 };
1735
1736 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1737         { .name = "seq0", .rst_shift = 0 },
1738         { .name = "seq1", .rst_shift = 1 },
1739         { .name = "logic", .rst_shift = 2 },
1740 };
1741
1742 static struct omap_hwmod omap44xx_iva_hwmod = {
1743         .name           = "iva",
1744         .class          = &omap44xx_iva_hwmod_class,
1745         .clkdm_name     = "ivahd_clkdm",
1746         .mpu_irqs       = omap44xx_iva_irqs,
1747         .rst_lines      = omap44xx_iva_resets,
1748         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1749         .main_clk       = "iva_fck",
1750         .prcm = {
1751                 .omap4 = {
1752                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1753                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1754                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1755                         .modulemode   = MODULEMODE_HWCTRL,
1756                 },
1757         },
1758 };
1759
1760 /*
1761  * 'kbd' class
1762  * keyboard controller
1763  */
1764
1765 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1766         .rev_offs       = 0x0000,
1767         .sysc_offs      = 0x0010,
1768         .syss_offs      = 0x0014,
1769         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1770                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1771                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1772                            SYSS_HAS_RESET_STATUS),
1773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1774         .sysc_fields    = &omap_hwmod_sysc_type1,
1775 };
1776
1777 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1778         .name   = "kbd",
1779         .sysc   = &omap44xx_kbd_sysc,
1780 };
1781
1782 /* kbd */
1783 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1784         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1785         { .irq = -1 }
1786 };
1787
1788 static struct omap_hwmod omap44xx_kbd_hwmod = {
1789         .name           = "kbd",
1790         .class          = &omap44xx_kbd_hwmod_class,
1791         .clkdm_name     = "l4_wkup_clkdm",
1792         .mpu_irqs       = omap44xx_kbd_irqs,
1793         .main_clk       = "kbd_fck",
1794         .prcm = {
1795                 .omap4 = {
1796                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1797                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1798                         .modulemode   = MODULEMODE_SWCTRL,
1799                 },
1800         },
1801 };
1802
1803 /*
1804  * 'mailbox' class
1805  * mailbox module allowing communication between the on-chip processors using a
1806  * queued mailbox-interrupt mechanism.
1807  */
1808
1809 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1810         .rev_offs       = 0x0000,
1811         .sysc_offs      = 0x0010,
1812         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1813                            SYSC_HAS_SOFTRESET),
1814         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1815         .sysc_fields    = &omap_hwmod_sysc_type2,
1816 };
1817
1818 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1819         .name   = "mailbox",
1820         .sysc   = &omap44xx_mailbox_sysc,
1821 };
1822
1823 /* mailbox */
1824 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1825         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1826         { .irq = -1 }
1827 };
1828
1829 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1830         .name           = "mailbox",
1831         .class          = &omap44xx_mailbox_hwmod_class,
1832         .clkdm_name     = "l4_cfg_clkdm",
1833         .mpu_irqs       = omap44xx_mailbox_irqs,
1834         .prcm = {
1835                 .omap4 = {
1836                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1837                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1838                 },
1839         },
1840 };
1841
1842 /*
1843  * 'mcasp' class
1844  * multi-channel audio serial port controller
1845  */
1846
1847 /* The IP is not compliant to type1 / type2 scheme */
1848 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1849         .sidle_shift    = 0,
1850 };
1851
1852 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1853         .sysc_offs      = 0x0004,
1854         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1855         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1856                            SIDLE_SMART_WKUP),
1857         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1858 };
1859
1860 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1861         .name   = "mcasp",
1862         .sysc   = &omap44xx_mcasp_sysc,
1863 };
1864
1865 /* mcasp */
1866 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1867         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1868         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1869         { .irq = -1 }
1870 };
1871
1872 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1873         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1874         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1875         { .dma_req = -1 }
1876 };
1877
1878 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1879         .name           = "mcasp",
1880         .class          = &omap44xx_mcasp_hwmod_class,
1881         .clkdm_name     = "abe_clkdm",
1882         .mpu_irqs       = omap44xx_mcasp_irqs,
1883         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1884         .main_clk       = "mcasp_fck",
1885         .prcm = {
1886                 .omap4 = {
1887                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1888                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1889                         .modulemode   = MODULEMODE_SWCTRL,
1890                 },
1891         },
1892 };
1893
1894 /*
1895  * 'mcbsp' class
1896  * multi channel buffered serial port controller
1897  */
1898
1899 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1900         .sysc_offs      = 0x008c,
1901         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1902                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1903         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1904         .sysc_fields    = &omap_hwmod_sysc_type1,
1905 };
1906
1907 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1908         .name   = "mcbsp",
1909         .sysc   = &omap44xx_mcbsp_sysc,
1910         .rev    = MCBSP_CONFIG_TYPE4,
1911 };
1912
1913 /* mcbsp1 */
1914 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1915         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1916         { .irq = -1 }
1917 };
1918
1919 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1920         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1921         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1922         { .dma_req = -1 }
1923 };
1924
1925 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1926         { .role = "pad_fck", .clk = "pad_clks_ck" },
1927         { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
1928 };
1929
1930 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1931         .name           = "mcbsp1",
1932         .class          = &omap44xx_mcbsp_hwmod_class,
1933         .clkdm_name     = "abe_clkdm",
1934         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1935         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1936         .main_clk       = "mcbsp1_fck",
1937         .prcm = {
1938                 .omap4 = {
1939                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1940                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1941                         .modulemode   = MODULEMODE_SWCTRL,
1942                 },
1943         },
1944         .opt_clks       = mcbsp1_opt_clks,
1945         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1946 };
1947
1948 /* mcbsp2 */
1949 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1950         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1951         { .irq = -1 }
1952 };
1953
1954 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1955         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1956         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1957         { .dma_req = -1 }
1958 };
1959
1960 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1961         { .role = "pad_fck", .clk = "pad_clks_ck" },
1962         { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
1963 };
1964
1965 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1966         .name           = "mcbsp2",
1967         .class          = &omap44xx_mcbsp_hwmod_class,
1968         .clkdm_name     = "abe_clkdm",
1969         .mpu_irqs       = omap44xx_mcbsp2_irqs,
1970         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
1971         .main_clk       = "mcbsp2_fck",
1972         .prcm = {
1973                 .omap4 = {
1974                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1975                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1976                         .modulemode   = MODULEMODE_SWCTRL,
1977                 },
1978         },
1979         .opt_clks       = mcbsp2_opt_clks,
1980         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1981 };
1982
1983 /* mcbsp3 */
1984 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1985         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1986         { .irq = -1 }
1987 };
1988
1989 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1990         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1991         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1992         { .dma_req = -1 }
1993 };
1994
1995 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1996         { .role = "pad_fck", .clk = "pad_clks_ck" },
1997         { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
1998 };
1999
2000 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2001         .name           = "mcbsp3",
2002         .class          = &omap44xx_mcbsp_hwmod_class,
2003         .clkdm_name     = "abe_clkdm",
2004         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2005         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2006         .main_clk       = "mcbsp3_fck",
2007         .prcm = {
2008                 .omap4 = {
2009                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2010                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2011                         .modulemode   = MODULEMODE_SWCTRL,
2012                 },
2013         },
2014         .opt_clks       = mcbsp3_opt_clks,
2015         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2016 };
2017
2018 /* mcbsp4 */
2019 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2020         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2021         { .irq = -1 }
2022 };
2023
2024 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2025         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2026         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2027         { .dma_req = -1 }
2028 };
2029
2030 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2031         { .role = "pad_fck", .clk = "pad_clks_ck" },
2032         { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
2033 };
2034
2035 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2036         .name           = "mcbsp4",
2037         .class          = &omap44xx_mcbsp_hwmod_class,
2038         .clkdm_name     = "l4_per_clkdm",
2039         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2040         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2041         .main_clk       = "mcbsp4_fck",
2042         .prcm = {
2043                 .omap4 = {
2044                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2045                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2046                         .modulemode   = MODULEMODE_SWCTRL,
2047                 },
2048         },
2049         .opt_clks       = mcbsp4_opt_clks,
2050         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2051 };
2052
2053 /*
2054  * 'mcpdm' class
2055  * multi channel pdm controller (proprietary interface with phoenix power
2056  * ic)
2057  */
2058
2059 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2060         .rev_offs       = 0x0000,
2061         .sysc_offs      = 0x0010,
2062         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2063                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2064         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2065                            SIDLE_SMART_WKUP),
2066         .sysc_fields    = &omap_hwmod_sysc_type2,
2067 };
2068
2069 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2070         .name   = "mcpdm",
2071         .sysc   = &omap44xx_mcpdm_sysc,
2072 };
2073
2074 /* mcpdm */
2075 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2076         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2077         { .irq = -1 }
2078 };
2079
2080 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2081         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2082         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2083         { .dma_req = -1 }
2084 };
2085
2086 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2087         .name           = "mcpdm",
2088         .class          = &omap44xx_mcpdm_hwmod_class,
2089         .clkdm_name     = "abe_clkdm",
2090         .mpu_irqs       = omap44xx_mcpdm_irqs,
2091         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2092         .main_clk       = "mcpdm_fck",
2093         .prcm = {
2094                 .omap4 = {
2095                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2096                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2097                         .modulemode   = MODULEMODE_SWCTRL,
2098                 },
2099         },
2100 };
2101
2102 /*
2103  * 'mcspi' class
2104  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2105  * bus
2106  */
2107
2108 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2109         .rev_offs       = 0x0000,
2110         .sysc_offs      = 0x0010,
2111         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2112                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2113         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2114                            SIDLE_SMART_WKUP),
2115         .sysc_fields    = &omap_hwmod_sysc_type2,
2116 };
2117
2118 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2119         .name   = "mcspi",
2120         .sysc   = &omap44xx_mcspi_sysc,
2121         .rev    = OMAP4_MCSPI_REV,
2122 };
2123
2124 /* mcspi1 */
2125 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2126         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2127         { .irq = -1 }
2128 };
2129
2130 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2131         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2132         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2133         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2134         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2135         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2136         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2137         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2138         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2139         { .dma_req = -1 }
2140 };
2141
2142 /* mcspi1 dev_attr */
2143 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2144         .num_chipselect = 4,
2145 };
2146
2147 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2148         .name           = "mcspi1",
2149         .class          = &omap44xx_mcspi_hwmod_class,
2150         .clkdm_name     = "l4_per_clkdm",
2151         .mpu_irqs       = omap44xx_mcspi1_irqs,
2152         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2153         .main_clk       = "mcspi1_fck",
2154         .prcm = {
2155                 .omap4 = {
2156                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2157                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2158                         .modulemode   = MODULEMODE_SWCTRL,
2159                 },
2160         },
2161         .dev_attr       = &mcspi1_dev_attr,
2162 };
2163
2164 /* mcspi2 */
2165 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2166         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2167         { .irq = -1 }
2168 };
2169
2170 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2171         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2172         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2173         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2174         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2175         { .dma_req = -1 }
2176 };
2177
2178 /* mcspi2 dev_attr */
2179 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2180         .num_chipselect = 2,
2181 };
2182
2183 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2184         .name           = "mcspi2",
2185         .class          = &omap44xx_mcspi_hwmod_class,
2186         .clkdm_name     = "l4_per_clkdm",
2187         .mpu_irqs       = omap44xx_mcspi2_irqs,
2188         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2189         .main_clk       = "mcspi2_fck",
2190         .prcm = {
2191                 .omap4 = {
2192                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2193                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2194                         .modulemode   = MODULEMODE_SWCTRL,
2195                 },
2196         },
2197         .dev_attr       = &mcspi2_dev_attr,
2198 };
2199
2200 /* mcspi3 */
2201 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2202         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2203         { .irq = -1 }
2204 };
2205
2206 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2207         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2208         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2209         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2210         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2211         { .dma_req = -1 }
2212 };
2213
2214 /* mcspi3 dev_attr */
2215 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2216         .num_chipselect = 2,
2217 };
2218
2219 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2220         .name           = "mcspi3",
2221         .class          = &omap44xx_mcspi_hwmod_class,
2222         .clkdm_name     = "l4_per_clkdm",
2223         .mpu_irqs       = omap44xx_mcspi3_irqs,
2224         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2225         .main_clk       = "mcspi3_fck",
2226         .prcm = {
2227                 .omap4 = {
2228                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2229                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2230                         .modulemode   = MODULEMODE_SWCTRL,
2231                 },
2232         },
2233         .dev_attr       = &mcspi3_dev_attr,
2234 };
2235
2236 /* mcspi4 */
2237 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2238         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2239         { .irq = -1 }
2240 };
2241
2242 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2243         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2244         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2245         { .dma_req = -1 }
2246 };
2247
2248 /* mcspi4 dev_attr */
2249 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2250         .num_chipselect = 1,
2251 };
2252
2253 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2254         .name           = "mcspi4",
2255         .class          = &omap44xx_mcspi_hwmod_class,
2256         .clkdm_name     = "l4_per_clkdm",
2257         .mpu_irqs       = omap44xx_mcspi4_irqs,
2258         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2259         .main_clk       = "mcspi4_fck",
2260         .prcm = {
2261                 .omap4 = {
2262                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2263                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2264                         .modulemode   = MODULEMODE_SWCTRL,
2265                 },
2266         },
2267         .dev_attr       = &mcspi4_dev_attr,
2268 };
2269
2270 /*
2271  * 'mmc' class
2272  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2273  */
2274
2275 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2276         .rev_offs       = 0x0000,
2277         .sysc_offs      = 0x0010,
2278         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2279                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2280                            SYSC_HAS_SOFTRESET),
2281         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2282                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2283                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2284         .sysc_fields    = &omap_hwmod_sysc_type2,
2285 };
2286
2287 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2288         .name   = "mmc",
2289         .sysc   = &omap44xx_mmc_sysc,
2290 };
2291
2292 /* mmc1 */
2293 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2294         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2295         { .irq = -1 }
2296 };
2297
2298 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2299         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2300         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2301         { .dma_req = -1 }
2302 };
2303
2304 /* mmc1 dev_attr */
2305 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2306         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2307 };
2308
2309 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2310         .name           = "mmc1",
2311         .class          = &omap44xx_mmc_hwmod_class,
2312         .clkdm_name     = "l3_init_clkdm",
2313         .mpu_irqs       = omap44xx_mmc1_irqs,
2314         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2315         .main_clk       = "mmc1_fck",
2316         .prcm = {
2317                 .omap4 = {
2318                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2319                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2320                         .modulemode   = MODULEMODE_SWCTRL,
2321                 },
2322         },
2323         .dev_attr       = &mmc1_dev_attr,
2324 };
2325
2326 /* mmc2 */
2327 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2328         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2329         { .irq = -1 }
2330 };
2331
2332 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2333         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2334         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2335         { .dma_req = -1 }
2336 };
2337
2338 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2339         .name           = "mmc2",
2340         .class          = &omap44xx_mmc_hwmod_class,
2341         .clkdm_name     = "l3_init_clkdm",
2342         .mpu_irqs       = omap44xx_mmc2_irqs,
2343         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2344         .main_clk       = "mmc2_fck",
2345         .prcm = {
2346                 .omap4 = {
2347                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2348                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2349                         .modulemode   = MODULEMODE_SWCTRL,
2350                 },
2351         },
2352 };
2353
2354 /* mmc3 */
2355 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2356         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2357         { .irq = -1 }
2358 };
2359
2360 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2361         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2362         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2363         { .dma_req = -1 }
2364 };
2365
2366 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2367         .name           = "mmc3",
2368         .class          = &omap44xx_mmc_hwmod_class,
2369         .clkdm_name     = "l4_per_clkdm",
2370         .mpu_irqs       = omap44xx_mmc3_irqs,
2371         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2372         .main_clk       = "mmc3_fck",
2373         .prcm = {
2374                 .omap4 = {
2375                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2376                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2377                         .modulemode   = MODULEMODE_SWCTRL,
2378                 },
2379         },
2380 };
2381
2382 /* mmc4 */
2383 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2384         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2385         { .irq = -1 }
2386 };
2387
2388 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2389         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2390         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2391         { .dma_req = -1 }
2392 };
2393
2394 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2395         .name           = "mmc4",
2396         .class          = &omap44xx_mmc_hwmod_class,
2397         .clkdm_name     = "l4_per_clkdm",
2398         .mpu_irqs       = omap44xx_mmc4_irqs,
2399         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2400         .main_clk       = "mmc4_fck",
2401         .prcm = {
2402                 .omap4 = {
2403                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2404                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2405                         .modulemode   = MODULEMODE_SWCTRL,
2406                 },
2407         },
2408 };
2409
2410 /* mmc5 */
2411 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2412         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2413         { .irq = -1 }
2414 };
2415
2416 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2417         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2418         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2419         { .dma_req = -1 }
2420 };
2421
2422 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2423         .name           = "mmc5",
2424         .class          = &omap44xx_mmc_hwmod_class,
2425         .clkdm_name     = "l4_per_clkdm",
2426         .mpu_irqs       = omap44xx_mmc5_irqs,
2427         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2428         .main_clk       = "mmc5_fck",
2429         .prcm = {
2430                 .omap4 = {
2431                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2432                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2433                         .modulemode   = MODULEMODE_SWCTRL,
2434                 },
2435         },
2436 };
2437
2438 /*
2439  * 'mpu' class
2440  * mpu sub-system
2441  */
2442
2443 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2444         .name   = "mpu",
2445 };
2446
2447 /* mpu */
2448 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2449         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2450         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2451         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2452         { .irq = -1 }
2453 };
2454
2455 static struct omap_hwmod omap44xx_mpu_hwmod = {
2456         .name           = "mpu",
2457         .class          = &omap44xx_mpu_hwmod_class,
2458         .clkdm_name     = "mpuss_clkdm",
2459         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2460         .mpu_irqs       = omap44xx_mpu_irqs,
2461         .main_clk       = "dpll_mpu_m2_ck",
2462         .prcm = {
2463                 .omap4 = {
2464                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2465                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2466                 },
2467         },
2468 };
2469
2470 /*
2471  * 'ocmc_ram' class
2472  * top-level core on-chip ram
2473  */
2474
2475 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2476         .name   = "ocmc_ram",
2477 };
2478
2479 /* ocmc_ram */
2480 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2481         .name           = "ocmc_ram",
2482         .class          = &omap44xx_ocmc_ram_hwmod_class,
2483         .clkdm_name     = "l3_2_clkdm",
2484         .prcm = {
2485                 .omap4 = {
2486                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2487                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2488                 },
2489         },
2490 };
2491
2492 /*
2493  * 'ocp2scp' class
2494  * bridge to transform ocp interface protocol to scp (serial control port)
2495  * protocol
2496  */
2497
2498 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2499         .name   = "ocp2scp",
2500 };
2501
2502 /* ocp2scp_usb_phy */
2503 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2504         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2505 };
2506
2507 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2508         .name           = "ocp2scp_usb_phy",
2509         .class          = &omap44xx_ocp2scp_hwmod_class,
2510         .clkdm_name     = "l3_init_clkdm",
2511         .prcm = {
2512                 .omap4 = {
2513                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2514                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2515                         .modulemode   = MODULEMODE_HWCTRL,
2516                 },
2517         },
2518         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2519         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2520 };
2521
2522 /*
2523  * 'prcm' class
2524  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2525  * + clock manager 1 (in always on power domain) + local prm in mpu
2526  */
2527
2528 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2529         .name   = "prcm",
2530 };
2531
2532 /* prcm_mpu */
2533 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2534         .name           = "prcm_mpu",
2535         .class          = &omap44xx_prcm_hwmod_class,
2536         .clkdm_name     = "l4_wkup_clkdm",
2537 };
2538
2539 /* cm_core_aon */
2540 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2541         .name           = "cm_core_aon",
2542         .class          = &omap44xx_prcm_hwmod_class,
2543         .clkdm_name     = "cm_clkdm",
2544 };
2545
2546 /* cm_core */
2547 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2548         .name           = "cm_core",
2549         .class          = &omap44xx_prcm_hwmod_class,
2550         .clkdm_name     = "cm_clkdm",
2551 };
2552
2553 /* prm */
2554 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2555         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2556         { .irq = -1 }
2557 };
2558
2559 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2560         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2561         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2562 };
2563
2564 static struct omap_hwmod omap44xx_prm_hwmod = {
2565         .name           = "prm",
2566         .class          = &omap44xx_prcm_hwmod_class,
2567         .clkdm_name     = "prm_clkdm",
2568         .mpu_irqs       = omap44xx_prm_irqs,
2569         .rst_lines      = omap44xx_prm_resets,
2570         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2571 };
2572
2573 /*
2574  * 'scrm' class
2575  * system clock and reset manager
2576  */
2577
2578 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2579         .name   = "scrm",
2580 };
2581
2582 /* scrm */
2583 static struct omap_hwmod omap44xx_scrm_hwmod = {
2584         .name           = "scrm",
2585         .class          = &omap44xx_scrm_hwmod_class,
2586         .clkdm_name     = "l4_wkup_clkdm",
2587 };
2588
2589 /*
2590  * 'sl2if' class
2591  * shared level 2 memory interface
2592  */
2593
2594 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2595         .name   = "sl2if",
2596 };
2597
2598 /* sl2if */
2599 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2600         .name           = "sl2if",
2601         .class          = &omap44xx_sl2if_hwmod_class,
2602         .clkdm_name     = "ivahd_clkdm",
2603         .prcm = {
2604                 .omap4 = {
2605                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2606                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2607                         .modulemode   = MODULEMODE_HWCTRL,
2608                 },
2609         },
2610 };
2611
2612 /*
2613  * 'slimbus' class
2614  * bidirectional, multi-drop, multi-channel two-line serial interface between
2615  * the device and external components
2616  */
2617
2618 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2619         .rev_offs       = 0x0000,
2620         .sysc_offs      = 0x0010,
2621         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2622                            SYSC_HAS_SOFTRESET),
2623         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2624                            SIDLE_SMART_WKUP),
2625         .sysc_fields    = &omap_hwmod_sysc_type2,
2626 };
2627
2628 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2629         .name   = "slimbus",
2630         .sysc   = &omap44xx_slimbus_sysc,
2631 };
2632
2633 /* slimbus1 */
2634 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2635         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2636         { .irq = -1 }
2637 };
2638
2639 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2640         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2641         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2642         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2643         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2644         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2645         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2646         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2647         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2648         { .dma_req = -1 }
2649 };
2650
2651 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2652         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2653         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2654         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2655         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2656 };
2657
2658 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2659         .name           = "slimbus1",
2660         .class          = &omap44xx_slimbus_hwmod_class,
2661         .clkdm_name     = "abe_clkdm",
2662         .mpu_irqs       = omap44xx_slimbus1_irqs,
2663         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2664         .prcm = {
2665                 .omap4 = {
2666                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2667                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2668                         .modulemode   = MODULEMODE_SWCTRL,
2669                 },
2670         },
2671         .opt_clks       = slimbus1_opt_clks,
2672         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2673 };
2674
2675 /* slimbus2 */
2676 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2677         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2678         { .irq = -1 }
2679 };
2680
2681 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2682         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2683         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2684         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2685         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2686         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2687         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2688         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2689         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2690         { .dma_req = -1 }
2691 };
2692
2693 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2694         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2695         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2696         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2697 };
2698
2699 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2700         .name           = "slimbus2",
2701         .class          = &omap44xx_slimbus_hwmod_class,
2702         .clkdm_name     = "l4_per_clkdm",
2703         .mpu_irqs       = omap44xx_slimbus2_irqs,
2704         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2705         .prcm = {
2706                 .omap4 = {
2707                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2708                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2709                         .modulemode   = MODULEMODE_SWCTRL,
2710                 },
2711         },
2712         .opt_clks       = slimbus2_opt_clks,
2713         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2714 };
2715
2716 /*
2717  * 'smartreflex' class
2718  * smartreflex module (monitor silicon performance and outputs a measure of
2719  * performance error)
2720  */
2721
2722 /* The IP is not compliant to type1 / type2 scheme */
2723 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2724         .sidle_shift    = 24,
2725         .enwkup_shift   = 26,
2726 };
2727
2728 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2729         .sysc_offs      = 0x0038,
2730         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2731         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2732                            SIDLE_SMART_WKUP),
2733         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2734 };
2735
2736 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2737         .name   = "smartreflex",
2738         .sysc   = &omap44xx_smartreflex_sysc,
2739         .rev    = 2,
2740 };
2741
2742 /* smartreflex_core */
2743 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2744         .sensor_voltdm_name   = "core",
2745 };
2746
2747 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2748         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2749         { .irq = -1 }
2750 };
2751
2752 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2753         .name           = "smartreflex_core",
2754         .class          = &omap44xx_smartreflex_hwmod_class,
2755         .clkdm_name     = "l4_ao_clkdm",
2756         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2757
2758         .main_clk       = "smartreflex_core_fck",
2759         .prcm = {
2760                 .omap4 = {
2761                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2762                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2763                         .modulemode   = MODULEMODE_SWCTRL,
2764                 },
2765         },
2766         .dev_attr       = &smartreflex_core_dev_attr,
2767 };
2768
2769 /* smartreflex_iva */
2770 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2771         .sensor_voltdm_name     = "iva",
2772 };
2773
2774 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2775         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2776         { .irq = -1 }
2777 };
2778
2779 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2780         .name           = "smartreflex_iva",
2781         .class          = &omap44xx_smartreflex_hwmod_class,
2782         .clkdm_name     = "l4_ao_clkdm",
2783         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2784         .main_clk       = "smartreflex_iva_fck",
2785         .prcm = {
2786                 .omap4 = {
2787                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2788                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2789                         .modulemode   = MODULEMODE_SWCTRL,
2790                 },
2791         },
2792         .dev_attr       = &smartreflex_iva_dev_attr,
2793 };
2794
2795 /* smartreflex_mpu */
2796 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2797         .sensor_voltdm_name     = "mpu",
2798 };
2799
2800 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2801         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2802         { .irq = -1 }
2803 };
2804
2805 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2806         .name           = "smartreflex_mpu",
2807         .class          = &omap44xx_smartreflex_hwmod_class,
2808         .clkdm_name     = "l4_ao_clkdm",
2809         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2810         .main_clk       = "smartreflex_mpu_fck",
2811         .prcm = {
2812                 .omap4 = {
2813                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2814                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2815                         .modulemode   = MODULEMODE_SWCTRL,
2816                 },
2817         },
2818         .dev_attr       = &smartreflex_mpu_dev_attr,
2819 };
2820
2821 /*
2822  * 'spinlock' class
2823  * spinlock provides hardware assistance for synchronizing the processes
2824  * running on multiple processors
2825  */
2826
2827 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2828         .rev_offs       = 0x0000,
2829         .sysc_offs      = 0x0010,
2830         .syss_offs      = 0x0014,
2831         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2832                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2833                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2834         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2835                            SIDLE_SMART_WKUP),
2836         .sysc_fields    = &omap_hwmod_sysc_type1,
2837 };
2838
2839 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2840         .name   = "spinlock",
2841         .sysc   = &omap44xx_spinlock_sysc,
2842 };
2843
2844 /* spinlock */
2845 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2846         .name           = "spinlock",
2847         .class          = &omap44xx_spinlock_hwmod_class,
2848         .clkdm_name     = "l4_cfg_clkdm",
2849         .prcm = {
2850                 .omap4 = {
2851                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2852                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2853                 },
2854         },
2855 };
2856
2857 /*
2858  * 'timer' class
2859  * general purpose timer module with accurate 1ms tick
2860  * This class contains several variants: ['timer_1ms', 'timer']
2861  */
2862
2863 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2864         .rev_offs       = 0x0000,
2865         .sysc_offs      = 0x0010,
2866         .syss_offs      = 0x0014,
2867         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2868                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2869                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2870                            SYSS_HAS_RESET_STATUS),
2871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2872         .sysc_fields    = &omap_hwmod_sysc_type1,
2873 };
2874
2875 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2876         .name   = "timer",
2877         .sysc   = &omap44xx_timer_1ms_sysc,
2878 };
2879
2880 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2881         .rev_offs       = 0x0000,
2882         .sysc_offs      = 0x0010,
2883         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2884                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2885         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2886                            SIDLE_SMART_WKUP),
2887         .sysc_fields    = &omap_hwmod_sysc_type2,
2888 };
2889
2890 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2891         .name   = "timer",
2892         .sysc   = &omap44xx_timer_sysc,
2893 };
2894
2895 /* always-on timers dev attribute */
2896 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2897         .timer_capability       = OMAP_TIMER_ALWON,
2898 };
2899
2900 /* pwm timers dev attribute */
2901 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2902         .timer_capability       = OMAP_TIMER_HAS_PWM,
2903 };
2904
2905 /* timer1 */
2906 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2907         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2908         { .irq = -1 }
2909 };
2910
2911 static struct omap_hwmod omap44xx_timer1_hwmod = {
2912         .name           = "timer1",
2913         .class          = &omap44xx_timer_1ms_hwmod_class,
2914         .clkdm_name     = "l4_wkup_clkdm",
2915         .mpu_irqs       = omap44xx_timer1_irqs,
2916         .main_clk       = "timer1_fck",
2917         .prcm = {
2918                 .omap4 = {
2919                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2920                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2921                         .modulemode   = MODULEMODE_SWCTRL,
2922                 },
2923         },
2924         .dev_attr       = &capability_alwon_dev_attr,
2925 };
2926
2927 /* timer2 */
2928 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2929         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2930         { .irq = -1 }
2931 };
2932
2933 static struct omap_hwmod omap44xx_timer2_hwmod = {
2934         .name           = "timer2",
2935         .class          = &omap44xx_timer_1ms_hwmod_class,
2936         .clkdm_name     = "l4_per_clkdm",
2937         .mpu_irqs       = omap44xx_timer2_irqs,
2938         .main_clk       = "timer2_fck",
2939         .prcm = {
2940                 .omap4 = {
2941                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2942                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2943                         .modulemode   = MODULEMODE_SWCTRL,
2944                 },
2945         },
2946 };
2947
2948 /* timer3 */
2949 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2950         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2951         { .irq = -1 }
2952 };
2953
2954 static struct omap_hwmod omap44xx_timer3_hwmod = {
2955         .name           = "timer3",
2956         .class          = &omap44xx_timer_hwmod_class,
2957         .clkdm_name     = "l4_per_clkdm",
2958         .mpu_irqs       = omap44xx_timer3_irqs,
2959         .main_clk       = "timer3_fck",
2960         .prcm = {
2961                 .omap4 = {
2962                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2963                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2964                         .modulemode   = MODULEMODE_SWCTRL,
2965                 },
2966         },
2967 };
2968
2969 /* timer4 */
2970 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2971         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2972         { .irq = -1 }
2973 };
2974
2975 static struct omap_hwmod omap44xx_timer4_hwmod = {
2976         .name           = "timer4",
2977         .class          = &omap44xx_timer_hwmod_class,
2978         .clkdm_name     = "l4_per_clkdm",
2979         .mpu_irqs       = omap44xx_timer4_irqs,
2980         .main_clk       = "timer4_fck",
2981         .prcm = {
2982                 .omap4 = {
2983                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2984                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2985                         .modulemode   = MODULEMODE_SWCTRL,
2986                 },
2987         },
2988 };
2989
2990 /* timer5 */
2991 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2992         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2993         { .irq = -1 }
2994 };
2995
2996 static struct omap_hwmod omap44xx_timer5_hwmod = {
2997         .name           = "timer5",
2998         .class          = &omap44xx_timer_hwmod_class,
2999         .clkdm_name     = "abe_clkdm",
3000         .mpu_irqs       = omap44xx_timer5_irqs,
3001         .main_clk       = "timer5_fck",
3002         .prcm = {
3003                 .omap4 = {
3004                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3005                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3006                         .modulemode   = MODULEMODE_SWCTRL,
3007                 },
3008         },
3009 };
3010
3011 /* timer6 */
3012 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3013         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3014         { .irq = -1 }
3015 };
3016
3017 static struct omap_hwmod omap44xx_timer6_hwmod = {
3018         .name           = "timer6",
3019         .class          = &omap44xx_timer_hwmod_class,
3020         .clkdm_name     = "abe_clkdm",
3021         .mpu_irqs       = omap44xx_timer6_irqs,
3022
3023         .main_clk       = "timer6_fck",
3024         .prcm = {
3025                 .omap4 = {
3026                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3027                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3028                         .modulemode   = MODULEMODE_SWCTRL,
3029                 },
3030         },
3031 };
3032
3033 /* timer7 */
3034 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3035         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3036         { .irq = -1 }
3037 };
3038
3039 static struct omap_hwmod omap44xx_timer7_hwmod = {
3040         .name           = "timer7",
3041         .class          = &omap44xx_timer_hwmod_class,
3042         .clkdm_name     = "abe_clkdm",
3043         .mpu_irqs       = omap44xx_timer7_irqs,
3044         .main_clk       = "timer7_fck",
3045         .prcm = {
3046                 .omap4 = {
3047                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3048                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3049                         .modulemode   = MODULEMODE_SWCTRL,
3050                 },
3051         },
3052 };
3053
3054 /* timer8 */
3055 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3056         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3057         { .irq = -1 }
3058 };
3059
3060 static struct omap_hwmod omap44xx_timer8_hwmod = {
3061         .name           = "timer8",
3062         .class          = &omap44xx_timer_hwmod_class,
3063         .clkdm_name     = "abe_clkdm",
3064         .mpu_irqs       = omap44xx_timer8_irqs,
3065         .main_clk       = "timer8_fck",
3066         .prcm = {
3067                 .omap4 = {
3068                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3069                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3070                         .modulemode   = MODULEMODE_SWCTRL,
3071                 },
3072         },
3073         .dev_attr       = &capability_pwm_dev_attr,
3074 };
3075
3076 /* timer9 */
3077 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3078         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3079         { .irq = -1 }
3080 };
3081
3082 static struct omap_hwmod omap44xx_timer9_hwmod = {
3083         .name           = "timer9",
3084         .class          = &omap44xx_timer_hwmod_class,
3085         .clkdm_name     = "l4_per_clkdm",
3086         .mpu_irqs       = omap44xx_timer9_irqs,
3087         .main_clk       = "timer9_fck",
3088         .prcm = {
3089                 .omap4 = {
3090                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3091                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3092                         .modulemode   = MODULEMODE_SWCTRL,
3093                 },
3094         },
3095         .dev_attr       = &capability_pwm_dev_attr,
3096 };
3097
3098 /* timer10 */
3099 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3100         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3101         { .irq = -1 }
3102 };
3103
3104 static struct omap_hwmod omap44xx_timer10_hwmod = {
3105         .name           = "timer10",
3106         .class          = &omap44xx_timer_1ms_hwmod_class,
3107         .clkdm_name     = "l4_per_clkdm",
3108         .mpu_irqs       = omap44xx_timer10_irqs,
3109         .main_clk       = "timer10_fck",
3110         .prcm = {
3111                 .omap4 = {
3112                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3113                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3114                         .modulemode   = MODULEMODE_SWCTRL,
3115                 },
3116         },
3117         .dev_attr       = &capability_pwm_dev_attr,
3118 };
3119
3120 /* timer11 */
3121 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3122         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3123         { .irq = -1 }
3124 };
3125
3126 static struct omap_hwmod omap44xx_timer11_hwmod = {
3127         .name           = "timer11",
3128         .class          = &omap44xx_timer_hwmod_class,
3129         .clkdm_name     = "l4_per_clkdm",
3130         .mpu_irqs       = omap44xx_timer11_irqs,
3131         .main_clk       = "timer11_fck",
3132         .prcm = {
3133                 .omap4 = {
3134                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3135                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3136                         .modulemode   = MODULEMODE_SWCTRL,
3137                 },
3138         },
3139         .dev_attr       = &capability_pwm_dev_attr,
3140 };
3141
3142 /*
3143  * 'uart' class
3144  * universal asynchronous receiver/transmitter (uart)
3145  */
3146
3147 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3148         .rev_offs       = 0x0050,
3149         .sysc_offs      = 0x0054,
3150         .syss_offs      = 0x0058,
3151         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3152                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3153                            SYSS_HAS_RESET_STATUS),
3154         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3155                            SIDLE_SMART_WKUP),
3156         .sysc_fields    = &omap_hwmod_sysc_type1,
3157 };
3158
3159 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3160         .name   = "uart",
3161         .sysc   = &omap44xx_uart_sysc,
3162 };
3163
3164 /* uart1 */
3165 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3166         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3167         { .irq = -1 }
3168 };
3169
3170 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3171         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3172         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3173         { .dma_req = -1 }
3174 };
3175
3176 static struct omap_hwmod omap44xx_uart1_hwmod = {
3177         .name           = "uart1",
3178         .class          = &omap44xx_uart_hwmod_class,
3179         .clkdm_name     = "l4_per_clkdm",
3180         .mpu_irqs       = omap44xx_uart1_irqs,
3181         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3182         .main_clk       = "uart1_fck",
3183         .prcm = {
3184                 .omap4 = {
3185                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3186                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3187                         .modulemode   = MODULEMODE_SWCTRL,
3188                 },
3189         },
3190 };
3191
3192 /* uart2 */
3193 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3194         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3195         { .irq = -1 }
3196 };
3197
3198 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3199         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3200         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3201         { .dma_req = -1 }
3202 };
3203
3204 static struct omap_hwmod omap44xx_uart2_hwmod = {
3205         .name           = "uart2",
3206         .class          = &omap44xx_uart_hwmod_class,
3207         .clkdm_name     = "l4_per_clkdm",
3208         .mpu_irqs       = omap44xx_uart2_irqs,
3209         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3210         .main_clk       = "uart2_fck",
3211         .prcm = {
3212                 .omap4 = {
3213                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3214                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3215                         .modulemode   = MODULEMODE_SWCTRL,
3216                 },
3217         },
3218 };
3219
3220 /* uart3 */
3221 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3222         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3223         { .irq = -1 }
3224 };
3225
3226 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3227         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3228         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3229         { .dma_req = -1 }
3230 };
3231
3232 static struct omap_hwmod omap44xx_uart3_hwmod = {
3233         .name           = "uart3",
3234         .class          = &omap44xx_uart_hwmod_class,
3235         .clkdm_name     = "l4_per_clkdm",
3236         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3237         .mpu_irqs       = omap44xx_uart3_irqs,
3238         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3239         .main_clk       = "uart3_fck",
3240         .prcm = {
3241                 .omap4 = {
3242                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3243                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3244                         .modulemode   = MODULEMODE_SWCTRL,
3245                 },
3246         },
3247 };
3248
3249 /* uart4 */
3250 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3251         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3252         { .irq = -1 }
3253 };
3254
3255 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3256         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3257         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3258         { .dma_req = -1 }
3259 };
3260
3261 static struct omap_hwmod omap44xx_uart4_hwmod = {
3262         .name           = "uart4",
3263         .class          = &omap44xx_uart_hwmod_class,
3264         .clkdm_name     = "l4_per_clkdm",
3265         .mpu_irqs       = omap44xx_uart4_irqs,
3266         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3267         .main_clk       = "uart4_fck",
3268         .prcm = {
3269                 .omap4 = {
3270                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3271                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3272                         .modulemode   = MODULEMODE_SWCTRL,
3273                 },
3274         },
3275 };
3276
3277 /*
3278  * 'usb_host_fs' class
3279  * full-speed usb host controller
3280  */
3281
3282 /* The IP is not compliant to type1 / type2 scheme */
3283 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3284         .midle_shift    = 4,
3285         .sidle_shift    = 2,
3286         .srst_shift     = 1,
3287 };
3288
3289 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3290         .rev_offs       = 0x0000,
3291         .sysc_offs      = 0x0210,
3292         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3293                            SYSC_HAS_SOFTRESET),
3294         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3295                            SIDLE_SMART_WKUP),
3296         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3297 };
3298
3299 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3300         .name   = "usb_host_fs",
3301         .sysc   = &omap44xx_usb_host_fs_sysc,
3302 };
3303
3304 /* usb_host_fs */
3305 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3306         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3307         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3308         { .irq = -1 }
3309 };
3310
3311 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3312         .name           = "usb_host_fs",
3313         .class          = &omap44xx_usb_host_fs_hwmod_class,
3314         .clkdm_name     = "l3_init_clkdm",
3315         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3316         .main_clk       = "usb_host_fs_fck",
3317         .prcm = {
3318                 .omap4 = {
3319                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3320                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3321                         .modulemode   = MODULEMODE_SWCTRL,
3322                 },
3323         },
3324 };
3325
3326 /*
3327  * 'usb_host_hs' class
3328  * high-speed multi-port usb host controller
3329  */
3330
3331 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3332         .rev_offs       = 0x0000,
3333         .sysc_offs      = 0x0010,
3334         .syss_offs      = 0x0014,
3335         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3336                            SYSC_HAS_SOFTRESET),
3337         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3338                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3339                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3340         .sysc_fields    = &omap_hwmod_sysc_type2,
3341 };
3342
3343 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3344         .name   = "usb_host_hs",
3345         .sysc   = &omap44xx_usb_host_hs_sysc,
3346 };
3347
3348 /* usb_host_hs */
3349 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3350         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3351         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3352         { .irq = -1 }
3353 };
3354
3355 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3356         .name           = "usb_host_hs",
3357         .class          = &omap44xx_usb_host_hs_hwmod_class,
3358         .clkdm_name     = "l3_init_clkdm",
3359         .main_clk       = "usb_host_hs_fck",
3360         .prcm = {
3361                 .omap4 = {
3362                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3363                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3364                         .modulemode   = MODULEMODE_SWCTRL,
3365                 },
3366         },
3367         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3368
3369         /*
3370          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3371          * id: i660
3372          *
3373          * Description:
3374          * In the following configuration :
3375          * - USBHOST module is set to smart-idle mode
3376          * - PRCM asserts idle_req to the USBHOST module ( This typically
3377          *   happens when the system is going to a low power mode : all ports
3378          *   have been suspended, the master part of the USBHOST module has
3379          *   entered the standby state, and SW has cut the functional clocks)
3380          * - an USBHOST interrupt occurs before the module is able to answer
3381          *   idle_ack, typically a remote wakeup IRQ.
3382          * Then the USB HOST module will enter a deadlock situation where it
3383          * is no more accessible nor functional.
3384          *
3385          * Workaround:
3386          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3387          */
3388
3389         /*
3390          * Errata: USB host EHCI may stall when entering smart-standby mode
3391          * Id: i571
3392          *
3393          * Description:
3394          * When the USBHOST module is set to smart-standby mode, and when it is
3395          * ready to enter the standby state (i.e. all ports are suspended and
3396          * all attached devices are in suspend mode), then it can wrongly assert
3397          * the Mstandby signal too early while there are still some residual OCP
3398          * transactions ongoing. If this condition occurs, the internal state
3399          * machine may go to an undefined state and the USB link may be stuck
3400          * upon the next resume.
3401          *
3402          * Workaround:
3403          * Don't use smart standby; use only force standby,
3404          * hence HWMOD_SWSUP_MSTANDBY
3405          */
3406
3407         /*
3408          * During system boot; If the hwmod framework resets the module
3409          * the module will have smart idle settings; which can lead to deadlock
3410          * (above Errata Id:i660); so, dont reset the module during boot;
3411          * Use HWMOD_INIT_NO_RESET.
3412          */
3413
3414         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3415                           HWMOD_INIT_NO_RESET,
3416 };
3417
3418 /*
3419  * 'usb_otg_hs' class
3420  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3421  */
3422
3423 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3424         .rev_offs       = 0x0400,
3425         .sysc_offs      = 0x0404,
3426         .syss_offs      = 0x0408,
3427         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3428                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3429                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3430         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3431                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3432                            MSTANDBY_SMART),
3433         .sysc_fields    = &omap_hwmod_sysc_type1,
3434 };
3435
3436 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3437         .name   = "usb_otg_hs",
3438         .sysc   = &omap44xx_usb_otg_hs_sysc,
3439 };
3440
3441 /* usb_otg_hs */
3442 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3443         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3444         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3445         { .irq = -1 }
3446 };
3447
3448 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3449         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3450 };
3451
3452 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3453         .name           = "usb_otg_hs",
3454         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3455         .clkdm_name     = "l3_init_clkdm",
3456         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3457         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3458         .main_clk       = "usb_otg_hs_ick",
3459         .prcm = {
3460                 .omap4 = {
3461                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3462                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3463                         .modulemode   = MODULEMODE_HWCTRL,
3464                 },
3465         },
3466         .opt_clks       = usb_otg_hs_opt_clks,
3467         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3468 };
3469
3470 /*
3471  * 'usb_tll_hs' class
3472  * usb_tll_hs module is the adapter on the usb_host_hs ports
3473  */
3474
3475 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3476         .rev_offs       = 0x0000,
3477         .sysc_offs      = 0x0010,
3478         .syss_offs      = 0x0014,
3479         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3480                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3481                            SYSC_HAS_AUTOIDLE),
3482         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3483         .sysc_fields    = &omap_hwmod_sysc_type1,
3484 };
3485
3486 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3487         .name   = "usb_tll_hs",
3488         .sysc   = &omap44xx_usb_tll_hs_sysc,
3489 };
3490
3491 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3492         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3493         { .irq = -1 }
3494 };
3495
3496 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3497         .name           = "usb_tll_hs",
3498         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3499         .clkdm_name     = "l3_init_clkdm",
3500         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3501         .main_clk       = "usb_tll_hs_ick",
3502         .prcm = {
3503                 .omap4 = {
3504                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3505                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3506                         .modulemode   = MODULEMODE_HWCTRL,
3507                 },
3508         },
3509 };
3510
3511 /*
3512  * 'wd_timer' class
3513  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3514  * overflow condition
3515  */
3516
3517 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3518         .rev_offs       = 0x0000,
3519         .sysc_offs      = 0x0010,
3520         .syss_offs      = 0x0014,
3521         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3522                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3523         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3524                            SIDLE_SMART_WKUP),
3525         .sysc_fields    = &omap_hwmod_sysc_type1,
3526 };
3527
3528 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3529         .name           = "wd_timer",
3530         .sysc           = &omap44xx_wd_timer_sysc,
3531         .pre_shutdown   = &omap2_wd_timer_disable,
3532         .reset          = &omap2_wd_timer_reset,
3533 };
3534
3535 /* wd_timer2 */
3536 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3537         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3538         { .irq = -1 }
3539 };
3540
3541 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3542         .name           = "wd_timer2",
3543         .class          = &omap44xx_wd_timer_hwmod_class,
3544         .clkdm_name     = "l4_wkup_clkdm",
3545         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3546         .main_clk       = "wd_timer2_fck",
3547         .prcm = {
3548                 .omap4 = {
3549                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3550                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3551                         .modulemode   = MODULEMODE_SWCTRL,
3552                 },
3553         },
3554 };
3555
3556 /* wd_timer3 */
3557 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3558         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3559         { .irq = -1 }
3560 };
3561
3562 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3563         .name           = "wd_timer3",
3564         .class          = &omap44xx_wd_timer_hwmod_class,
3565         .clkdm_name     = "abe_clkdm",
3566         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3567         .main_clk       = "wd_timer3_fck",
3568         .prcm = {
3569                 .omap4 = {
3570                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3571                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3572                         .modulemode   = MODULEMODE_SWCTRL,
3573                 },
3574         },
3575 };
3576
3577
3578 /*
3579  * interfaces
3580  */
3581
3582 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3583         {
3584                 .pa_start       = 0x4a204000,
3585                 .pa_end         = 0x4a2040ff,
3586                 .flags          = ADDR_TYPE_RT
3587         },
3588         { }
3589 };
3590
3591 /* c2c -> c2c_target_fw */
3592 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3593         .master         = &omap44xx_c2c_hwmod,
3594         .slave          = &omap44xx_c2c_target_fw_hwmod,
3595         .clk            = "div_core_ck",
3596         .addr           = omap44xx_c2c_target_fw_addrs,
3597         .user           = OCP_USER_MPU,
3598 };
3599
3600 /* l4_cfg -> c2c_target_fw */
3601 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3602         .master         = &omap44xx_l4_cfg_hwmod,
3603         .slave          = &omap44xx_c2c_target_fw_hwmod,
3604         .clk            = "l4_div_ck",
3605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3606 };
3607
3608 /* l3_main_1 -> dmm */
3609 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3610         .master         = &omap44xx_l3_main_1_hwmod,
3611         .slave          = &omap44xx_dmm_hwmod,
3612         .clk            = "l3_div_ck",
3613         .user           = OCP_USER_SDMA,
3614 };
3615
3616 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3617         {
3618                 .pa_start       = 0x4e000000,
3619                 .pa_end         = 0x4e0007ff,
3620                 .flags          = ADDR_TYPE_RT
3621         },
3622         { }
3623 };
3624
3625 /* mpu -> dmm */
3626 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3627         .master         = &omap44xx_mpu_hwmod,
3628         .slave          = &omap44xx_dmm_hwmod,
3629         .clk            = "l3_div_ck",
3630         .addr           = omap44xx_dmm_addrs,
3631         .user           = OCP_USER_MPU,
3632 };
3633
3634 /* c2c -> emif_fw */
3635 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3636         .master         = &omap44xx_c2c_hwmod,
3637         .slave          = &omap44xx_emif_fw_hwmod,
3638         .clk            = "div_core_ck",
3639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3640 };
3641
3642 /* dmm -> emif_fw */
3643 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3644         .master         = &omap44xx_dmm_hwmod,
3645         .slave          = &omap44xx_emif_fw_hwmod,
3646         .clk            = "l3_div_ck",
3647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3648 };
3649
3650 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3651         {
3652                 .pa_start       = 0x4a20c000,
3653                 .pa_end         = 0x4a20c0ff,
3654                 .flags          = ADDR_TYPE_RT
3655         },
3656         { }
3657 };
3658
3659 /* l4_cfg -> emif_fw */
3660 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3661         .master         = &omap44xx_l4_cfg_hwmod,
3662         .slave          = &omap44xx_emif_fw_hwmod,
3663         .clk            = "l4_div_ck",
3664         .addr           = omap44xx_emif_fw_addrs,
3665         .user           = OCP_USER_MPU,
3666 };
3667
3668 /* iva -> l3_instr */
3669 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3670         .master         = &omap44xx_iva_hwmod,
3671         .slave          = &omap44xx_l3_instr_hwmod,
3672         .clk            = "l3_div_ck",
3673         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3674 };
3675
3676 /* l3_main_3 -> l3_instr */
3677 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3678         .master         = &omap44xx_l3_main_3_hwmod,
3679         .slave          = &omap44xx_l3_instr_hwmod,
3680         .clk            = "l3_div_ck",
3681         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3682 };
3683
3684 /* ocp_wp_noc -> l3_instr */
3685 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3686         .master         = &omap44xx_ocp_wp_noc_hwmod,
3687         .slave          = &omap44xx_l3_instr_hwmod,
3688         .clk            = "l3_div_ck",
3689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3690 };
3691
3692 /* dsp -> l3_main_1 */
3693 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3694         .master         = &omap44xx_dsp_hwmod,
3695         .slave          = &omap44xx_l3_main_1_hwmod,
3696         .clk            = "l3_div_ck",
3697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3698 };
3699
3700 /* dss -> l3_main_1 */
3701 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3702         .master         = &omap44xx_dss_hwmod,
3703         .slave          = &omap44xx_l3_main_1_hwmod,
3704         .clk            = "l3_div_ck",
3705         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3706 };
3707
3708 /* l3_main_2 -> l3_main_1 */
3709 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3710         .master         = &omap44xx_l3_main_2_hwmod,
3711         .slave          = &omap44xx_l3_main_1_hwmod,
3712         .clk            = "l3_div_ck",
3713         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3714 };
3715
3716 /* l4_cfg -> l3_main_1 */
3717 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3718         .master         = &omap44xx_l4_cfg_hwmod,
3719         .slave          = &omap44xx_l3_main_1_hwmod,
3720         .clk            = "l4_div_ck",
3721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3722 };
3723
3724 /* mmc1 -> l3_main_1 */
3725 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3726         .master         = &omap44xx_mmc1_hwmod,
3727         .slave          = &omap44xx_l3_main_1_hwmod,
3728         .clk            = "l3_div_ck",
3729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3730 };
3731
3732 /* mmc2 -> l3_main_1 */
3733 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3734         .master         = &omap44xx_mmc2_hwmod,
3735         .slave          = &omap44xx_l3_main_1_hwmod,
3736         .clk            = "l3_div_ck",
3737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3738 };
3739
3740 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3741         {
3742                 .pa_start       = 0x44000000,
3743                 .pa_end         = 0x44000fff,
3744                 .flags          = ADDR_TYPE_RT
3745         },
3746         { }
3747 };
3748
3749 /* mpu -> l3_main_1 */
3750 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3751         .master         = &omap44xx_mpu_hwmod,
3752         .slave          = &omap44xx_l3_main_1_hwmod,
3753         .clk            = "l3_div_ck",
3754         .addr           = omap44xx_l3_main_1_addrs,
3755         .user           = OCP_USER_MPU,
3756 };
3757
3758 /* c2c_target_fw -> l3_main_2 */
3759 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3760         .master         = &omap44xx_c2c_target_fw_hwmod,
3761         .slave          = &omap44xx_l3_main_2_hwmod,
3762         .clk            = "l3_div_ck",
3763         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3764 };
3765
3766 /* debugss -> l3_main_2 */
3767 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3768         .master         = &omap44xx_debugss_hwmod,
3769         .slave          = &omap44xx_l3_main_2_hwmod,
3770         .clk            = "dbgclk_mux_ck",
3771         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3772 };
3773
3774 /* dma_system -> l3_main_2 */
3775 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3776         .master         = &omap44xx_dma_system_hwmod,
3777         .slave          = &omap44xx_l3_main_2_hwmod,
3778         .clk            = "l3_div_ck",
3779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3780 };
3781
3782 /* fdif -> l3_main_2 */
3783 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3784         .master         = &omap44xx_fdif_hwmod,
3785         .slave          = &omap44xx_l3_main_2_hwmod,
3786         .clk            = "l3_div_ck",
3787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3788 };
3789
3790 /* gpu -> l3_main_2 */
3791 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3792         .master         = &omap44xx_gpu_hwmod,
3793         .slave          = &omap44xx_l3_main_2_hwmod,
3794         .clk            = "l3_div_ck",
3795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3796 };
3797
3798 /* hsi -> l3_main_2 */
3799 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3800         .master         = &omap44xx_hsi_hwmod,
3801         .slave          = &omap44xx_l3_main_2_hwmod,
3802         .clk            = "l3_div_ck",
3803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3804 };
3805
3806 /* ipu -> l3_main_2 */
3807 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3808         .master         = &omap44xx_ipu_hwmod,
3809         .slave          = &omap44xx_l3_main_2_hwmod,
3810         .clk            = "l3_div_ck",
3811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3812 };
3813
3814 /* iss -> l3_main_2 */
3815 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3816         .master         = &omap44xx_iss_hwmod,
3817         .slave          = &omap44xx_l3_main_2_hwmod,
3818         .clk            = "l3_div_ck",
3819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3820 };
3821
3822 /* iva -> l3_main_2 */
3823 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3824         .master         = &omap44xx_iva_hwmod,
3825         .slave          = &omap44xx_l3_main_2_hwmod,
3826         .clk            = "l3_div_ck",
3827         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3828 };
3829
3830 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3831         {
3832                 .pa_start       = 0x44800000,
3833                 .pa_end         = 0x44801fff,
3834                 .flags          = ADDR_TYPE_RT
3835         },
3836         { }
3837 };
3838
3839 /* l3_main_1 -> l3_main_2 */
3840 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3841         .master         = &omap44xx_l3_main_1_hwmod,
3842         .slave          = &omap44xx_l3_main_2_hwmod,
3843         .clk            = "l3_div_ck",
3844         .addr           = omap44xx_l3_main_2_addrs,
3845         .user           = OCP_USER_MPU,
3846 };
3847
3848 /* l4_cfg -> l3_main_2 */
3849 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3850         .master         = &omap44xx_l4_cfg_hwmod,
3851         .slave          = &omap44xx_l3_main_2_hwmod,
3852         .clk            = "l4_div_ck",
3853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3854 };
3855
3856 /* usb_host_fs -> l3_main_2 */
3857 static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
3858         .master         = &omap44xx_usb_host_fs_hwmod,
3859         .slave          = &omap44xx_l3_main_2_hwmod,
3860         .clk            = "l3_div_ck",
3861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3862 };
3863
3864 /* usb_host_hs -> l3_main_2 */
3865 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3866         .master         = &omap44xx_usb_host_hs_hwmod,
3867         .slave          = &omap44xx_l3_main_2_hwmod,
3868         .clk            = "l3_div_ck",
3869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3870 };
3871
3872 /* usb_otg_hs -> l3_main_2 */
3873 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3874         .master         = &omap44xx_usb_otg_hs_hwmod,
3875         .slave          = &omap44xx_l3_main_2_hwmod,
3876         .clk            = "l3_div_ck",
3877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3878 };
3879
3880 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3881         {
3882                 .pa_start       = 0x45000000,
3883                 .pa_end         = 0x45000fff,
3884                 .flags          = ADDR_TYPE_RT
3885         },
3886         { }
3887 };
3888
3889 /* l3_main_1 -> l3_main_3 */
3890 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3891         .master         = &omap44xx_l3_main_1_hwmod,
3892         .slave          = &omap44xx_l3_main_3_hwmod,
3893         .clk            = "l3_div_ck",
3894         .addr           = omap44xx_l3_main_3_addrs,
3895         .user           = OCP_USER_MPU,
3896 };
3897
3898 /* l3_main_2 -> l3_main_3 */
3899 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3900         .master         = &omap44xx_l3_main_2_hwmod,
3901         .slave          = &omap44xx_l3_main_3_hwmod,
3902         .clk            = "l3_div_ck",
3903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3904 };
3905
3906 /* l4_cfg -> l3_main_3 */
3907 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3908         .master         = &omap44xx_l4_cfg_hwmod,
3909         .slave          = &omap44xx_l3_main_3_hwmod,
3910         .clk            = "l4_div_ck",
3911         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3912 };
3913
3914 /* aess -> l4_abe */
3915 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
3916         .master         = &omap44xx_aess_hwmod,
3917         .slave          = &omap44xx_l4_abe_hwmod,
3918         .clk            = "ocp_abe_iclk",
3919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3920 };
3921
3922 /* dsp -> l4_abe */
3923 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3924         .master         = &omap44xx_dsp_hwmod,
3925         .slave          = &omap44xx_l4_abe_hwmod,
3926         .clk            = "ocp_abe_iclk",
3927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3928 };
3929
3930 /* l3_main_1 -> l4_abe */
3931 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3932         .master         = &omap44xx_l3_main_1_hwmod,
3933         .slave          = &omap44xx_l4_abe_hwmod,
3934         .clk            = "l3_div_ck",
3935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3936 };
3937
3938 /* mpu -> l4_abe */
3939 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3940         .master         = &omap44xx_mpu_hwmod,
3941         .slave          = &omap44xx_l4_abe_hwmod,
3942         .clk            = "ocp_abe_iclk",
3943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3944 };
3945
3946 /* l3_main_1 -> l4_cfg */
3947 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3948         .master         = &omap44xx_l3_main_1_hwmod,
3949         .slave          = &omap44xx_l4_cfg_hwmod,
3950         .clk            = "l3_div_ck",
3951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3952 };
3953
3954 /* l3_main_2 -> l4_per */
3955 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3956         .master         = &omap44xx_l3_main_2_hwmod,
3957         .slave          = &omap44xx_l4_per_hwmod,
3958         .clk            = "l3_div_ck",
3959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3960 };
3961
3962 /* l4_cfg -> l4_wkup */
3963 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3964         .master         = &omap44xx_l4_cfg_hwmod,
3965         .slave          = &omap44xx_l4_wkup_hwmod,
3966         .clk            = "l4_div_ck",
3967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3968 };
3969
3970 /* mpu -> mpu_private */
3971 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3972         .master         = &omap44xx_mpu_hwmod,
3973         .slave          = &omap44xx_mpu_private_hwmod,
3974         .clk            = "l3_div_ck",
3975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3976 };
3977
3978 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3979         {
3980                 .pa_start       = 0x4a102000,
3981                 .pa_end         = 0x4a10207f,
3982                 .flags          = ADDR_TYPE_RT
3983         },
3984         { }
3985 };
3986
3987 /* l4_cfg -> ocp_wp_noc */
3988 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3989         .master         = &omap44xx_l4_cfg_hwmod,
3990         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3991         .clk            = "l4_div_ck",
3992         .addr           = omap44xx_ocp_wp_noc_addrs,
3993         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3994 };
3995
3996 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3997         {
3998                 .pa_start       = 0x401f1000,
3999                 .pa_end         = 0x401f13ff,
4000                 .flags          = ADDR_TYPE_RT
4001         },
4002         { }
4003 };
4004
4005 /* l4_abe -> aess */
4006 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
4007         .master         = &omap44xx_l4_abe_hwmod,
4008         .slave          = &omap44xx_aess_hwmod,
4009         .clk            = "ocp_abe_iclk",
4010         .addr           = omap44xx_aess_addrs,
4011         .user           = OCP_USER_MPU,
4012 };
4013
4014 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4015         {
4016                 .pa_start       = 0x490f1000,
4017                 .pa_end         = 0x490f13ff,
4018                 .flags          = ADDR_TYPE_RT
4019         },
4020         { }
4021 };
4022
4023 /* l4_abe -> aess (dma) */
4024 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
4025         .master         = &omap44xx_l4_abe_hwmod,
4026         .slave          = &omap44xx_aess_hwmod,
4027         .clk            = "ocp_abe_iclk",
4028         .addr           = omap44xx_aess_dma_addrs,
4029         .user           = OCP_USER_SDMA,
4030 };
4031
4032 /* l3_main_2 -> c2c */
4033 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4034         .master         = &omap44xx_l3_main_2_hwmod,
4035         .slave          = &omap44xx_c2c_hwmod,
4036         .clk            = "l3_div_ck",
4037         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4038 };
4039
4040 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4041         {
4042                 .pa_start       = 0x4a304000,
4043                 .pa_end         = 0x4a30401f,
4044                 .flags          = ADDR_TYPE_RT
4045         },
4046         { }
4047 };
4048
4049 /* l4_wkup -> counter_32k */
4050 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4051         .master         = &omap44xx_l4_wkup_hwmod,
4052         .slave          = &omap44xx_counter_32k_hwmod,
4053         .clk            = "l4_wkup_clk_mux_ck",
4054         .addr           = omap44xx_counter_32k_addrs,
4055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4056 };
4057
4058 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4059         {
4060                 .pa_start       = 0x4a002000,
4061                 .pa_end         = 0x4a0027ff,
4062                 .flags          = ADDR_TYPE_RT
4063         },
4064         { }
4065 };
4066
4067 /* l4_cfg -> ctrl_module_core */
4068 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4069         .master         = &omap44xx_l4_cfg_hwmod,
4070         .slave          = &omap44xx_ctrl_module_core_hwmod,
4071         .clk            = "l4_div_ck",
4072         .addr           = omap44xx_ctrl_module_core_addrs,
4073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4074 };
4075
4076 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4077         {
4078                 .pa_start       = 0x4a100000,
4079                 .pa_end         = 0x4a1007ff,
4080                 .flags          = ADDR_TYPE_RT
4081         },
4082         { }
4083 };
4084
4085 /* l4_cfg -> ctrl_module_pad_core */
4086 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4087         .master         = &omap44xx_l4_cfg_hwmod,
4088         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4089         .clk            = "l4_div_ck",
4090         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4091         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4092 };
4093
4094 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4095         {
4096                 .pa_start       = 0x4a30c000,
4097                 .pa_end         = 0x4a30c7ff,
4098                 .flags          = ADDR_TYPE_RT
4099         },
4100         { }
4101 };
4102
4103 /* l4_wkup -> ctrl_module_wkup */
4104 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4105         .master         = &omap44xx_l4_wkup_hwmod,
4106         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4107         .clk            = "l4_wkup_clk_mux_ck",
4108         .addr           = omap44xx_ctrl_module_wkup_addrs,
4109         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4110 };
4111
4112 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4113         {
4114                 .pa_start       = 0x4a31e000,
4115                 .pa_end         = 0x4a31e7ff,
4116                 .flags          = ADDR_TYPE_RT
4117         },
4118         { }
4119 };
4120
4121 /* l4_wkup -> ctrl_module_pad_wkup */
4122 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4123         .master         = &omap44xx_l4_wkup_hwmod,
4124         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4125         .clk            = "l4_wkup_clk_mux_ck",
4126         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4128 };
4129
4130 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4131         {
4132                 .pa_start       = 0x54160000,
4133                 .pa_end         = 0x54167fff,
4134                 .flags          = ADDR_TYPE_RT
4135         },
4136         { }
4137 };
4138
4139 /* l3_instr -> debugss */
4140 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4141         .master         = &omap44xx_l3_instr_hwmod,
4142         .slave          = &omap44xx_debugss_hwmod,
4143         .clk            = "l3_div_ck",
4144         .addr           = omap44xx_debugss_addrs,
4145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4146 };
4147
4148 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4149         {
4150                 .pa_start       = 0x4a056000,
4151                 .pa_end         = 0x4a056fff,
4152                 .flags          = ADDR_TYPE_RT
4153         },
4154         { }
4155 };
4156
4157 /* l4_cfg -> dma_system */
4158 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4159         .master         = &omap44xx_l4_cfg_hwmod,
4160         .slave          = &omap44xx_dma_system_hwmod,
4161         .clk            = "l4_div_ck",
4162         .addr           = omap44xx_dma_system_addrs,
4163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4164 };
4165
4166 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4167         {
4168                 .name           = "mpu",
4169                 .pa_start       = 0x4012e000,
4170                 .pa_end         = 0x4012e07f,
4171                 .flags          = ADDR_TYPE_RT
4172         },
4173         { }
4174 };
4175
4176 /* l4_abe -> dmic */
4177 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4178         .master         = &omap44xx_l4_abe_hwmod,
4179         .slave          = &omap44xx_dmic_hwmod,
4180         .clk            = "ocp_abe_iclk",
4181         .addr           = omap44xx_dmic_addrs,
4182         .user           = OCP_USER_MPU,
4183 };
4184
4185 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4186         {
4187                 .name           = "dma",
4188                 .pa_start       = 0x4902e000,
4189                 .pa_end         = 0x4902e07f,
4190                 .flags          = ADDR_TYPE_RT
4191         },
4192         { }
4193 };
4194
4195 /* l4_abe -> dmic (dma) */
4196 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4197         .master         = &omap44xx_l4_abe_hwmod,
4198         .slave          = &omap44xx_dmic_hwmod,
4199         .clk            = "ocp_abe_iclk",
4200         .addr           = omap44xx_dmic_dma_addrs,
4201         .user           = OCP_USER_SDMA,
4202 };
4203
4204 /* dsp -> iva */
4205 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4206         .master         = &omap44xx_dsp_hwmod,
4207         .slave          = &omap44xx_iva_hwmod,
4208         .clk            = "dpll_iva_m5x2_ck",
4209         .user           = OCP_USER_DSP,
4210 };
4211
4212 /* dsp -> sl2if */
4213 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4214         .master         = &omap44xx_dsp_hwmod,
4215         .slave          = &omap44xx_sl2if_hwmod,
4216         .clk            = "dpll_iva_m5x2_ck",
4217         .user           = OCP_USER_DSP,
4218 };
4219
4220 /* l4_cfg -> dsp */
4221 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4222         .master         = &omap44xx_l4_cfg_hwmod,
4223         .slave          = &omap44xx_dsp_hwmod,
4224         .clk            = "l4_div_ck",
4225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4226 };
4227
4228 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4229         {
4230                 .pa_start       = 0x58000000,
4231                 .pa_end         = 0x5800007f,
4232                 .flags          = ADDR_TYPE_RT
4233         },
4234         { }
4235 };
4236
4237 /* l3_main_2 -> dss */
4238 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4239         .master         = &omap44xx_l3_main_2_hwmod,
4240         .slave          = &omap44xx_dss_hwmod,
4241         .clk            = "dss_fck",
4242         .addr           = omap44xx_dss_dma_addrs,
4243         .user           = OCP_USER_SDMA,
4244 };
4245
4246 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4247         {
4248                 .pa_start       = 0x48040000,
4249                 .pa_end         = 0x4804007f,
4250                 .flags          = ADDR_TYPE_RT
4251         },
4252         { }
4253 };
4254
4255 /* l4_per -> dss */
4256 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4257         .master         = &omap44xx_l4_per_hwmod,
4258         .slave          = &omap44xx_dss_hwmod,
4259         .clk            = "l4_div_ck",
4260         .addr           = omap44xx_dss_addrs,
4261         .user           = OCP_USER_MPU,
4262 };
4263
4264 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4265         {
4266                 .pa_start       = 0x58001000,
4267                 .pa_end         = 0x58001fff,
4268                 .flags          = ADDR_TYPE_RT
4269         },
4270         { }
4271 };
4272
4273 /* l3_main_2 -> dss_dispc */
4274 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4275         .master         = &omap44xx_l3_main_2_hwmod,
4276         .slave          = &omap44xx_dss_dispc_hwmod,
4277         .clk            = "dss_fck",
4278         .addr           = omap44xx_dss_dispc_dma_addrs,
4279         .user           = OCP_USER_SDMA,
4280 };
4281
4282 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4283         {
4284                 .pa_start       = 0x48041000,
4285                 .pa_end         = 0x48041fff,
4286                 .flags          = ADDR_TYPE_RT
4287         },
4288         { }
4289 };
4290
4291 /* l4_per -> dss_dispc */
4292 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4293         .master         = &omap44xx_l4_per_hwmod,
4294         .slave          = &omap44xx_dss_dispc_hwmod,
4295         .clk            = "l4_div_ck",
4296         .addr           = omap44xx_dss_dispc_addrs,
4297         .user           = OCP_USER_MPU,
4298 };
4299
4300 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4301         {
4302                 .pa_start       = 0x58004000,
4303                 .pa_end         = 0x580041ff,
4304                 .flags          = ADDR_TYPE_RT
4305         },
4306         { }
4307 };
4308
4309 /* l3_main_2 -> dss_dsi1 */
4310 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4311         .master         = &omap44xx_l3_main_2_hwmod,
4312         .slave          = &omap44xx_dss_dsi1_hwmod,
4313         .clk            = "dss_fck",
4314         .addr           = omap44xx_dss_dsi1_dma_addrs,
4315         .user           = OCP_USER_SDMA,
4316 };
4317
4318 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4319         {
4320                 .pa_start       = 0x48044000,
4321                 .pa_end         = 0x480441ff,
4322                 .flags          = ADDR_TYPE_RT
4323         },
4324         { }
4325 };
4326
4327 /* l4_per -> dss_dsi1 */
4328 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4329         .master         = &omap44xx_l4_per_hwmod,
4330         .slave          = &omap44xx_dss_dsi1_hwmod,
4331         .clk            = "l4_div_ck",
4332         .addr           = omap44xx_dss_dsi1_addrs,
4333         .user           = OCP_USER_MPU,
4334 };
4335
4336 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4337         {
4338                 .pa_start       = 0x58005000,
4339                 .pa_end         = 0x580051ff,
4340                 .flags          = ADDR_TYPE_RT
4341         },
4342         { }
4343 };
4344
4345 /* l3_main_2 -> dss_dsi2 */
4346 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4347         .master         = &omap44xx_l3_main_2_hwmod,
4348         .slave          = &omap44xx_dss_dsi2_hwmod,
4349         .clk            = "dss_fck",
4350         .addr           = omap44xx_dss_dsi2_dma_addrs,
4351         .user           = OCP_USER_SDMA,
4352 };
4353
4354 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4355         {
4356                 .pa_start       = 0x48045000,
4357                 .pa_end         = 0x480451ff,
4358                 .flags          = ADDR_TYPE_RT
4359         },
4360         { }
4361 };
4362
4363 /* l4_per -> dss_dsi2 */
4364 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4365         .master         = &omap44xx_l4_per_hwmod,
4366         .slave          = &omap44xx_dss_dsi2_hwmod,
4367         .clk            = "l4_div_ck",
4368         .addr           = omap44xx_dss_dsi2_addrs,
4369         .user           = OCP_USER_MPU,
4370 };
4371
4372 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4373         {
4374                 .pa_start       = 0x58006000,
4375                 .pa_end         = 0x58006fff,
4376                 .flags          = ADDR_TYPE_RT
4377         },
4378         { }
4379 };
4380
4381 /* l3_main_2 -> dss_hdmi */
4382 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4383         .master         = &omap44xx_l3_main_2_hwmod,
4384         .slave          = &omap44xx_dss_hdmi_hwmod,
4385         .clk            = "dss_fck",
4386         .addr           = omap44xx_dss_hdmi_dma_addrs,
4387         .user           = OCP_USER_SDMA,
4388 };
4389
4390 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4391         {
4392                 .pa_start       = 0x48046000,
4393                 .pa_end         = 0x48046fff,
4394                 .flags          = ADDR_TYPE_RT
4395         },
4396         { }
4397 };
4398
4399 /* l4_per -> dss_hdmi */
4400 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4401         .master         = &omap44xx_l4_per_hwmod,
4402         .slave          = &omap44xx_dss_hdmi_hwmod,
4403         .clk            = "l4_div_ck",
4404         .addr           = omap44xx_dss_hdmi_addrs,
4405         .user           = OCP_USER_MPU,
4406 };
4407
4408 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4409         {
4410                 .pa_start       = 0x58002000,
4411                 .pa_end         = 0x580020ff,
4412                 .flags          = ADDR_TYPE_RT
4413         },
4414         { }
4415 };
4416
4417 /* l3_main_2 -> dss_rfbi */
4418 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4419         .master         = &omap44xx_l3_main_2_hwmod,
4420         .slave          = &omap44xx_dss_rfbi_hwmod,
4421         .clk            = "dss_fck",
4422         .addr           = omap44xx_dss_rfbi_dma_addrs,
4423         .user           = OCP_USER_SDMA,
4424 };
4425
4426 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4427         {
4428                 .pa_start       = 0x48042000,
4429                 .pa_end         = 0x480420ff,
4430                 .flags          = ADDR_TYPE_RT
4431         },
4432         { }
4433 };
4434
4435 /* l4_per -> dss_rfbi */
4436 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4437         .master         = &omap44xx_l4_per_hwmod,
4438         .slave          = &omap44xx_dss_rfbi_hwmod,
4439         .clk            = "l4_div_ck",
4440         .addr           = omap44xx_dss_rfbi_addrs,
4441         .user           = OCP_USER_MPU,
4442 };
4443
4444 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4445         {
4446                 .pa_start       = 0x58003000,
4447                 .pa_end         = 0x580030ff,
4448                 .flags          = ADDR_TYPE_RT
4449         },
4450         { }
4451 };
4452
4453 /* l3_main_2 -> dss_venc */
4454 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4455         .master         = &omap44xx_l3_main_2_hwmod,
4456         .slave          = &omap44xx_dss_venc_hwmod,
4457         .clk            = "dss_fck",
4458         .addr           = omap44xx_dss_venc_dma_addrs,
4459         .user           = OCP_USER_SDMA,
4460 };
4461
4462 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4463         {
4464                 .pa_start       = 0x48043000,
4465                 .pa_end         = 0x480430ff,
4466                 .flags          = ADDR_TYPE_RT
4467         },
4468         { }
4469 };
4470
4471 /* l4_per -> dss_venc */
4472 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4473         .master         = &omap44xx_l4_per_hwmod,
4474         .slave          = &omap44xx_dss_venc_hwmod,
4475         .clk            = "l4_div_ck",
4476         .addr           = omap44xx_dss_venc_addrs,
4477         .user           = OCP_USER_MPU,
4478 };
4479
4480 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4481         {
4482                 .pa_start       = 0x48078000,
4483                 .pa_end         = 0x48078fff,
4484                 .flags          = ADDR_TYPE_RT
4485         },
4486         { }
4487 };
4488
4489 /* l4_per -> elm */
4490 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4491         .master         = &omap44xx_l4_per_hwmod,
4492         .slave          = &omap44xx_elm_hwmod,
4493         .clk            = "l4_div_ck",
4494         .addr           = omap44xx_elm_addrs,
4495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4496 };
4497
4498 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4499         {
4500                 .pa_start       = 0x4c000000,
4501                 .pa_end         = 0x4c0000ff,
4502                 .flags          = ADDR_TYPE_RT
4503         },
4504         { }
4505 };
4506
4507 /* emif_fw -> emif1 */
4508 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4509         .master         = &omap44xx_emif_fw_hwmod,
4510         .slave          = &omap44xx_emif1_hwmod,
4511         .clk            = "l3_div_ck",
4512         .addr           = omap44xx_emif1_addrs,
4513         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4514 };
4515
4516 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4517         {
4518                 .pa_start       = 0x4d000000,
4519                 .pa_end         = 0x4d0000ff,
4520                 .flags          = ADDR_TYPE_RT
4521         },
4522         { }
4523 };
4524
4525 /* emif_fw -> emif2 */
4526 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4527         .master         = &omap44xx_emif_fw_hwmod,
4528         .slave          = &omap44xx_emif2_hwmod,
4529         .clk            = "l3_div_ck",
4530         .addr           = omap44xx_emif2_addrs,
4531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4532 };
4533
4534 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4535         {
4536                 .pa_start       = 0x4a10a000,
4537                 .pa_end         = 0x4a10a1ff,
4538                 .flags          = ADDR_TYPE_RT
4539         },
4540         { }
4541 };
4542
4543 /* l4_cfg -> fdif */
4544 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4545         .master         = &omap44xx_l4_cfg_hwmod,
4546         .slave          = &omap44xx_fdif_hwmod,
4547         .clk            = "l4_div_ck",
4548         .addr           = omap44xx_fdif_addrs,
4549         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4550 };
4551
4552 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4553         {
4554                 .pa_start       = 0x4a310000,
4555                 .pa_end         = 0x4a3101ff,
4556                 .flags          = ADDR_TYPE_RT
4557         },
4558         { }
4559 };
4560
4561 /* l4_wkup -> gpio1 */
4562 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4563         .master         = &omap44xx_l4_wkup_hwmod,
4564         .slave          = &omap44xx_gpio1_hwmod,
4565         .clk            = "l4_wkup_clk_mux_ck",
4566         .addr           = omap44xx_gpio1_addrs,
4567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4568 };
4569
4570 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4571         {
4572                 .pa_start       = 0x48055000,
4573                 .pa_end         = 0x480551ff,
4574                 .flags          = ADDR_TYPE_RT
4575         },
4576         { }
4577 };
4578
4579 /* l4_per -> gpio2 */
4580 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4581         .master         = &omap44xx_l4_per_hwmod,
4582         .slave          = &omap44xx_gpio2_hwmod,
4583         .clk            = "l4_div_ck",
4584         .addr           = omap44xx_gpio2_addrs,
4585         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4586 };
4587
4588 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4589         {
4590                 .pa_start       = 0x48057000,
4591                 .pa_end         = 0x480571ff,
4592                 .flags          = ADDR_TYPE_RT
4593         },
4594         { }
4595 };
4596
4597 /* l4_per -> gpio3 */
4598 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4599         .master         = &omap44xx_l4_per_hwmod,
4600         .slave          = &omap44xx_gpio3_hwmod,
4601         .clk            = "l4_div_ck",
4602         .addr           = omap44xx_gpio3_addrs,
4603         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4604 };
4605
4606 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4607         {
4608                 .pa_start       = 0x48059000,
4609                 .pa_end         = 0x480591ff,
4610                 .flags          = ADDR_TYPE_RT
4611         },
4612         { }
4613 };
4614
4615 /* l4_per -> gpio4 */
4616 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4617         .master         = &omap44xx_l4_per_hwmod,
4618         .slave          = &omap44xx_gpio4_hwmod,
4619         .clk            = "l4_div_ck",
4620         .addr           = omap44xx_gpio4_addrs,
4621         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4622 };
4623
4624 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4625         {
4626                 .pa_start       = 0x4805b000,
4627                 .pa_end         = 0x4805b1ff,
4628                 .flags          = ADDR_TYPE_RT
4629         },
4630         { }
4631 };
4632
4633 /* l4_per -> gpio5 */
4634 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4635         .master         = &omap44xx_l4_per_hwmod,
4636         .slave          = &omap44xx_gpio5_hwmod,
4637         .clk            = "l4_div_ck",
4638         .addr           = omap44xx_gpio5_addrs,
4639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4640 };
4641
4642 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4643         {
4644                 .pa_start       = 0x4805d000,
4645                 .pa_end         = 0x4805d1ff,
4646                 .flags          = ADDR_TYPE_RT
4647         },
4648         { }
4649 };
4650
4651 /* l4_per -> gpio6 */
4652 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4653         .master         = &omap44xx_l4_per_hwmod,
4654         .slave          = &omap44xx_gpio6_hwmod,
4655         .clk            = "l4_div_ck",
4656         .addr           = omap44xx_gpio6_addrs,
4657         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4658 };
4659
4660 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4661         {
4662                 .pa_start       = 0x50000000,
4663                 .pa_end         = 0x500003ff,
4664                 .flags          = ADDR_TYPE_RT
4665         },
4666         { }
4667 };
4668
4669 /* l3_main_2 -> gpmc */
4670 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4671         .master         = &omap44xx_l3_main_2_hwmod,
4672         .slave          = &omap44xx_gpmc_hwmod,
4673         .clk            = "l3_div_ck",
4674         .addr           = omap44xx_gpmc_addrs,
4675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4676 };
4677
4678 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4679         {
4680                 .pa_start       = 0x56000000,
4681                 .pa_end         = 0x5600ffff,
4682                 .flags          = ADDR_TYPE_RT
4683         },
4684         { }
4685 };
4686
4687 /* l3_main_2 -> gpu */
4688 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4689         .master         = &omap44xx_l3_main_2_hwmod,
4690         .slave          = &omap44xx_gpu_hwmod,
4691         .clk            = "l3_div_ck",
4692         .addr           = omap44xx_gpu_addrs,
4693         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4694 };
4695
4696 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4697         {
4698                 .pa_start       = 0x480b2000,
4699                 .pa_end         = 0x480b201f,
4700                 .flags          = ADDR_TYPE_RT
4701         },
4702         { }
4703 };
4704
4705 /* l4_per -> hdq1w */
4706 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4707         .master         = &omap44xx_l4_per_hwmod,
4708         .slave          = &omap44xx_hdq1w_hwmod,
4709         .clk            = "l4_div_ck",
4710         .addr           = omap44xx_hdq1w_addrs,
4711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4712 };
4713
4714 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4715         {
4716                 .pa_start       = 0x4a058000,
4717                 .pa_end         = 0x4a05bfff,
4718                 .flags          = ADDR_TYPE_RT
4719         },
4720         { }
4721 };
4722
4723 /* l4_cfg -> hsi */
4724 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4725         .master         = &omap44xx_l4_cfg_hwmod,
4726         .slave          = &omap44xx_hsi_hwmod,
4727         .clk            = "l4_div_ck",
4728         .addr           = omap44xx_hsi_addrs,
4729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4730 };
4731
4732 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4733         {
4734                 .pa_start       = 0x48070000,
4735                 .pa_end         = 0x480700ff,
4736                 .flags          = ADDR_TYPE_RT
4737         },
4738         { }
4739 };
4740
4741 /* l4_per -> i2c1 */
4742 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4743         .master         = &omap44xx_l4_per_hwmod,
4744         .slave          = &omap44xx_i2c1_hwmod,
4745         .clk            = "l4_div_ck",
4746         .addr           = omap44xx_i2c1_addrs,
4747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4748 };
4749
4750 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4751         {
4752                 .pa_start       = 0x48072000,
4753                 .pa_end         = 0x480720ff,
4754                 .flags          = ADDR_TYPE_RT
4755         },
4756         { }
4757 };
4758
4759 /* l4_per -> i2c2 */
4760 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4761         .master         = &omap44xx_l4_per_hwmod,
4762         .slave          = &omap44xx_i2c2_hwmod,
4763         .clk            = "l4_div_ck",
4764         .addr           = omap44xx_i2c2_addrs,
4765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4766 };
4767
4768 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4769         {
4770                 .pa_start       = 0x48060000,
4771                 .pa_end         = 0x480600ff,
4772                 .flags          = ADDR_TYPE_RT
4773         },
4774         { }
4775 };
4776
4777 /* l4_per -> i2c3 */
4778 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4779         .master         = &omap44xx_l4_per_hwmod,
4780         .slave          = &omap44xx_i2c3_hwmod,
4781         .clk            = "l4_div_ck",
4782         .addr           = omap44xx_i2c3_addrs,
4783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4784 };
4785
4786 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4787         {
4788                 .pa_start       = 0x48350000,
4789                 .pa_end         = 0x483500ff,
4790                 .flags          = ADDR_TYPE_RT
4791         },
4792         { }
4793 };
4794
4795 /* l4_per -> i2c4 */
4796 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4797         .master         = &omap44xx_l4_per_hwmod,
4798         .slave          = &omap44xx_i2c4_hwmod,
4799         .clk            = "l4_div_ck",
4800         .addr           = omap44xx_i2c4_addrs,
4801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4802 };
4803
4804 /* l3_main_2 -> ipu */
4805 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4806         .master         = &omap44xx_l3_main_2_hwmod,
4807         .slave          = &omap44xx_ipu_hwmod,
4808         .clk            = "l3_div_ck",
4809         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4810 };
4811
4812 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4813         {
4814                 .pa_start       = 0x52000000,
4815                 .pa_end         = 0x520000ff,
4816                 .flags          = ADDR_TYPE_RT
4817         },
4818         { }
4819 };
4820
4821 /* l3_main_2 -> iss */
4822 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4823         .master         = &omap44xx_l3_main_2_hwmod,
4824         .slave          = &omap44xx_iss_hwmod,
4825         .clk            = "l3_div_ck",
4826         .addr           = omap44xx_iss_addrs,
4827         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4828 };
4829
4830 /* iva -> sl2if */
4831 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4832         .master         = &omap44xx_iva_hwmod,
4833         .slave          = &omap44xx_sl2if_hwmod,
4834         .clk            = "dpll_iva_m5x2_ck",
4835         .user           = OCP_USER_IVA,
4836 };
4837
4838 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4839         {
4840                 .pa_start       = 0x5a000000,
4841                 .pa_end         = 0x5a07ffff,
4842                 .flags          = ADDR_TYPE_RT
4843         },
4844         { }
4845 };
4846
4847 /* l3_main_2 -> iva */
4848 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4849         .master         = &omap44xx_l3_main_2_hwmod,
4850         .slave          = &omap44xx_iva_hwmod,
4851         .clk            = "l3_div_ck",
4852         .addr           = omap44xx_iva_addrs,
4853         .user           = OCP_USER_MPU,
4854 };
4855
4856 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4857         {
4858                 .pa_start       = 0x4a31c000,
4859                 .pa_end         = 0x4a31c07f,
4860                 .flags          = ADDR_TYPE_RT
4861         },
4862         { }
4863 };
4864
4865 /* l4_wkup -> kbd */
4866 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4867         .master         = &omap44xx_l4_wkup_hwmod,
4868         .slave          = &omap44xx_kbd_hwmod,
4869         .clk            = "l4_wkup_clk_mux_ck",
4870         .addr           = omap44xx_kbd_addrs,
4871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4872 };
4873
4874 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4875         {
4876                 .pa_start       = 0x4a0f4000,
4877                 .pa_end         = 0x4a0f41ff,
4878                 .flags          = ADDR_TYPE_RT
4879         },
4880         { }
4881 };
4882
4883 /* l4_cfg -> mailbox */
4884 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4885         .master         = &omap44xx_l4_cfg_hwmod,
4886         .slave          = &omap44xx_mailbox_hwmod,
4887         .clk            = "l4_div_ck",
4888         .addr           = omap44xx_mailbox_addrs,
4889         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4890 };
4891
4892 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4893         {
4894                 .pa_start       = 0x40128000,
4895                 .pa_end         = 0x401283ff,
4896                 .flags          = ADDR_TYPE_RT
4897         },
4898         { }
4899 };
4900
4901 /* l4_abe -> mcasp */
4902 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4903         .master         = &omap44xx_l4_abe_hwmod,
4904         .slave          = &omap44xx_mcasp_hwmod,
4905         .clk            = "ocp_abe_iclk",
4906         .addr           = omap44xx_mcasp_addrs,
4907         .user           = OCP_USER_MPU,
4908 };
4909
4910 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4911         {
4912                 .pa_start       = 0x49028000,
4913                 .pa_end         = 0x490283ff,
4914                 .flags          = ADDR_TYPE_RT
4915         },
4916         { }
4917 };
4918
4919 /* l4_abe -> mcasp (dma) */
4920 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4921         .master         = &omap44xx_l4_abe_hwmod,
4922         .slave          = &omap44xx_mcasp_hwmod,
4923         .clk            = "ocp_abe_iclk",
4924         .addr           = omap44xx_mcasp_dma_addrs,
4925         .user           = OCP_USER_SDMA,
4926 };
4927
4928 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4929         {
4930                 .name           = "mpu",
4931                 .pa_start       = 0x40122000,
4932                 .pa_end         = 0x401220ff,
4933                 .flags          = ADDR_TYPE_RT
4934         },
4935         { }
4936 };
4937
4938 /* l4_abe -> mcbsp1 */
4939 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4940         .master         = &omap44xx_l4_abe_hwmod,
4941         .slave          = &omap44xx_mcbsp1_hwmod,
4942         .clk            = "ocp_abe_iclk",
4943         .addr           = omap44xx_mcbsp1_addrs,
4944         .user           = OCP_USER_MPU,
4945 };
4946
4947 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4948         {
4949                 .name           = "dma",
4950                 .pa_start       = 0x49022000,
4951                 .pa_end         = 0x490220ff,
4952                 .flags          = ADDR_TYPE_RT
4953         },
4954         { }
4955 };
4956
4957 /* l4_abe -> mcbsp1 (dma) */
4958 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4959         .master         = &omap44xx_l4_abe_hwmod,
4960         .slave          = &omap44xx_mcbsp1_hwmod,
4961         .clk            = "ocp_abe_iclk",
4962         .addr           = omap44xx_mcbsp1_dma_addrs,
4963         .user           = OCP_USER_SDMA,
4964 };
4965
4966 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4967         {
4968                 .name           = "mpu",
4969                 .pa_start       = 0x40124000,
4970                 .pa_end         = 0x401240ff,
4971                 .flags          = ADDR_TYPE_RT
4972         },
4973         { }
4974 };
4975
4976 /* l4_abe -> mcbsp2 */
4977 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4978         .master         = &omap44xx_l4_abe_hwmod,
4979         .slave          = &omap44xx_mcbsp2_hwmod,
4980         .clk            = "ocp_abe_iclk",
4981         .addr           = omap44xx_mcbsp2_addrs,
4982         .user           = OCP_USER_MPU,
4983 };
4984
4985 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4986         {
4987                 .name           = "dma",
4988                 .pa_start       = 0x49024000,
4989                 .pa_end         = 0x490240ff,
4990                 .flags          = ADDR_TYPE_RT
4991         },
4992         { }
4993 };
4994
4995 /* l4_abe -> mcbsp2 (dma) */
4996 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4997         .master         = &omap44xx_l4_abe_hwmod,
4998         .slave          = &omap44xx_mcbsp2_hwmod,
4999         .clk            = "ocp_abe_iclk",
5000         .addr           = omap44xx_mcbsp2_dma_addrs,
5001         .user           = OCP_USER_SDMA,
5002 };
5003
5004 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5005         {
5006                 .name           = "mpu",
5007                 .pa_start       = 0x40126000,
5008                 .pa_end         = 0x401260ff,
5009                 .flags          = ADDR_TYPE_RT
5010         },
5011         { }
5012 };
5013
5014 /* l4_abe -> mcbsp3 */
5015 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5016         .master         = &omap44xx_l4_abe_hwmod,
5017         .slave          = &omap44xx_mcbsp3_hwmod,
5018         .clk            = "ocp_abe_iclk",
5019         .addr           = omap44xx_mcbsp3_addrs,
5020         .user           = OCP_USER_MPU,
5021 };
5022
5023 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5024         {
5025                 .name           = "dma",
5026                 .pa_start       = 0x49026000,
5027                 .pa_end         = 0x490260ff,
5028                 .flags          = ADDR_TYPE_RT
5029         },
5030         { }
5031 };
5032
5033 /* l4_abe -> mcbsp3 (dma) */
5034 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5035         .master         = &omap44xx_l4_abe_hwmod,
5036         .slave          = &omap44xx_mcbsp3_hwmod,
5037         .clk            = "ocp_abe_iclk",
5038         .addr           = omap44xx_mcbsp3_dma_addrs,
5039         .user           = OCP_USER_SDMA,
5040 };
5041
5042 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5043         {
5044                 .pa_start       = 0x48096000,
5045                 .pa_end         = 0x480960ff,
5046                 .flags          = ADDR_TYPE_RT
5047         },
5048         { }
5049 };
5050
5051 /* l4_per -> mcbsp4 */
5052 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5053         .master         = &omap44xx_l4_per_hwmod,
5054         .slave          = &omap44xx_mcbsp4_hwmod,
5055         .clk            = "l4_div_ck",
5056         .addr           = omap44xx_mcbsp4_addrs,
5057         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5058 };
5059
5060 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5061         {
5062                 .pa_start       = 0x40132000,
5063                 .pa_end         = 0x4013207f,
5064                 .flags          = ADDR_TYPE_RT
5065         },
5066         { }
5067 };
5068
5069 /* l4_abe -> mcpdm */
5070 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5071         .master         = &omap44xx_l4_abe_hwmod,
5072         .slave          = &omap44xx_mcpdm_hwmod,
5073         .clk            = "ocp_abe_iclk",
5074         .addr           = omap44xx_mcpdm_addrs,
5075         .user           = OCP_USER_MPU,
5076 };
5077
5078 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5079         {
5080                 .pa_start       = 0x49032000,
5081                 .pa_end         = 0x4903207f,
5082                 .flags          = ADDR_TYPE_RT
5083         },
5084         { }
5085 };
5086
5087 /* l4_abe -> mcpdm (dma) */
5088 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5089         .master         = &omap44xx_l4_abe_hwmod,
5090         .slave          = &omap44xx_mcpdm_hwmod,
5091         .clk            = "ocp_abe_iclk",
5092         .addr           = omap44xx_mcpdm_dma_addrs,
5093         .user           = OCP_USER_SDMA,
5094 };
5095
5096 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5097         {
5098                 .pa_start       = 0x48098000,
5099                 .pa_end         = 0x480981ff,
5100                 .flags          = ADDR_TYPE_RT
5101         },
5102         { }
5103 };
5104
5105 /* l4_per -> mcspi1 */
5106 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5107         .master         = &omap44xx_l4_per_hwmod,
5108         .slave          = &omap44xx_mcspi1_hwmod,
5109         .clk            = "l4_div_ck",
5110         .addr           = omap44xx_mcspi1_addrs,
5111         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5112 };
5113
5114 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5115         {
5116                 .pa_start       = 0x4809a000,
5117                 .pa_end         = 0x4809a1ff,
5118                 .flags          = ADDR_TYPE_RT
5119         },
5120         { }
5121 };
5122
5123 /* l4_per -> mcspi2 */
5124 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5125         .master         = &omap44xx_l4_per_hwmod,
5126         .slave          = &omap44xx_mcspi2_hwmod,
5127         .clk            = "l4_div_ck",
5128         .addr           = omap44xx_mcspi2_addrs,
5129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5130 };
5131
5132 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5133         {
5134                 .pa_start       = 0x480b8000,
5135                 .pa_end         = 0x480b81ff,
5136                 .flags          = ADDR_TYPE_RT
5137         },
5138         { }
5139 };
5140
5141 /* l4_per -> mcspi3 */
5142 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5143         .master         = &omap44xx_l4_per_hwmod,
5144         .slave          = &omap44xx_mcspi3_hwmod,
5145         .clk            = "l4_div_ck",
5146         .addr           = omap44xx_mcspi3_addrs,
5147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5148 };
5149
5150 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5151         {
5152                 .pa_start       = 0x480ba000,
5153                 .pa_end         = 0x480ba1ff,
5154                 .flags          = ADDR_TYPE_RT
5155         },
5156         { }
5157 };
5158
5159 /* l4_per -> mcspi4 */
5160 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5161         .master         = &omap44xx_l4_per_hwmod,
5162         .slave          = &omap44xx_mcspi4_hwmod,
5163         .clk            = "l4_div_ck",
5164         .addr           = omap44xx_mcspi4_addrs,
5165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5166 };
5167
5168 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5169         {
5170                 .pa_start       = 0x4809c000,
5171                 .pa_end         = 0x4809c3ff,
5172                 .flags          = ADDR_TYPE_RT
5173         },
5174         { }
5175 };
5176
5177 /* l4_per -> mmc1 */
5178 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5179         .master         = &omap44xx_l4_per_hwmod,
5180         .slave          = &omap44xx_mmc1_hwmod,
5181         .clk            = "l4_div_ck",
5182         .addr           = omap44xx_mmc1_addrs,
5183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5184 };
5185
5186 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5187         {
5188                 .pa_start       = 0x480b4000,
5189                 .pa_end         = 0x480b43ff,
5190                 .flags          = ADDR_TYPE_RT
5191         },
5192         { }
5193 };
5194
5195 /* l4_per -> mmc2 */
5196 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5197         .master         = &omap44xx_l4_per_hwmod,
5198         .slave          = &omap44xx_mmc2_hwmod,
5199         .clk            = "l4_div_ck",
5200         .addr           = omap44xx_mmc2_addrs,
5201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5202 };
5203
5204 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5205         {
5206                 .pa_start       = 0x480ad000,
5207                 .pa_end         = 0x480ad3ff,
5208                 .flags          = ADDR_TYPE_RT
5209         },
5210         { }
5211 };
5212
5213 /* l4_per -> mmc3 */
5214 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5215         .master         = &omap44xx_l4_per_hwmod,
5216         .slave          = &omap44xx_mmc3_hwmod,
5217         .clk            = "l4_div_ck",
5218         .addr           = omap44xx_mmc3_addrs,
5219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5220 };
5221
5222 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5223         {
5224                 .pa_start       = 0x480d1000,
5225                 .pa_end         = 0x480d13ff,
5226                 .flags          = ADDR_TYPE_RT
5227         },
5228         { }
5229 };
5230
5231 /* l4_per -> mmc4 */
5232 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5233         .master         = &omap44xx_l4_per_hwmod,
5234         .slave          = &omap44xx_mmc4_hwmod,
5235         .clk            = "l4_div_ck",
5236         .addr           = omap44xx_mmc4_addrs,
5237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5238 };
5239
5240 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5241         {
5242                 .pa_start       = 0x480d5000,
5243                 .pa_end         = 0x480d53ff,
5244                 .flags          = ADDR_TYPE_RT
5245         },
5246         { }
5247 };
5248
5249 /* l4_per -> mmc5 */
5250 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5251         .master         = &omap44xx_l4_per_hwmod,
5252         .slave          = &omap44xx_mmc5_hwmod,
5253         .clk            = "l4_div_ck",
5254         .addr           = omap44xx_mmc5_addrs,
5255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5256 };
5257
5258 /* l3_main_2 -> ocmc_ram */
5259 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5260         .master         = &omap44xx_l3_main_2_hwmod,
5261         .slave          = &omap44xx_ocmc_ram_hwmod,
5262         .clk            = "l3_div_ck",
5263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5264 };
5265
5266 /* l4_cfg -> ocp2scp_usb_phy */
5267 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5268         .master         = &omap44xx_l4_cfg_hwmod,
5269         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5270         .clk            = "l4_div_ck",
5271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5272 };
5273
5274 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5275         {
5276                 .pa_start       = 0x48243000,
5277                 .pa_end         = 0x48243fff,
5278                 .flags          = ADDR_TYPE_RT
5279         },
5280         { }
5281 };
5282
5283 /* mpu_private -> prcm_mpu */
5284 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5285         .master         = &omap44xx_mpu_private_hwmod,
5286         .slave          = &omap44xx_prcm_mpu_hwmod,
5287         .clk            = "l3_div_ck",
5288         .addr           = omap44xx_prcm_mpu_addrs,
5289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5290 };
5291
5292 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5293         {
5294                 .pa_start       = 0x4a004000,
5295                 .pa_end         = 0x4a004fff,
5296                 .flags          = ADDR_TYPE_RT
5297         },
5298         { }
5299 };
5300
5301 /* l4_wkup -> cm_core_aon */
5302 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5303         .master         = &omap44xx_l4_wkup_hwmod,
5304         .slave          = &omap44xx_cm_core_aon_hwmod,
5305         .clk            = "l4_wkup_clk_mux_ck",
5306         .addr           = omap44xx_cm_core_aon_addrs,
5307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5308 };
5309
5310 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5311         {
5312                 .pa_start       = 0x4a008000,
5313                 .pa_end         = 0x4a009fff,
5314                 .flags          = ADDR_TYPE_RT
5315         },
5316         { }
5317 };
5318
5319 /* l4_cfg -> cm_core */
5320 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5321         .master         = &omap44xx_l4_cfg_hwmod,
5322         .slave          = &omap44xx_cm_core_hwmod,
5323         .clk            = "l4_div_ck",
5324         .addr           = omap44xx_cm_core_addrs,
5325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5326 };
5327
5328 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5329         {
5330                 .pa_start       = 0x4a306000,
5331                 .pa_end         = 0x4a307fff,
5332                 .flags          = ADDR_TYPE_RT
5333         },
5334         { }
5335 };
5336
5337 /* l4_wkup -> prm */
5338 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5339         .master         = &omap44xx_l4_wkup_hwmod,
5340         .slave          = &omap44xx_prm_hwmod,
5341         .clk            = "l4_wkup_clk_mux_ck",
5342         .addr           = omap44xx_prm_addrs,
5343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5344 };
5345
5346 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5347         {
5348                 .pa_start       = 0x4a30a000,
5349                 .pa_end         = 0x4a30a7ff,
5350                 .flags          = ADDR_TYPE_RT
5351         },
5352         { }
5353 };
5354
5355 /* l4_wkup -> scrm */
5356 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5357         .master         = &omap44xx_l4_wkup_hwmod,
5358         .slave          = &omap44xx_scrm_hwmod,
5359         .clk            = "l4_wkup_clk_mux_ck",
5360         .addr           = omap44xx_scrm_addrs,
5361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5362 };
5363
5364 /* l3_main_2 -> sl2if */
5365 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5366         .master         = &omap44xx_l3_main_2_hwmod,
5367         .slave          = &omap44xx_sl2if_hwmod,
5368         .clk            = "l3_div_ck",
5369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5370 };
5371
5372 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5373         {
5374                 .pa_start       = 0x4012c000,
5375                 .pa_end         = 0x4012c3ff,
5376                 .flags          = ADDR_TYPE_RT
5377         },
5378         { }
5379 };
5380
5381 /* l4_abe -> slimbus1 */
5382 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5383         .master         = &omap44xx_l4_abe_hwmod,
5384         .slave          = &omap44xx_slimbus1_hwmod,
5385         .clk            = "ocp_abe_iclk",
5386         .addr           = omap44xx_slimbus1_addrs,
5387         .user           = OCP_USER_MPU,
5388 };
5389
5390 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5391         {
5392                 .pa_start       = 0x4902c000,
5393                 .pa_end         = 0x4902c3ff,
5394                 .flags          = ADDR_TYPE_RT
5395         },
5396         { }
5397 };
5398
5399 /* l4_abe -> slimbus1 (dma) */
5400 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5401         .master         = &omap44xx_l4_abe_hwmod,
5402         .slave          = &omap44xx_slimbus1_hwmod,
5403         .clk            = "ocp_abe_iclk",
5404         .addr           = omap44xx_slimbus1_dma_addrs,
5405         .user           = OCP_USER_SDMA,
5406 };
5407
5408 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5409         {
5410                 .pa_start       = 0x48076000,
5411                 .pa_end         = 0x480763ff,
5412                 .flags          = ADDR_TYPE_RT
5413         },
5414         { }
5415 };
5416
5417 /* l4_per -> slimbus2 */
5418 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5419         .master         = &omap44xx_l4_per_hwmod,
5420         .slave          = &omap44xx_slimbus2_hwmod,
5421         .clk            = "l4_div_ck",
5422         .addr           = omap44xx_slimbus2_addrs,
5423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5424 };
5425
5426 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5427         {
5428                 .pa_start       = 0x4a0dd000,
5429                 .pa_end         = 0x4a0dd03f,
5430                 .flags          = ADDR_TYPE_RT
5431         },
5432         { }
5433 };
5434
5435 /* l4_cfg -> smartreflex_core */
5436 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5437         .master         = &omap44xx_l4_cfg_hwmod,
5438         .slave          = &omap44xx_smartreflex_core_hwmod,
5439         .clk            = "l4_div_ck",
5440         .addr           = omap44xx_smartreflex_core_addrs,
5441         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5442 };
5443
5444 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5445         {
5446                 .pa_start       = 0x4a0db000,
5447                 .pa_end         = 0x4a0db03f,
5448                 .flags          = ADDR_TYPE_RT
5449         },
5450         { }
5451 };
5452
5453 /* l4_cfg -> smartreflex_iva */
5454 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5455         .master         = &omap44xx_l4_cfg_hwmod,
5456         .slave          = &omap44xx_smartreflex_iva_hwmod,
5457         .clk            = "l4_div_ck",
5458         .addr           = omap44xx_smartreflex_iva_addrs,
5459         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5460 };
5461
5462 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5463         {
5464                 .pa_start       = 0x4a0d9000,
5465                 .pa_end         = 0x4a0d903f,
5466                 .flags          = ADDR_TYPE_RT
5467         },
5468         { }
5469 };
5470
5471 /* l4_cfg -> smartreflex_mpu */
5472 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5473         .master         = &omap44xx_l4_cfg_hwmod,
5474         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5475         .clk            = "l4_div_ck",
5476         .addr           = omap44xx_smartreflex_mpu_addrs,
5477         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5478 };
5479
5480 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5481         {
5482                 .pa_start       = 0x4a0f6000,
5483                 .pa_end         = 0x4a0f6fff,
5484                 .flags          = ADDR_TYPE_RT
5485         },
5486         { }
5487 };
5488
5489 /* l4_cfg -> spinlock */
5490 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5491         .master         = &omap44xx_l4_cfg_hwmod,
5492         .slave          = &omap44xx_spinlock_hwmod,
5493         .clk            = "l4_div_ck",
5494         .addr           = omap44xx_spinlock_addrs,
5495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5496 };
5497
5498 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5499         {
5500                 .pa_start       = 0x4a318000,
5501                 .pa_end         = 0x4a31807f,
5502                 .flags          = ADDR_TYPE_RT
5503         },
5504         { }
5505 };
5506
5507 /* l4_wkup -> timer1 */
5508 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5509         .master         = &omap44xx_l4_wkup_hwmod,
5510         .slave          = &omap44xx_timer1_hwmod,
5511         .clk            = "l4_wkup_clk_mux_ck",
5512         .addr           = omap44xx_timer1_addrs,
5513         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5514 };
5515
5516 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5517         {
5518                 .pa_start       = 0x48032000,
5519                 .pa_end         = 0x4803207f,
5520                 .flags          = ADDR_TYPE_RT
5521         },
5522         { }
5523 };
5524
5525 /* l4_per -> timer2 */
5526 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5527         .master         = &omap44xx_l4_per_hwmod,
5528         .slave          = &omap44xx_timer2_hwmod,
5529         .clk            = "l4_div_ck",
5530         .addr           = omap44xx_timer2_addrs,
5531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5532 };
5533
5534 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5535         {
5536                 .pa_start       = 0x48034000,
5537                 .pa_end         = 0x4803407f,
5538                 .flags          = ADDR_TYPE_RT
5539         },
5540         { }
5541 };
5542
5543 /* l4_per -> timer3 */
5544 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5545         .master         = &omap44xx_l4_per_hwmod,
5546         .slave          = &omap44xx_timer3_hwmod,
5547         .clk            = "l4_div_ck",
5548         .addr           = omap44xx_timer3_addrs,
5549         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5550 };
5551
5552 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5553         {
5554                 .pa_start       = 0x48036000,
5555                 .pa_end         = 0x4803607f,
5556                 .flags          = ADDR_TYPE_RT
5557         },
5558         { }
5559 };
5560
5561 /* l4_per -> timer4 */
5562 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5563         .master         = &omap44xx_l4_per_hwmod,
5564         .slave          = &omap44xx_timer4_hwmod,
5565         .clk            = "l4_div_ck",
5566         .addr           = omap44xx_timer4_addrs,
5567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5568 };
5569
5570 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5571         {
5572                 .pa_start       = 0x40138000,
5573                 .pa_end         = 0x4013807f,
5574                 .flags          = ADDR_TYPE_RT
5575         },
5576         { }
5577 };
5578
5579 /* l4_abe -> timer5 */
5580 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5581         .master         = &omap44xx_l4_abe_hwmod,
5582         .slave          = &omap44xx_timer5_hwmod,
5583         .clk            = "ocp_abe_iclk",
5584         .addr           = omap44xx_timer5_addrs,
5585         .user           = OCP_USER_MPU,
5586 };
5587
5588 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5589         {
5590                 .pa_start       = 0x49038000,
5591                 .pa_end         = 0x4903807f,
5592                 .flags          = ADDR_TYPE_RT
5593         },
5594         { }
5595 };
5596
5597 /* l4_abe -> timer5 (dma) */
5598 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5599         .master         = &omap44xx_l4_abe_hwmod,
5600         .slave          = &omap44xx_timer5_hwmod,
5601         .clk            = "ocp_abe_iclk",
5602         .addr           = omap44xx_timer5_dma_addrs,
5603         .user           = OCP_USER_SDMA,
5604 };
5605
5606 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5607         {
5608                 .pa_start       = 0x4013a000,
5609                 .pa_end         = 0x4013a07f,
5610                 .flags          = ADDR_TYPE_RT
5611         },
5612         { }
5613 };
5614
5615 /* l4_abe -> timer6 */
5616 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5617         .master         = &omap44xx_l4_abe_hwmod,
5618         .slave          = &omap44xx_timer6_hwmod,
5619         .clk            = "ocp_abe_iclk",
5620         .addr           = omap44xx_timer6_addrs,
5621         .user           = OCP_USER_MPU,
5622 };
5623
5624 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5625         {
5626                 .pa_start       = 0x4903a000,
5627                 .pa_end         = 0x4903a07f,
5628                 .flags          = ADDR_TYPE_RT
5629         },
5630         { }
5631 };
5632
5633 /* l4_abe -> timer6 (dma) */
5634 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5635         .master         = &omap44xx_l4_abe_hwmod,
5636         .slave          = &omap44xx_timer6_hwmod,
5637         .clk            = "ocp_abe_iclk",
5638         .addr           = omap44xx_timer6_dma_addrs,
5639         .user           = OCP_USER_SDMA,
5640 };
5641
5642 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5643         {
5644                 .pa_start       = 0x4013c000,
5645                 .pa_end         = 0x4013c07f,
5646                 .flags          = ADDR_TYPE_RT
5647         },
5648         { }
5649 };
5650
5651 /* l4_abe -> timer7 */
5652 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5653         .master         = &omap44xx_l4_abe_hwmod,
5654         .slave          = &omap44xx_timer7_hwmod,
5655         .clk            = "ocp_abe_iclk",
5656         .addr           = omap44xx_timer7_addrs,
5657         .user           = OCP_USER_MPU,
5658 };
5659
5660 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5661         {
5662                 .pa_start       = 0x4903c000,
5663                 .pa_end         = 0x4903c07f,
5664                 .flags          = ADDR_TYPE_RT
5665         },
5666         { }
5667 };
5668
5669 /* l4_abe -> timer7 (dma) */
5670 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5671         .master         = &omap44xx_l4_abe_hwmod,
5672         .slave          = &omap44xx_timer7_hwmod,
5673         .clk            = "ocp_abe_iclk",
5674         .addr           = omap44xx_timer7_dma_addrs,
5675         .user           = OCP_USER_SDMA,
5676 };
5677
5678 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5679         {
5680                 .pa_start       = 0x4013e000,
5681                 .pa_end         = 0x4013e07f,
5682                 .flags          = ADDR_TYPE_RT
5683         },
5684         { }
5685 };
5686
5687 /* l4_abe -> timer8 */
5688 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5689         .master         = &omap44xx_l4_abe_hwmod,
5690         .slave          = &omap44xx_timer8_hwmod,
5691         .clk            = "ocp_abe_iclk",
5692         .addr           = omap44xx_timer8_addrs,
5693         .user           = OCP_USER_MPU,
5694 };
5695
5696 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5697         {
5698                 .pa_start       = 0x4903e000,
5699                 .pa_end         = 0x4903e07f,
5700                 .flags          = ADDR_TYPE_RT
5701         },
5702         { }
5703 };
5704
5705 /* l4_abe -> timer8 (dma) */
5706 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5707         .master         = &omap44xx_l4_abe_hwmod,
5708         .slave          = &omap44xx_timer8_hwmod,
5709         .clk            = "ocp_abe_iclk",
5710         .addr           = omap44xx_timer8_dma_addrs,
5711         .user           = OCP_USER_SDMA,
5712 };
5713
5714 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5715         {
5716                 .pa_start       = 0x4803e000,
5717                 .pa_end         = 0x4803e07f,
5718                 .flags          = ADDR_TYPE_RT
5719         },
5720         { }
5721 };
5722
5723 /* l4_per -> timer9 */
5724 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5725         .master         = &omap44xx_l4_per_hwmod,
5726         .slave          = &omap44xx_timer9_hwmod,
5727         .clk            = "l4_div_ck",
5728         .addr           = omap44xx_timer9_addrs,
5729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5730 };
5731
5732 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5733         {
5734                 .pa_start       = 0x48086000,
5735                 .pa_end         = 0x4808607f,
5736                 .flags          = ADDR_TYPE_RT
5737         },
5738         { }
5739 };
5740
5741 /* l4_per -> timer10 */
5742 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5743         .master         = &omap44xx_l4_per_hwmod,
5744         .slave          = &omap44xx_timer10_hwmod,
5745         .clk            = "l4_div_ck",
5746         .addr           = omap44xx_timer10_addrs,
5747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5748 };
5749
5750 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5751         {
5752                 .pa_start       = 0x48088000,
5753                 .pa_end         = 0x4808807f,
5754                 .flags          = ADDR_TYPE_RT
5755         },
5756         { }
5757 };
5758
5759 /* l4_per -> timer11 */
5760 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5761         .master         = &omap44xx_l4_per_hwmod,
5762         .slave          = &omap44xx_timer11_hwmod,
5763         .clk            = "l4_div_ck",
5764         .addr           = omap44xx_timer11_addrs,
5765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5766 };
5767
5768 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5769         {
5770                 .pa_start       = 0x4806a000,
5771                 .pa_end         = 0x4806a0ff,
5772                 .flags          = ADDR_TYPE_RT
5773         },
5774         { }
5775 };
5776
5777 /* l4_per -> uart1 */
5778 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5779         .master         = &omap44xx_l4_per_hwmod,
5780         .slave          = &omap44xx_uart1_hwmod,
5781         .clk            = "l4_div_ck",
5782         .addr           = omap44xx_uart1_addrs,
5783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5784 };
5785
5786 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5787         {
5788                 .pa_start       = 0x4806c000,
5789                 .pa_end         = 0x4806c0ff,
5790                 .flags          = ADDR_TYPE_RT
5791         },
5792         { }
5793 };
5794
5795 /* l4_per -> uart2 */
5796 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5797         .master         = &omap44xx_l4_per_hwmod,
5798         .slave          = &omap44xx_uart2_hwmod,
5799         .clk            = "l4_div_ck",
5800         .addr           = omap44xx_uart2_addrs,
5801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5802 };
5803
5804 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5805         {
5806                 .pa_start       = 0x48020000,
5807                 .pa_end         = 0x480200ff,
5808                 .flags          = ADDR_TYPE_RT
5809         },
5810         { }
5811 };
5812
5813 /* l4_per -> uart3 */
5814 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5815         .master         = &omap44xx_l4_per_hwmod,
5816         .slave          = &omap44xx_uart3_hwmod,
5817         .clk            = "l4_div_ck",
5818         .addr           = omap44xx_uart3_addrs,
5819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5820 };
5821
5822 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5823         {
5824                 .pa_start       = 0x4806e000,
5825                 .pa_end         = 0x4806e0ff,
5826                 .flags          = ADDR_TYPE_RT
5827         },
5828         { }
5829 };
5830
5831 /* l4_per -> uart4 */
5832 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5833         .master         = &omap44xx_l4_per_hwmod,
5834         .slave          = &omap44xx_uart4_hwmod,
5835         .clk            = "l4_div_ck",
5836         .addr           = omap44xx_uart4_addrs,
5837         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5838 };
5839
5840 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5841         {
5842                 .pa_start       = 0x4a0a9000,
5843                 .pa_end         = 0x4a0a93ff,
5844                 .flags          = ADDR_TYPE_RT
5845         },
5846         { }
5847 };
5848
5849 /* l4_cfg -> usb_host_fs */
5850 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
5851         .master         = &omap44xx_l4_cfg_hwmod,
5852         .slave          = &omap44xx_usb_host_fs_hwmod,
5853         .clk            = "l4_div_ck",
5854         .addr           = omap44xx_usb_host_fs_addrs,
5855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5856 };
5857
5858 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5859         {
5860                 .name           = "uhh",
5861                 .pa_start       = 0x4a064000,
5862                 .pa_end         = 0x4a0647ff,
5863                 .flags          = ADDR_TYPE_RT
5864         },
5865         {
5866                 .name           = "ohci",
5867                 .pa_start       = 0x4a064800,
5868                 .pa_end         = 0x4a064bff,
5869         },
5870         {
5871                 .name           = "ehci",
5872                 .pa_start       = 0x4a064c00,
5873                 .pa_end         = 0x4a064fff,
5874         },
5875         {}
5876 };
5877
5878 /* l4_cfg -> usb_host_hs */
5879 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5880         .master         = &omap44xx_l4_cfg_hwmod,
5881         .slave          = &omap44xx_usb_host_hs_hwmod,
5882         .clk            = "l4_div_ck",
5883         .addr           = omap44xx_usb_host_hs_addrs,
5884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5885 };
5886
5887 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5888         {
5889                 .pa_start       = 0x4a0ab000,
5890                 .pa_end         = 0x4a0ab003,
5891                 .flags          = ADDR_TYPE_RT
5892         },
5893         { }
5894 };
5895
5896 /* l4_cfg -> usb_otg_hs */
5897 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5898         .master         = &omap44xx_l4_cfg_hwmod,
5899         .slave          = &omap44xx_usb_otg_hs_hwmod,
5900         .clk            = "l4_div_ck",
5901         .addr           = omap44xx_usb_otg_hs_addrs,
5902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5903 };
5904
5905 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5906         {
5907                 .name           = "tll",
5908                 .pa_start       = 0x4a062000,
5909                 .pa_end         = 0x4a063fff,
5910                 .flags          = ADDR_TYPE_RT
5911         },
5912         {}
5913 };
5914
5915 /* l4_cfg -> usb_tll_hs */
5916 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5917         .master         = &omap44xx_l4_cfg_hwmod,
5918         .slave          = &omap44xx_usb_tll_hs_hwmod,
5919         .clk            = "l4_div_ck",
5920         .addr           = omap44xx_usb_tll_hs_addrs,
5921         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5922 };
5923
5924 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5925         {
5926                 .pa_start       = 0x4a314000,
5927                 .pa_end         = 0x4a31407f,
5928                 .flags          = ADDR_TYPE_RT
5929         },
5930         { }
5931 };
5932
5933 /* l4_wkup -> wd_timer2 */
5934 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5935         .master         = &omap44xx_l4_wkup_hwmod,
5936         .slave          = &omap44xx_wd_timer2_hwmod,
5937         .clk            = "l4_wkup_clk_mux_ck",
5938         .addr           = omap44xx_wd_timer2_addrs,
5939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5940 };
5941
5942 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5943         {
5944                 .pa_start       = 0x40130000,
5945                 .pa_end         = 0x4013007f,
5946                 .flags          = ADDR_TYPE_RT
5947         },
5948         { }
5949 };
5950
5951 /* l4_abe -> wd_timer3 */
5952 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5953         .master         = &omap44xx_l4_abe_hwmod,
5954         .slave          = &omap44xx_wd_timer3_hwmod,
5955         .clk            = "ocp_abe_iclk",
5956         .addr           = omap44xx_wd_timer3_addrs,
5957         .user           = OCP_USER_MPU,
5958 };
5959
5960 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5961         {
5962                 .pa_start       = 0x49030000,
5963                 .pa_end         = 0x4903007f,
5964                 .flags          = ADDR_TYPE_RT
5965         },
5966         { }
5967 };
5968
5969 /* l4_abe -> wd_timer3 (dma) */
5970 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5971         .master         = &omap44xx_l4_abe_hwmod,
5972         .slave          = &omap44xx_wd_timer3_hwmod,
5973         .clk            = "ocp_abe_iclk",
5974         .addr           = omap44xx_wd_timer3_dma_addrs,
5975         .user           = OCP_USER_SDMA,
5976 };
5977
5978 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5979         &omap44xx_c2c__c2c_target_fw,
5980         &omap44xx_l4_cfg__c2c_target_fw,
5981         &omap44xx_l3_main_1__dmm,
5982         &omap44xx_mpu__dmm,
5983         &omap44xx_c2c__emif_fw,
5984         &omap44xx_dmm__emif_fw,
5985         &omap44xx_l4_cfg__emif_fw,
5986         &omap44xx_iva__l3_instr,
5987         &omap44xx_l3_main_3__l3_instr,
5988         &omap44xx_ocp_wp_noc__l3_instr,
5989         &omap44xx_dsp__l3_main_1,
5990         &omap44xx_dss__l3_main_1,
5991         &omap44xx_l3_main_2__l3_main_1,
5992         &omap44xx_l4_cfg__l3_main_1,
5993         &omap44xx_mmc1__l3_main_1,
5994         &omap44xx_mmc2__l3_main_1,
5995         &omap44xx_mpu__l3_main_1,
5996         &omap44xx_c2c_target_fw__l3_main_2,
5997         &omap44xx_debugss__l3_main_2,
5998         &omap44xx_dma_system__l3_main_2,
5999         &omap44xx_fdif__l3_main_2,
6000         &omap44xx_gpu__l3_main_2,
6001         &omap44xx_hsi__l3_main_2,
6002         &omap44xx_ipu__l3_main_2,
6003         &omap44xx_iss__l3_main_2,
6004         &omap44xx_iva__l3_main_2,
6005         &omap44xx_l3_main_1__l3_main_2,
6006         &omap44xx_l4_cfg__l3_main_2,
6007         &omap44xx_usb_host_fs__l3_main_2,
6008         &omap44xx_usb_host_hs__l3_main_2,
6009         &omap44xx_usb_otg_hs__l3_main_2,
6010         &omap44xx_l3_main_1__l3_main_3,
6011         &omap44xx_l3_main_2__l3_main_3,
6012         &omap44xx_l4_cfg__l3_main_3,
6013         &omap44xx_aess__l4_abe,
6014         &omap44xx_dsp__l4_abe,
6015         &omap44xx_l3_main_1__l4_abe,
6016         &omap44xx_mpu__l4_abe,
6017         &omap44xx_l3_main_1__l4_cfg,
6018         &omap44xx_l3_main_2__l4_per,
6019         &omap44xx_l4_cfg__l4_wkup,
6020         &omap44xx_mpu__mpu_private,
6021         &omap44xx_l4_cfg__ocp_wp_noc,
6022         &omap44xx_l4_abe__aess,
6023         &omap44xx_l4_abe__aess_dma,
6024         &omap44xx_l3_main_2__c2c,
6025         &omap44xx_l4_wkup__counter_32k,
6026         &omap44xx_l4_cfg__ctrl_module_core,
6027         &omap44xx_l4_cfg__ctrl_module_pad_core,
6028         &omap44xx_l4_wkup__ctrl_module_wkup,
6029         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6030         &omap44xx_l3_instr__debugss,
6031         &omap44xx_l4_cfg__dma_system,
6032         &omap44xx_l4_abe__dmic,
6033         &omap44xx_l4_abe__dmic_dma,
6034         &omap44xx_dsp__iva,
6035         &omap44xx_dsp__sl2if,
6036         &omap44xx_l4_cfg__dsp,
6037         &omap44xx_l3_main_2__dss,
6038         &omap44xx_l4_per__dss,
6039         &omap44xx_l3_main_2__dss_dispc,
6040         &omap44xx_l4_per__dss_dispc,
6041         &omap44xx_l3_main_2__dss_dsi1,
6042         &omap44xx_l4_per__dss_dsi1,
6043         &omap44xx_l3_main_2__dss_dsi2,
6044         &omap44xx_l4_per__dss_dsi2,
6045         &omap44xx_l3_main_2__dss_hdmi,
6046         &omap44xx_l4_per__dss_hdmi,
6047         &omap44xx_l3_main_2__dss_rfbi,
6048         &omap44xx_l4_per__dss_rfbi,
6049         &omap44xx_l3_main_2__dss_venc,
6050         &omap44xx_l4_per__dss_venc,
6051         &omap44xx_l4_per__elm,
6052         &omap44xx_emif_fw__emif1,
6053         &omap44xx_emif_fw__emif2,
6054         &omap44xx_l4_cfg__fdif,
6055         &omap44xx_l4_wkup__gpio1,
6056         &omap44xx_l4_per__gpio2,
6057         &omap44xx_l4_per__gpio3,
6058         &omap44xx_l4_per__gpio4,
6059         &omap44xx_l4_per__gpio5,
6060         &omap44xx_l4_per__gpio6,
6061         &omap44xx_l3_main_2__gpmc,
6062         &omap44xx_l3_main_2__gpu,
6063         &omap44xx_l4_per__hdq1w,
6064         &omap44xx_l4_cfg__hsi,
6065         &omap44xx_l4_per__i2c1,
6066         &omap44xx_l4_per__i2c2,
6067         &omap44xx_l4_per__i2c3,
6068         &omap44xx_l4_per__i2c4,
6069         &omap44xx_l3_main_2__ipu,
6070         &omap44xx_l3_main_2__iss,
6071         &omap44xx_iva__sl2if,
6072         &omap44xx_l3_main_2__iva,
6073         &omap44xx_l4_wkup__kbd,
6074         &omap44xx_l4_cfg__mailbox,
6075         &omap44xx_l4_abe__mcasp,
6076         &omap44xx_l4_abe__mcasp_dma,
6077         &omap44xx_l4_abe__mcbsp1,
6078         &omap44xx_l4_abe__mcbsp1_dma,
6079         &omap44xx_l4_abe__mcbsp2,
6080         &omap44xx_l4_abe__mcbsp2_dma,
6081         &omap44xx_l4_abe__mcbsp3,
6082         &omap44xx_l4_abe__mcbsp3_dma,
6083         &omap44xx_l4_per__mcbsp4,
6084         &omap44xx_l4_abe__mcpdm,
6085         &omap44xx_l4_abe__mcpdm_dma,
6086         &omap44xx_l4_per__mcspi1,
6087         &omap44xx_l4_per__mcspi2,
6088         &omap44xx_l4_per__mcspi3,
6089         &omap44xx_l4_per__mcspi4,
6090         &omap44xx_l4_per__mmc1,
6091         &omap44xx_l4_per__mmc2,
6092         &omap44xx_l4_per__mmc3,
6093         &omap44xx_l4_per__mmc4,
6094         &omap44xx_l4_per__mmc5,
6095         &omap44xx_l3_main_2__ocmc_ram,
6096         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6097         &omap44xx_mpu_private__prcm_mpu,
6098         &omap44xx_l4_wkup__cm_core_aon,
6099         &omap44xx_l4_cfg__cm_core,
6100         &omap44xx_l4_wkup__prm,
6101         &omap44xx_l4_wkup__scrm,
6102         &omap44xx_l3_main_2__sl2if,
6103         &omap44xx_l4_abe__slimbus1,
6104         &omap44xx_l4_abe__slimbus1_dma,
6105         &omap44xx_l4_per__slimbus2,
6106         &omap44xx_l4_cfg__smartreflex_core,
6107         &omap44xx_l4_cfg__smartreflex_iva,
6108         &omap44xx_l4_cfg__smartreflex_mpu,
6109         &omap44xx_l4_cfg__spinlock,
6110         &omap44xx_l4_wkup__timer1,
6111         &omap44xx_l4_per__timer2,
6112         &omap44xx_l4_per__timer3,
6113         &omap44xx_l4_per__timer4,
6114         &omap44xx_l4_abe__timer5,
6115         &omap44xx_l4_abe__timer5_dma,
6116         &omap44xx_l4_abe__timer6,
6117         &omap44xx_l4_abe__timer6_dma,
6118         &omap44xx_l4_abe__timer7,
6119         &omap44xx_l4_abe__timer7_dma,
6120         &omap44xx_l4_abe__timer8,
6121         &omap44xx_l4_abe__timer8_dma,
6122         &omap44xx_l4_per__timer9,
6123         &omap44xx_l4_per__timer10,
6124         &omap44xx_l4_per__timer11,
6125         &omap44xx_l4_per__uart1,
6126         &omap44xx_l4_per__uart2,
6127         &omap44xx_l4_per__uart3,
6128         &omap44xx_l4_per__uart4,
6129         &omap44xx_l4_cfg__usb_host_fs,
6130         &omap44xx_l4_cfg__usb_host_hs,
6131         &omap44xx_l4_cfg__usb_otg_hs,
6132         &omap44xx_l4_cfg__usb_tll_hs,
6133         &omap44xx_l4_wkup__wd_timer2,
6134         &omap44xx_l4_abe__wd_timer3,
6135         &omap44xx_l4_abe__wd_timer3_dma,
6136         NULL,
6137 };
6138
6139 int __init omap44xx_hwmod_init(void)
6140 {
6141         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6142 }
6143