Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "smartreflex.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /*
  54  * 'c2c_target_fw' class
  55  * instance(s): c2c_target_fw
  56  */
  57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58         .name   = "c2c_target_fw",
  59 };
  60
  61 /* c2c_target_fw */
  62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63         .name           = "c2c_target_fw",
  64         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  65         .clkdm_name     = "d2d_clkdm",
  66         .prcm = {
  67                 .omap4 = {
  68                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm */
  83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85         { .irq = -1 }
  86 };
  87
  88 static struct omap_hwmod omap44xx_dmm_hwmod = {
  89         .name           = "dmm",
  90         .class          = &omap44xx_dmm_hwmod_class,
  91         .clkdm_name     = "l3_emif_clkdm",
  92         .mpu_irqs       = omap44xx_dmm_irqs,
  93         .prcm = {
  94                 .omap4 = {
  95                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97                 },
  98         },
  99 };
 100
 101 /*
 102  * 'emif_fw' class
 103  * instance(s): emif_fw
 104  */
 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106         .name   = "emif_fw",
 107 };
 108
 109 /* emif_fw */
 110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111         .name           = "emif_fw",
 112         .class          = &omap44xx_emif_fw_hwmod_class,
 113         .clkdm_name     = "l3_emif_clkdm",
 114         .prcm = {
 115                 .omap4 = {
 116                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'l3' class
 124  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125  */
 126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127         .name   = "l3",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &omap44xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_instr_clkdm",
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139                         .modulemode   = MODULEMODE_HWCTRL,
 140                 },
 141         },
 142 };
 143
 144 /* l3_main_1 */
 145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148         { .irq = -1 }
 149 };
 150
 151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152         .name           = "l3_main_1",
 153         .class          = &omap44xx_l3_hwmod_class,
 154         .clkdm_name     = "l3_1_clkdm",
 155         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160                 },
 161         },
 162 };
 163
 164 /* l3_main_2 */
 165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166         .name           = "l3_main_2",
 167         .class          = &omap44xx_l3_hwmod_class,
 168         .clkdm_name     = "l3_2_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173                 },
 174         },
 175 };
 176
 177 /* l3_main_3 */
 178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179         .name           = "l3_main_3",
 180         .class          = &omap44xx_l3_hwmod_class,
 181         .clkdm_name     = "l3_instr_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186                         .modulemode   = MODULEMODE_HWCTRL,
 187                 },
 188         },
 189 };
 190
 191 /*
 192  * 'l4' class
 193  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194  */
 195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196         .name   = "l4",
 197 };
 198
 199 /* l4_abe */
 200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201         .name           = "l4_abe",
 202         .class          = &omap44xx_l4_hwmod_class,
 203         .clkdm_name     = "abe_clkdm",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207                 },
 208         },
 209 };
 210
 211 /* l4_cfg */
 212 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 213         .name           = "l4_cfg",
 214         .class          = &omap44xx_l4_hwmod_class,
 215         .clkdm_name     = "l4_cfg_clkdm",
 216         .prcm = {
 217                 .omap4 = {
 218                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 219                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 220                 },
 221         },
 222 };
 223
 224 /* l4_per */
 225 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 226         .name           = "l4_per",
 227         .class          = &omap44xx_l4_hwmod_class,
 228         .clkdm_name     = "l4_per_clkdm",
 229         .prcm = {
 230                 .omap4 = {
 231                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 232                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 233                 },
 234         },
 235 };
 236
 237 /* l4_wkup */
 238 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 239         .name           = "l4_wkup",
 240         .class          = &omap44xx_l4_hwmod_class,
 241         .clkdm_name     = "l4_wkup_clkdm",
 242         .prcm = {
 243                 .omap4 = {
 244                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 245                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 246                 },
 247         },
 248 };
 249
 250 /*
 251  * 'mpu_bus' class
 252  * instance(s): mpu_private
 253  */
 254 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 255         .name   = "mpu_bus",
 256 };
 257
 258 /* mpu_private */
 259 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 260         .name           = "mpu_private",
 261         .class          = &omap44xx_mpu_bus_hwmod_class,
 262         .clkdm_name     = "mpuss_clkdm",
 263 };
 264
 265 /*
 266  * 'ocp_wp_noc' class
 267  * instance(s): ocp_wp_noc
 268  */
 269 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 270         .name   = "ocp_wp_noc",
 271 };
 272
 273 /* ocp_wp_noc */
 274 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 275         .name           = "ocp_wp_noc",
 276         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 277         .clkdm_name     = "l3_instr_clkdm",
 278         .prcm = {
 279                 .omap4 = {
 280                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 281                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 282                         .modulemode   = MODULEMODE_HWCTRL,
 283                 },
 284         },
 285 };
 286
 287 /*
 288  * Modules omap_hwmod structures
 289  *
 290  * The following IPs are excluded for the moment because:
 291  * - They do not need an explicit SW control using omap_hwmod API.
 292  * - They still need to be validated with the driver
 293  *   properly adapted to omap_hwmod / omap_device
 294  *
 295  * usim
 296  */
 297
 298 /*
 299  * 'aess' class
 300  * audio engine sub system
 301  */
 302
 303 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 304         .rev_offs       = 0x0000,
 305         .sysc_offs      = 0x0010,
 306         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 308                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 309                            MSTANDBY_SMART_WKUP),
 310         .sysc_fields    = &omap_hwmod_sysc_type2,
 311 };
 312
 313 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 314         .name   = "aess",
 315         .sysc   = &omap44xx_aess_sysc,
 316 };
 317
 318 /* aess */
 319 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 320         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 321         { .irq = -1 }
 322 };
 323
 324 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 325         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 326         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 327         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 328         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 329         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 330         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 331         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 332         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 333         { .dma_req = -1 }
 334 };
 335
 336 static struct omap_hwmod omap44xx_aess_hwmod = {
 337         .name           = "aess",
 338         .class          = &omap44xx_aess_hwmod_class,
 339         .clkdm_name     = "abe_clkdm",
 340         .mpu_irqs       = omap44xx_aess_irqs,
 341         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 342         .main_clk       = "aess_fck",
 343         .prcm = {
 344                 .omap4 = {
 345                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 346                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 347                         .modulemode   = MODULEMODE_SWCTRL,
 348                 },
 349         },
 350 };
 351
 352 /*
 353  * 'c2c' class
 354  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 355  * soc
 356  */
 357
 358 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 359         .name   = "c2c",
 360 };
 361
 362 /* c2c */
 363 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 364         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 365         { .irq = -1 }
 366 };
 367
 368 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 369         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 370         { .dma_req = -1 }
 371 };
 372
 373 static struct omap_hwmod omap44xx_c2c_hwmod = {
 374         .name           = "c2c",
 375         .class          = &omap44xx_c2c_hwmod_class,
 376         .clkdm_name     = "d2d_clkdm",
 377         .mpu_irqs       = omap44xx_c2c_irqs,
 378         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 382                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 383                 },
 384         },
 385 };
 386
 387 /*
 388  * 'counter' class
 389  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 390  */
 391
 392 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 393         .rev_offs       = 0x0000,
 394         .sysc_offs      = 0x0004,
 395         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 396         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 397                            SIDLE_SMART_WKUP),
 398         .sysc_fields    = &omap_hwmod_sysc_type1,
 399 };
 400
 401 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 402         .name   = "counter",
 403         .sysc   = &omap44xx_counter_sysc,
 404 };
 405
 406 /* counter_32k */
 407 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 408         .name           = "counter_32k",
 409         .class          = &omap44xx_counter_hwmod_class,
 410         .clkdm_name     = "l4_wkup_clkdm",
 411         .flags          = HWMOD_SWSUP_SIDLE,
 412         .main_clk       = "sys_32k_ck",
 413         .prcm = {
 414                 .omap4 = {
 415                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 416                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 417                 },
 418         },
 419 };
 420
 421 /*
 422  * 'ctrl_module' class
 423  * attila core control module + core pad control module + wkup pad control
 424  * module + attila wkup control module
 425  */
 426
 427 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 428         .rev_offs       = 0x0000,
 429         .sysc_offs      = 0x0010,
 430         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 432                            SIDLE_SMART_WKUP),
 433         .sysc_fields    = &omap_hwmod_sysc_type2,
 434 };
 435
 436 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 437         .name   = "ctrl_module",
 438         .sysc   = &omap44xx_ctrl_module_sysc,
 439 };
 440
 441 /* ctrl_module_core */
 442 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 443         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 444         { .irq = -1 }
 445 };
 446
 447 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 448         .name           = "ctrl_module_core",
 449         .class          = &omap44xx_ctrl_module_hwmod_class,
 450         .clkdm_name     = "l4_cfg_clkdm",
 451         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 452 };
 453
 454 /* ctrl_module_pad_core */
 455 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 456         .name           = "ctrl_module_pad_core",
 457         .class          = &omap44xx_ctrl_module_hwmod_class,
 458         .clkdm_name     = "l4_cfg_clkdm",
 459 };
 460
 461 /* ctrl_module_wkup */
 462 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 463         .name           = "ctrl_module_wkup",
 464         .class          = &omap44xx_ctrl_module_hwmod_class,
 465         .clkdm_name     = "l4_wkup_clkdm",
 466 };
 467
 468 /* ctrl_module_pad_wkup */
 469 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 470         .name           = "ctrl_module_pad_wkup",
 471         .class          = &omap44xx_ctrl_module_hwmod_class,
 472         .clkdm_name     = "l4_wkup_clkdm",
 473 };
 474
 475 /*
 476  * 'debugss' class
 477  * debug and emulation sub system
 478  */
 479
 480 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 481         .name   = "debugss",
 482 };
 483
 484 /* debugss */
 485 static struct omap_hwmod omap44xx_debugss_hwmod = {
 486         .name           = "debugss",
 487         .class          = &omap44xx_debugss_hwmod_class,
 488         .clkdm_name     = "emu_sys_clkdm",
 489         .main_clk       = "trace_clk_div_ck",
 490         .prcm = {
 491                 .omap4 = {
 492                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 493                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 494                 },
 495         },
 496 };
 497
 498 /*
 499  * 'dma' class
 500  * dma controller for data exchange between memory to memory (i.e. internal or
 501  * external memory) and gp peripherals to memory or memory to gp peripherals
 502  */
 503
 504 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 505         .rev_offs       = 0x0000,
 506         .sysc_offs      = 0x002c,
 507         .syss_offs      = 0x0028,
 508         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 509                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 510                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 511                            SYSS_HAS_RESET_STATUS),
 512         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 513                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 514         .sysc_fields    = &omap_hwmod_sysc_type1,
 515 };
 516
 517 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 518         .name   = "dma",
 519         .sysc   = &omap44xx_dma_sysc,
 520 };
 521
 522 /* dma dev_attr */
 523 static struct omap_dma_dev_attr dma_dev_attr = {
 524         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 525                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 526         .lch_count      = 32,
 527 };
 528
 529 /* dma_system */
 530 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 531         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 532         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 533         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 534         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 535         { .irq = -1 }
 536 };
 537
 538 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 539         .name           = "dma_system",
 540         .class          = &omap44xx_dma_hwmod_class,
 541         .clkdm_name     = "l3_dma_clkdm",
 542         .mpu_irqs       = omap44xx_dma_system_irqs,
 543         .main_clk       = "l3_div_ck",
 544         .prcm = {
 545                 .omap4 = {
 546                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 547                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 548                 },
 549         },
 550         .dev_attr       = &dma_dev_attr,
 551 };
 552
 553 /*
 554  * 'dmic' class
 555  * digital microphone controller
 556  */
 557
 558 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 559         .rev_offs       = 0x0000,
 560         .sysc_offs      = 0x0010,
 561         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 562                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 564                            SIDLE_SMART_WKUP),
 565         .sysc_fields    = &omap_hwmod_sysc_type2,
 566 };
 567
 568 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 569         .name   = "dmic",
 570         .sysc   = &omap44xx_dmic_sysc,
 571 };
 572
 573 /* dmic */
 574 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 575         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 576         { .irq = -1 }
 577 };
 578
 579 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 580         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 581         { .dma_req = -1 }
 582 };
 583
 584 static struct omap_hwmod omap44xx_dmic_hwmod = {
 585         .name           = "dmic",
 586         .class          = &omap44xx_dmic_hwmod_class,
 587         .clkdm_name     = "abe_clkdm",
 588         .mpu_irqs       = omap44xx_dmic_irqs,
 589         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 590         .main_clk       = "dmic_fck",
 591         .prcm = {
 592                 .omap4 = {
 593                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 594                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 595                         .modulemode   = MODULEMODE_SWCTRL,
 596                 },
 597         },
 598 };
 599
 600 /*
 601  * 'dsp' class
 602  * dsp sub-system
 603  */
 604
 605 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 606         .name   = "dsp",
 607 };
 608
 609 /* dsp */
 610 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 611         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 612         { .irq = -1 }
 613 };
 614
 615 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 616         { .name = "dsp", .rst_shift = 0 },
 617         { .name = "mmu_cache", .rst_shift = 1 },
 618 };
 619
 620 static struct omap_hwmod omap44xx_dsp_hwmod = {
 621         .name           = "dsp",
 622         .class          = &omap44xx_dsp_hwmod_class,
 623         .clkdm_name     = "tesla_clkdm",
 624         .mpu_irqs       = omap44xx_dsp_irqs,
 625         .rst_lines      = omap44xx_dsp_resets,
 626         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 627         .main_clk       = "dsp_fck",
 628         .prcm = {
 629                 .omap4 = {
 630                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 631                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 632                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 633                         .modulemode   = MODULEMODE_HWCTRL,
 634                 },
 635         },
 636 };
 637
 638 /*
 639  * 'dss' class
 640  * display sub-system
 641  */
 642
 643 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 644         .rev_offs       = 0x0000,
 645         .syss_offs      = 0x0014,
 646         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 647 };
 648
 649 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 650         .name   = "dss",
 651         .sysc   = &omap44xx_dss_sysc,
 652         .reset  = omap_dss_reset,
 653 };
 654
 655 /* dss */
 656 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 657         { .role = "sys_clk", .clk = "dss_sys_clk" },
 658         { .role = "tv_clk", .clk = "dss_tv_clk" },
 659         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 660 };
 661
 662 static struct omap_hwmod omap44xx_dss_hwmod = {
 663         .name           = "dss_core",
 664         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 665         .class          = &omap44xx_dss_hwmod_class,
 666         .clkdm_name     = "l3_dss_clkdm",
 667         .main_clk       = "dss_dss_clk",
 668         .prcm = {
 669                 .omap4 = {
 670                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 671                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 672                 },
 673         },
 674         .opt_clks       = dss_opt_clks,
 675         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 676 };
 677
 678 /*
 679  * 'dispc' class
 680  * display controller
 681  */
 682
 683 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 684         .rev_offs       = 0x0000,
 685         .sysc_offs      = 0x0010,
 686         .syss_offs      = 0x0014,
 687         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 688                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 689                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 690                            SYSS_HAS_RESET_STATUS),
 691         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 692                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 693         .sysc_fields    = &omap_hwmod_sysc_type1,
 694 };
 695
 696 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 697         .name   = "dispc",
 698         .sysc   = &omap44xx_dispc_sysc,
 699 };
 700
 701 /* dss_dispc */
 702 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 703         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 704         { .irq = -1 }
 705 };
 706
 707 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 708         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 709         { .dma_req = -1 }
 710 };
 711
 712 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 713         .manager_count          = 3,
 714         .has_framedonetv_irq    = 1
 715 };
 716
 717 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 718         .name           = "dss_dispc",
 719         .class          = &omap44xx_dispc_hwmod_class,
 720         .clkdm_name     = "l3_dss_clkdm",
 721         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 722         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 723         .main_clk       = "dss_dss_clk",
 724         .prcm = {
 725                 .omap4 = {
 726                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 727                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 728                 },
 729         },
 730         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 731 };
 732
 733 /*
 734  * 'dsi' class
 735  * display serial interface controller
 736  */
 737
 738 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 739         .rev_offs       = 0x0000,
 740         .sysc_offs      = 0x0010,
 741         .syss_offs      = 0x0014,
 742         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 743                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 744                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 745         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 746         .sysc_fields    = &omap_hwmod_sysc_type1,
 747 };
 748
 749 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 750         .name   = "dsi",
 751         .sysc   = &omap44xx_dsi_sysc,
 752 };
 753
 754 /* dss_dsi1 */
 755 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 756         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 757         { .irq = -1 }
 758 };
 759
 760 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 761         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 762         { .dma_req = -1 }
 763 };
 764
 765 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 766         { .role = "sys_clk", .clk = "dss_sys_clk" },
 767 };
 768
 769 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 770         .name           = "dss_dsi1",
 771         .class          = &omap44xx_dsi_hwmod_class,
 772         .clkdm_name     = "l3_dss_clkdm",
 773         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 774         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 775         .main_clk       = "dss_dss_clk",
 776         .prcm = {
 777                 .omap4 = {
 778                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 779                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 780                 },
 781         },
 782         .opt_clks       = dss_dsi1_opt_clks,
 783         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 784 };
 785
 786 /* dss_dsi2 */
 787 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 788         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 789         { .irq = -1 }
 790 };
 791
 792 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 793         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 794         { .dma_req = -1 }
 795 };
 796
 797 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 798         { .role = "sys_clk", .clk = "dss_sys_clk" },
 799 };
 800
 801 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 802         .name           = "dss_dsi2",
 803         .class          = &omap44xx_dsi_hwmod_class,
 804         .clkdm_name     = "l3_dss_clkdm",
 805         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 806         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 807         .main_clk       = "dss_dss_clk",
 808         .prcm = {
 809                 .omap4 = {
 810                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 811                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 812                 },
 813         },
 814         .opt_clks       = dss_dsi2_opt_clks,
 815         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 816 };
 817
 818 /*
 819  * 'hdmi' class
 820  * hdmi controller
 821  */
 822
 823 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 824         .rev_offs       = 0x0000,
 825         .sysc_offs      = 0x0010,
 826         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 827                            SYSC_HAS_SOFTRESET),
 828         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 829                            SIDLE_SMART_WKUP),
 830         .sysc_fields    = &omap_hwmod_sysc_type2,
 831 };
 832
 833 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 834         .name   = "hdmi",
 835         .sysc   = &omap44xx_hdmi_sysc,
 836 };
 837
 838 /* dss_hdmi */
 839 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 840         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 841         { .irq = -1 }
 842 };
 843
 844 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 845         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 846         { .dma_req = -1 }
 847 };
 848
 849 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 850         { .role = "sys_clk", .clk = "dss_sys_clk" },
 851 };
 852
 853 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 854         .name           = "dss_hdmi",
 855         .class          = &omap44xx_hdmi_hwmod_class,
 856         .clkdm_name     = "l3_dss_clkdm",
 857         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 858         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 859         .main_clk       = "dss_48mhz_clk",
 860         .prcm = {
 861                 .omap4 = {
 862                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 863                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 864                 },
 865         },
 866         .opt_clks       = dss_hdmi_opt_clks,
 867         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 868 };
 869
 870 /*
 871  * 'rfbi' class
 872  * remote frame buffer interface
 873  */
 874
 875 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 876         .rev_offs       = 0x0000,
 877         .sysc_offs      = 0x0010,
 878         .syss_offs      = 0x0014,
 879         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 880                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 881         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 882         .sysc_fields    = &omap_hwmod_sysc_type1,
 883 };
 884
 885 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 886         .name   = "rfbi",
 887         .sysc   = &omap44xx_rfbi_sysc,
 888 };
 889
 890 /* dss_rfbi */
 891 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 892         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 893         { .dma_req = -1 }
 894 };
 895
 896 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 897         { .role = "ick", .clk = "dss_fck" },
 898 };
 899
 900 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 901         .name           = "dss_rfbi",
 902         .class          = &omap44xx_rfbi_hwmod_class,
 903         .clkdm_name     = "l3_dss_clkdm",
 904         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 905         .main_clk       = "dss_dss_clk",
 906         .prcm = {
 907                 .omap4 = {
 908                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 909                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 910                 },
 911         },
 912         .opt_clks       = dss_rfbi_opt_clks,
 913         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 914 };
 915
 916 /*
 917  * 'venc' class
 918  * video encoder
 919  */
 920
 921 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 922         .name   = "venc",
 923 };
 924
 925 /* dss_venc */
 926 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 927         .name           = "dss_venc",
 928         .class          = &omap44xx_venc_hwmod_class,
 929         .clkdm_name     = "l3_dss_clkdm",
 930         .main_clk       = "dss_tv_clk",
 931         .prcm = {
 932                 .omap4 = {
 933                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 934                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 935                 },
 936         },
 937 };
 938
 939 /*
 940  * 'elm' class
 941  * bch error location module
 942  */
 943
 944 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 945         .rev_offs       = 0x0000,
 946         .sysc_offs      = 0x0010,
 947         .syss_offs      = 0x0014,
 948         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 949                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 950                            SYSS_HAS_RESET_STATUS),
 951         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 952         .sysc_fields    = &omap_hwmod_sysc_type1,
 953 };
 954
 955 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 956         .name   = "elm",
 957         .sysc   = &omap44xx_elm_sysc,
 958 };
 959
 960 /* elm */
 961 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 962         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 963         { .irq = -1 }
 964 };
 965
 966 static struct omap_hwmod omap44xx_elm_hwmod = {
 967         .name           = "elm",
 968         .class          = &omap44xx_elm_hwmod_class,
 969         .clkdm_name     = "l4_per_clkdm",
 970         .mpu_irqs       = omap44xx_elm_irqs,
 971         .prcm = {
 972                 .omap4 = {
 973                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 974                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 975                 },
 976         },
 977 };
 978
 979 /*
 980  * 'emif' class
 981  * external memory interface no1
 982  */
 983
 984 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 985         .rev_offs       = 0x0000,
 986 };
 987
 988 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 989         .name   = "emif",
 990         .sysc   = &omap44xx_emif_sysc,
 991 };
 992
 993 /* emif1 */
 994 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
 995         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
 996         { .irq = -1 }
 997 };
 998
 999 static struct omap_hwmod omap44xx_emif1_hwmod = {
1000         .name           = "emif1",
1001         .class          = &omap44xx_emif_hwmod_class,
1002         .clkdm_name     = "l3_emif_clkdm",
1003         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1004         .mpu_irqs       = omap44xx_emif1_irqs,
1005         .main_clk       = "ddrphy_ck",
1006         .prcm = {
1007                 .omap4 = {
1008                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1009                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1010                         .modulemode   = MODULEMODE_HWCTRL,
1011                 },
1012         },
1013 };
1014
1015 /* emif2 */
1016 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1017         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1018         { .irq = -1 }
1019 };
1020
1021 static struct omap_hwmod omap44xx_emif2_hwmod = {
1022         .name           = "emif2",
1023         .class          = &omap44xx_emif_hwmod_class,
1024         .clkdm_name     = "l3_emif_clkdm",
1025         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1026         .mpu_irqs       = omap44xx_emif2_irqs,
1027         .main_clk       = "ddrphy_ck",
1028         .prcm = {
1029                 .omap4 = {
1030                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1031                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1032                         .modulemode   = MODULEMODE_HWCTRL,
1033                 },
1034         },
1035 };
1036
1037 /*
1038  * 'fdif' class
1039  * face detection hw accelerator module
1040  */
1041
1042 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1043         .rev_offs       = 0x0000,
1044         .sysc_offs      = 0x0010,
1045         /*
1046          * FDIF needs 100 OCP clk cycles delay after a softreset before
1047          * accessing sysconfig again.
1048          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1049          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1050          *
1051          * TODO: Indicate errata when available.
1052          */
1053         .srst_udelay    = 2,
1054         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1055                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1056         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1057                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1058         .sysc_fields    = &omap_hwmod_sysc_type2,
1059 };
1060
1061 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1062         .name   = "fdif",
1063         .sysc   = &omap44xx_fdif_sysc,
1064 };
1065
1066 /* fdif */
1067 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1068         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1069         { .irq = -1 }
1070 };
1071
1072 static struct omap_hwmod omap44xx_fdif_hwmod = {
1073         .name           = "fdif",
1074         .class          = &omap44xx_fdif_hwmod_class,
1075         .clkdm_name     = "iss_clkdm",
1076         .mpu_irqs       = omap44xx_fdif_irqs,
1077         .main_clk       = "fdif_fck",
1078         .prcm = {
1079                 .omap4 = {
1080                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1081                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1082                         .modulemode   = MODULEMODE_SWCTRL,
1083                 },
1084         },
1085 };
1086
1087 /*
1088  * 'gpio' class
1089  * general purpose io module
1090  */
1091
1092 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1093         .rev_offs       = 0x0000,
1094         .sysc_offs      = 0x0010,
1095         .syss_offs      = 0x0114,
1096         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1097                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1098                            SYSS_HAS_RESET_STATUS),
1099         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1100                            SIDLE_SMART_WKUP),
1101         .sysc_fields    = &omap_hwmod_sysc_type1,
1102 };
1103
1104 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1105         .name   = "gpio",
1106         .sysc   = &omap44xx_gpio_sysc,
1107         .rev    = 2,
1108 };
1109
1110 /* gpio dev_attr */
1111 static struct omap_gpio_dev_attr gpio_dev_attr = {
1112         .bank_width     = 32,
1113         .dbck_flag      = true,
1114 };
1115
1116 /* gpio1 */
1117 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1118         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1119         { .irq = -1 }
1120 };
1121
1122 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1123         { .role = "dbclk", .clk = "gpio1_dbclk" },
1124 };
1125
1126 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1127         .name           = "gpio1",
1128         .class          = &omap44xx_gpio_hwmod_class,
1129         .clkdm_name     = "l4_wkup_clkdm",
1130         .mpu_irqs       = omap44xx_gpio1_irqs,
1131         .main_clk       = "gpio1_ick",
1132         .prcm = {
1133                 .omap4 = {
1134                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1135                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1136                         .modulemode   = MODULEMODE_HWCTRL,
1137                 },
1138         },
1139         .opt_clks       = gpio1_opt_clks,
1140         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1141         .dev_attr       = &gpio_dev_attr,
1142 };
1143
1144 /* gpio2 */
1145 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1146         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1147         { .irq = -1 }
1148 };
1149
1150 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1151         { .role = "dbclk", .clk = "gpio2_dbclk" },
1152 };
1153
1154 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1155         .name           = "gpio2",
1156         .class          = &omap44xx_gpio_hwmod_class,
1157         .clkdm_name     = "l4_per_clkdm",
1158         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1159         .mpu_irqs       = omap44xx_gpio2_irqs,
1160         .main_clk       = "gpio2_ick",
1161         .prcm = {
1162                 .omap4 = {
1163                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1164                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1165                         .modulemode   = MODULEMODE_HWCTRL,
1166                 },
1167         },
1168         .opt_clks       = gpio2_opt_clks,
1169         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1170         .dev_attr       = &gpio_dev_attr,
1171 };
1172
1173 /* gpio3 */
1174 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1175         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1176         { .irq = -1 }
1177 };
1178
1179 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1180         { .role = "dbclk", .clk = "gpio3_dbclk" },
1181 };
1182
1183 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1184         .name           = "gpio3",
1185         .class          = &omap44xx_gpio_hwmod_class,
1186         .clkdm_name     = "l4_per_clkdm",
1187         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1188         .mpu_irqs       = omap44xx_gpio3_irqs,
1189         .main_clk       = "gpio3_ick",
1190         .prcm = {
1191                 .omap4 = {
1192                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1193                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1194                         .modulemode   = MODULEMODE_HWCTRL,
1195                 },
1196         },
1197         .opt_clks       = gpio3_opt_clks,
1198         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1199         .dev_attr       = &gpio_dev_attr,
1200 };
1201
1202 /* gpio4 */
1203 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1204         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1205         { .irq = -1 }
1206 };
1207
1208 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1209         { .role = "dbclk", .clk = "gpio4_dbclk" },
1210 };
1211
1212 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1213         .name           = "gpio4",
1214         .class          = &omap44xx_gpio_hwmod_class,
1215         .clkdm_name     = "l4_per_clkdm",
1216         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1217         .mpu_irqs       = omap44xx_gpio4_irqs,
1218         .main_clk       = "gpio4_ick",
1219         .prcm = {
1220                 .omap4 = {
1221                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1222                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1223                         .modulemode   = MODULEMODE_HWCTRL,
1224                 },
1225         },
1226         .opt_clks       = gpio4_opt_clks,
1227         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1228         .dev_attr       = &gpio_dev_attr,
1229 };
1230
1231 /* gpio5 */
1232 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1233         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1234         { .irq = -1 }
1235 };
1236
1237 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1238         { .role = "dbclk", .clk = "gpio5_dbclk" },
1239 };
1240
1241 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1242         .name           = "gpio5",
1243         .class          = &omap44xx_gpio_hwmod_class,
1244         .clkdm_name     = "l4_per_clkdm",
1245         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1246         .mpu_irqs       = omap44xx_gpio5_irqs,
1247         .main_clk       = "gpio5_ick",
1248         .prcm = {
1249                 .omap4 = {
1250                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1251                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1252                         .modulemode   = MODULEMODE_HWCTRL,
1253                 },
1254         },
1255         .opt_clks       = gpio5_opt_clks,
1256         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1257         .dev_attr       = &gpio_dev_attr,
1258 };
1259
1260 /* gpio6 */
1261 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1262         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1263         { .irq = -1 }
1264 };
1265
1266 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1267         { .role = "dbclk", .clk = "gpio6_dbclk" },
1268 };
1269
1270 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1271         .name           = "gpio6",
1272         .class          = &omap44xx_gpio_hwmod_class,
1273         .clkdm_name     = "l4_per_clkdm",
1274         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1275         .mpu_irqs       = omap44xx_gpio6_irqs,
1276         .main_clk       = "gpio6_ick",
1277         .prcm = {
1278                 .omap4 = {
1279                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1280                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1281                         .modulemode   = MODULEMODE_HWCTRL,
1282                 },
1283         },
1284         .opt_clks       = gpio6_opt_clks,
1285         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1286         .dev_attr       = &gpio_dev_attr,
1287 };
1288
1289 /*
1290  * 'gpmc' class
1291  * general purpose memory controller
1292  */
1293
1294 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1295         .rev_offs       = 0x0000,
1296         .sysc_offs      = 0x0010,
1297         .syss_offs      = 0x0014,
1298         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1299                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1300         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1301         .sysc_fields    = &omap_hwmod_sysc_type1,
1302 };
1303
1304 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1305         .name   = "gpmc",
1306         .sysc   = &omap44xx_gpmc_sysc,
1307 };
1308
1309 /* gpmc */
1310 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1311         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1312         { .irq = -1 }
1313 };
1314
1315 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1316         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1317         { .dma_req = -1 }
1318 };
1319
1320 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1321         .name           = "gpmc",
1322         .class          = &omap44xx_gpmc_hwmod_class,
1323         .clkdm_name     = "l3_2_clkdm",
1324         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1325         .mpu_irqs       = omap44xx_gpmc_irqs,
1326         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1327         .prcm = {
1328                 .omap4 = {
1329                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1330                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1331                         .modulemode   = MODULEMODE_HWCTRL,
1332                 },
1333         },
1334 };
1335
1336 /*
1337  * 'gpu' class
1338  * 2d/3d graphics accelerator
1339  */
1340
1341 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1342         .rev_offs       = 0x1fc00,
1343         .sysc_offs      = 0x1fc10,
1344         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1345         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1346                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1347                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1348         .sysc_fields    = &omap_hwmod_sysc_type2,
1349 };
1350
1351 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1352         .name   = "gpu",
1353         .sysc   = &omap44xx_gpu_sysc,
1354 };
1355
1356 /* gpu */
1357 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1358         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1359         { .irq = -1 }
1360 };
1361
1362 static struct omap_hwmod omap44xx_gpu_hwmod = {
1363         .name           = "gpu",
1364         .class          = &omap44xx_gpu_hwmod_class,
1365         .clkdm_name     = "l3_gfx_clkdm",
1366         .mpu_irqs       = omap44xx_gpu_irqs,
1367         .main_clk       = "gpu_fck",
1368         .prcm = {
1369                 .omap4 = {
1370                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1371                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1372                         .modulemode   = MODULEMODE_SWCTRL,
1373                 },
1374         },
1375 };
1376
1377 /*
1378  * 'hdq1w' class
1379  * hdq / 1-wire serial interface controller
1380  */
1381
1382 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1383         .rev_offs       = 0x0000,
1384         .sysc_offs      = 0x0014,
1385         .syss_offs      = 0x0018,
1386         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1387                            SYSS_HAS_RESET_STATUS),
1388         .sysc_fields    = &omap_hwmod_sysc_type1,
1389 };
1390
1391 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1392         .name   = "hdq1w",
1393         .sysc   = &omap44xx_hdq1w_sysc,
1394 };
1395
1396 /* hdq1w */
1397 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1398         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1399         { .irq = -1 }
1400 };
1401
1402 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1403         .name           = "hdq1w",
1404         .class          = &omap44xx_hdq1w_hwmod_class,
1405         .clkdm_name     = "l4_per_clkdm",
1406         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1407         .mpu_irqs       = omap44xx_hdq1w_irqs,
1408         .main_clk       = "hdq1w_fck",
1409         .prcm = {
1410                 .omap4 = {
1411                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1412                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_SWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'hsi' class
1420  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1421  * serial if)
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0010,
1427         .syss_offs      = 0x0014,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1429                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1430                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1432                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1433                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1434         .sysc_fields    = &omap_hwmod_sysc_type1,
1435 };
1436
1437 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1438         .name   = "hsi",
1439         .sysc   = &omap44xx_hsi_sysc,
1440 };
1441
1442 /* hsi */
1443 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1444         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1445         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1446         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1447         { .irq = -1 }
1448 };
1449
1450 static struct omap_hwmod omap44xx_hsi_hwmod = {
1451         .name           = "hsi",
1452         .class          = &omap44xx_hsi_hwmod_class,
1453         .clkdm_name     = "l3_init_clkdm",
1454         .mpu_irqs       = omap44xx_hsi_irqs,
1455         .main_clk       = "hsi_fck",
1456         .prcm = {
1457                 .omap4 = {
1458                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1459                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1460                         .modulemode   = MODULEMODE_HWCTRL,
1461                 },
1462         },
1463 };
1464
1465 /*
1466  * 'i2c' class
1467  * multimaster high-speed i2c controller
1468  */
1469
1470 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1471         .sysc_offs      = 0x0010,
1472         .syss_offs      = 0x0090,
1473         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1474                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1475                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1476         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1477                            SIDLE_SMART_WKUP),
1478         .clockact       = CLOCKACT_TEST_ICLK,
1479         .sysc_fields    = &omap_hwmod_sysc_type1,
1480 };
1481
1482 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1483         .name   = "i2c",
1484         .sysc   = &omap44xx_i2c_sysc,
1485         .rev    = OMAP_I2C_IP_VERSION_2,
1486         .reset  = &omap_i2c_reset,
1487 };
1488
1489 static struct omap_i2c_dev_attr i2c_dev_attr = {
1490         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1491                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1492 };
1493
1494 /* i2c1 */
1495 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1496         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1497         { .irq = -1 }
1498 };
1499
1500 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1501         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1502         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1503         { .dma_req = -1 }
1504 };
1505
1506 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1507         .name           = "i2c1",
1508         .class          = &omap44xx_i2c_hwmod_class,
1509         .clkdm_name     = "l4_per_clkdm",
1510         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1511         .mpu_irqs       = omap44xx_i2c1_irqs,
1512         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1513         .main_clk       = "i2c1_fck",
1514         .prcm = {
1515                 .omap4 = {
1516                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1517                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1518                         .modulemode   = MODULEMODE_SWCTRL,
1519                 },
1520         },
1521         .dev_attr       = &i2c_dev_attr,
1522 };
1523
1524 /* i2c2 */
1525 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1526         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1527         { .irq = -1 }
1528 };
1529
1530 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1531         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1532         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1533         { .dma_req = -1 }
1534 };
1535
1536 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1537         .name           = "i2c2",
1538         .class          = &omap44xx_i2c_hwmod_class,
1539         .clkdm_name     = "l4_per_clkdm",
1540         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1541         .mpu_irqs       = omap44xx_i2c2_irqs,
1542         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1543         .main_clk       = "i2c2_fck",
1544         .prcm = {
1545                 .omap4 = {
1546                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1547                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1548                         .modulemode   = MODULEMODE_SWCTRL,
1549                 },
1550         },
1551         .dev_attr       = &i2c_dev_attr,
1552 };
1553
1554 /* i2c3 */
1555 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1556         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1557         { .irq = -1 }
1558 };
1559
1560 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1561         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1562         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1563         { .dma_req = -1 }
1564 };
1565
1566 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1567         .name           = "i2c3",
1568         .class          = &omap44xx_i2c_hwmod_class,
1569         .clkdm_name     = "l4_per_clkdm",
1570         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1571         .mpu_irqs       = omap44xx_i2c3_irqs,
1572         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1573         .main_clk       = "i2c3_fck",
1574         .prcm = {
1575                 .omap4 = {
1576                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1577                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1578                         .modulemode   = MODULEMODE_SWCTRL,
1579                 },
1580         },
1581         .dev_attr       = &i2c_dev_attr,
1582 };
1583
1584 /* i2c4 */
1585 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1586         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1587         { .irq = -1 }
1588 };
1589
1590 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1591         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1592         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1593         { .dma_req = -1 }
1594 };
1595
1596 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1597         .name           = "i2c4",
1598         .class          = &omap44xx_i2c_hwmod_class,
1599         .clkdm_name     = "l4_per_clkdm",
1600         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1601         .mpu_irqs       = omap44xx_i2c4_irqs,
1602         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1603         .main_clk       = "i2c4_fck",
1604         .prcm = {
1605                 .omap4 = {
1606                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1607                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1608                         .modulemode   = MODULEMODE_SWCTRL,
1609                 },
1610         },
1611         .dev_attr       = &i2c_dev_attr,
1612 };
1613
1614 /*
1615  * 'ipu' class
1616  * imaging processor unit
1617  */
1618
1619 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1620         .name   = "ipu",
1621 };
1622
1623 /* ipu */
1624 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1625         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1626         { .irq = -1 }
1627 };
1628
1629 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1630         { .name = "cpu0", .rst_shift = 0 },
1631         { .name = "cpu1", .rst_shift = 1 },
1632         { .name = "mmu_cache", .rst_shift = 2 },
1633 };
1634
1635 static struct omap_hwmod omap44xx_ipu_hwmod = {
1636         .name           = "ipu",
1637         .class          = &omap44xx_ipu_hwmod_class,
1638         .clkdm_name     = "ducati_clkdm",
1639         .mpu_irqs       = omap44xx_ipu_irqs,
1640         .rst_lines      = omap44xx_ipu_resets,
1641         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1642         .main_clk       = "ipu_fck",
1643         .prcm = {
1644                 .omap4 = {
1645                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1646                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1648                         .modulemode   = MODULEMODE_HWCTRL,
1649                 },
1650         },
1651 };
1652
1653 /*
1654  * 'iss' class
1655  * external images sensor pixel data processor
1656  */
1657
1658 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1659         .rev_offs       = 0x0000,
1660         .sysc_offs      = 0x0010,
1661         /*
1662          * ISS needs 100 OCP clk cycles delay after a softreset before
1663          * accessing sysconfig again.
1664          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1665          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1666          *
1667          * TODO: Indicate errata when available.
1668          */
1669         .srst_udelay    = 2,
1670         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1671                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1672         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1673                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1674                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1675         .sysc_fields    = &omap_hwmod_sysc_type2,
1676 };
1677
1678 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1679         .name   = "iss",
1680         .sysc   = &omap44xx_iss_sysc,
1681 };
1682
1683 /* iss */
1684 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1685         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1686         { .irq = -1 }
1687 };
1688
1689 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1690         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1691         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1692         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1693         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1694         { .dma_req = -1 }
1695 };
1696
1697 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1698         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1699 };
1700
1701 static struct omap_hwmod omap44xx_iss_hwmod = {
1702         .name           = "iss",
1703         .class          = &omap44xx_iss_hwmod_class,
1704         .clkdm_name     = "iss_clkdm",
1705         .mpu_irqs       = omap44xx_iss_irqs,
1706         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1707         .main_clk       = "iss_fck",
1708         .prcm = {
1709                 .omap4 = {
1710                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1711                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1712                         .modulemode   = MODULEMODE_SWCTRL,
1713                 },
1714         },
1715         .opt_clks       = iss_opt_clks,
1716         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1717 };
1718
1719 /*
1720  * 'iva' class
1721  * multi-standard video encoder/decoder hardware accelerator
1722  */
1723
1724 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1725         .name   = "iva",
1726 };
1727
1728 /* iva */
1729 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1730         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1731         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1732         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1733         { .irq = -1 }
1734 };
1735
1736 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1737         { .name = "seq0", .rst_shift = 0 },
1738         { .name = "seq1", .rst_shift = 1 },
1739         { .name = "logic", .rst_shift = 2 },
1740 };
1741
1742 static struct omap_hwmod omap44xx_iva_hwmod = {
1743         .name           = "iva",
1744         .class          = &omap44xx_iva_hwmod_class,
1745         .clkdm_name     = "ivahd_clkdm",
1746         .mpu_irqs       = omap44xx_iva_irqs,
1747         .rst_lines      = omap44xx_iva_resets,
1748         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1749         .main_clk       = "iva_fck",
1750         .prcm = {
1751                 .omap4 = {
1752                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1753                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1754                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1755                         .modulemode   = MODULEMODE_HWCTRL,
1756                 },
1757         },
1758 };
1759
1760 /*
1761  * 'kbd' class
1762  * keyboard controller
1763  */
1764
1765 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1766         .rev_offs       = 0x0000,
1767         .sysc_offs      = 0x0010,
1768         .syss_offs      = 0x0014,
1769         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1770                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1771                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1772                            SYSS_HAS_RESET_STATUS),
1773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1774         .sysc_fields    = &omap_hwmod_sysc_type1,
1775 };
1776
1777 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1778         .name   = "kbd",
1779         .sysc   = &omap44xx_kbd_sysc,
1780 };
1781
1782 /* kbd */
1783 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1784         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1785         { .irq = -1 }
1786 };
1787
1788 static struct omap_hwmod omap44xx_kbd_hwmod = {
1789         .name           = "kbd",
1790         .class          = &omap44xx_kbd_hwmod_class,
1791         .clkdm_name     = "l4_wkup_clkdm",
1792         .mpu_irqs       = omap44xx_kbd_irqs,
1793         .main_clk       = "kbd_fck",
1794         .prcm = {
1795                 .omap4 = {
1796                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1797                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1798                         .modulemode   = MODULEMODE_SWCTRL,
1799                 },
1800         },
1801 };
1802
1803 /*
1804  * 'mailbox' class
1805  * mailbox module allowing communication between the on-chip processors using a
1806  * queued mailbox-interrupt mechanism.
1807  */
1808
1809 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1810         .rev_offs       = 0x0000,
1811         .sysc_offs      = 0x0010,
1812         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1813                            SYSC_HAS_SOFTRESET),
1814         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1815         .sysc_fields    = &omap_hwmod_sysc_type2,
1816 };
1817
1818 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1819         .name   = "mailbox",
1820         .sysc   = &omap44xx_mailbox_sysc,
1821 };
1822
1823 /* mailbox */
1824 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1825         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1826         { .irq = -1 }
1827 };
1828
1829 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1830         .name           = "mailbox",
1831         .class          = &omap44xx_mailbox_hwmod_class,
1832         .clkdm_name     = "l4_cfg_clkdm",
1833         .mpu_irqs       = omap44xx_mailbox_irqs,
1834         .prcm = {
1835                 .omap4 = {
1836                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1837                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1838                 },
1839         },
1840 };
1841
1842 /*
1843  * 'mcasp' class
1844  * multi-channel audio serial port controller
1845  */
1846
1847 /* The IP is not compliant to type1 / type2 scheme */
1848 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1849         .sidle_shift    = 0,
1850 };
1851
1852 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1853         .sysc_offs      = 0x0004,
1854         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1855         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1856                            SIDLE_SMART_WKUP),
1857         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1858 };
1859
1860 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1861         .name   = "mcasp",
1862         .sysc   = &omap44xx_mcasp_sysc,
1863 };
1864
1865 /* mcasp */
1866 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1867         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1868         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1869         { .irq = -1 }
1870 };
1871
1872 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1873         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1874         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1875         { .dma_req = -1 }
1876 };
1877
1878 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1879         .name           = "mcasp",
1880         .class          = &omap44xx_mcasp_hwmod_class,
1881         .clkdm_name     = "abe_clkdm",
1882         .mpu_irqs       = omap44xx_mcasp_irqs,
1883         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1884         .main_clk       = "mcasp_fck",
1885         .prcm = {
1886                 .omap4 = {
1887                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1888                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1889                         .modulemode   = MODULEMODE_SWCTRL,
1890                 },
1891         },
1892 };
1893
1894 /*
1895  * 'mcbsp' class
1896  * multi channel buffered serial port controller
1897  */
1898
1899 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1900         .sysc_offs      = 0x008c,
1901         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1902                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1903         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1904         .sysc_fields    = &omap_hwmod_sysc_type1,
1905 };
1906
1907 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1908         .name   = "mcbsp",
1909         .sysc   = &omap44xx_mcbsp_sysc,
1910         .rev    = MCBSP_CONFIG_TYPE4,
1911 };
1912
1913 /* mcbsp1 */
1914 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1915         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1916         { .irq = -1 }
1917 };
1918
1919 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1920         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1921         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1922         { .dma_req = -1 }
1923 };
1924
1925 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1926         { .role = "pad_fck", .clk = "pad_clks_ck" },
1927         { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
1928 };
1929
1930 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1931         .name           = "mcbsp1",
1932         .class          = &omap44xx_mcbsp_hwmod_class,
1933         .clkdm_name     = "abe_clkdm",
1934         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1935         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1936         .main_clk       = "mcbsp1_fck",
1937         .prcm = {
1938                 .omap4 = {
1939                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1940                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1941                         .modulemode   = MODULEMODE_SWCTRL,
1942                 },
1943         },
1944         .opt_clks       = mcbsp1_opt_clks,
1945         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1946 };
1947
1948 /* mcbsp2 */
1949 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1950         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1951         { .irq = -1 }
1952 };
1953
1954 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1955         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1956         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1957         { .dma_req = -1 }
1958 };
1959
1960 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1961         { .role = "pad_fck", .clk = "pad_clks_ck" },
1962         { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
1963 };
1964
1965 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1966         .name           = "mcbsp2",
1967         .class          = &omap44xx_mcbsp_hwmod_class,
1968         .clkdm_name     = "abe_clkdm",
1969         .mpu_irqs       = omap44xx_mcbsp2_irqs,
1970         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
1971         .main_clk       = "mcbsp2_fck",
1972         .prcm = {
1973                 .omap4 = {
1974                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1975                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1976                         .modulemode   = MODULEMODE_SWCTRL,
1977                 },
1978         },
1979         .opt_clks       = mcbsp2_opt_clks,
1980         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1981 };
1982
1983 /* mcbsp3 */
1984 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1985         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1986         { .irq = -1 }
1987 };
1988
1989 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1990         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1991         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1992         { .dma_req = -1 }
1993 };
1994
1995 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1996         { .role = "pad_fck", .clk = "pad_clks_ck" },
1997         { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
1998 };
1999
2000 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2001         .name           = "mcbsp3",
2002         .class          = &omap44xx_mcbsp_hwmod_class,
2003         .clkdm_name     = "abe_clkdm",
2004         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2005         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2006         .main_clk       = "mcbsp3_fck",
2007         .prcm = {
2008                 .omap4 = {
2009                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2010                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2011                         .modulemode   = MODULEMODE_SWCTRL,
2012                 },
2013         },
2014         .opt_clks       = mcbsp3_opt_clks,
2015         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2016 };
2017
2018 /* mcbsp4 */
2019 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2020         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2021         { .irq = -1 }
2022 };
2023
2024 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2025         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2026         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2027         { .dma_req = -1 }
2028 };
2029
2030 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2031         { .role = "pad_fck", .clk = "pad_clks_ck" },
2032         { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
2033 };
2034
2035 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2036         .name           = "mcbsp4",
2037         .class          = &omap44xx_mcbsp_hwmod_class,
2038         .clkdm_name     = "l4_per_clkdm",
2039         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2040         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2041         .main_clk       = "mcbsp4_fck",
2042         .prcm = {
2043                 .omap4 = {
2044                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2045                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2046                         .modulemode   = MODULEMODE_SWCTRL,
2047                 },
2048         },
2049         .opt_clks       = mcbsp4_opt_clks,
2050         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2051 };
2052
2053 /*
2054  * 'mcpdm' class
2055  * multi channel pdm controller (proprietary interface with phoenix power
2056  * ic)
2057  */
2058
2059 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2060         .rev_offs       = 0x0000,
2061         .sysc_offs      = 0x0010,
2062         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2063                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2064         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2065                            SIDLE_SMART_WKUP),
2066         .sysc_fields    = &omap_hwmod_sysc_type2,
2067 };
2068
2069 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2070         .name   = "mcpdm",
2071         .sysc   = &omap44xx_mcpdm_sysc,
2072 };
2073
2074 /* mcpdm */
2075 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2076         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2077         { .irq = -1 }
2078 };
2079
2080 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2081         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2082         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2083         { .dma_req = -1 }
2084 };
2085
2086 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2087         .name           = "mcpdm",
2088         .class          = &omap44xx_mcpdm_hwmod_class,
2089         .clkdm_name     = "abe_clkdm",
2090         .mpu_irqs       = omap44xx_mcpdm_irqs,
2091         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2092         .main_clk       = "mcpdm_fck",
2093         .prcm = {
2094                 .omap4 = {
2095                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2096                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2097                         .modulemode   = MODULEMODE_SWCTRL,
2098                 },
2099         },
2100 };
2101
2102 /*
2103  * 'mcspi' class
2104  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2105  * bus
2106  */
2107
2108 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2109         .rev_offs       = 0x0000,
2110         .sysc_offs      = 0x0010,
2111         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2112                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2113         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2114                            SIDLE_SMART_WKUP),
2115         .sysc_fields    = &omap_hwmod_sysc_type2,
2116 };
2117
2118 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2119         .name   = "mcspi",
2120         .sysc   = &omap44xx_mcspi_sysc,
2121         .rev    = OMAP4_MCSPI_REV,
2122 };
2123
2124 /* mcspi1 */
2125 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2126         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2127         { .irq = -1 }
2128 };
2129
2130 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2131         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2132         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2133         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2134         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2135         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2136         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2137         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2138         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2139         { .dma_req = -1 }
2140 };
2141
2142 /* mcspi1 dev_attr */
2143 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2144         .num_chipselect = 4,
2145 };
2146
2147 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2148         .name           = "mcspi1",
2149         .class          = &omap44xx_mcspi_hwmod_class,
2150         .clkdm_name     = "l4_per_clkdm",
2151         .mpu_irqs       = omap44xx_mcspi1_irqs,
2152         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2153         .main_clk       = "mcspi1_fck",
2154         .prcm = {
2155                 .omap4 = {
2156                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2157                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2158                         .modulemode   = MODULEMODE_SWCTRL,
2159                 },
2160         },
2161         .dev_attr       = &mcspi1_dev_attr,
2162 };
2163
2164 /* mcspi2 */
2165 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2166         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2167         { .irq = -1 }
2168 };
2169
2170 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2171         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2172         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2173         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2174         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2175         { .dma_req = -1 }
2176 };
2177
2178 /* mcspi2 dev_attr */
2179 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2180         .num_chipselect = 2,
2181 };
2182
2183 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2184         .name           = "mcspi2",
2185         .class          = &omap44xx_mcspi_hwmod_class,
2186         .clkdm_name     = "l4_per_clkdm",
2187         .mpu_irqs       = omap44xx_mcspi2_irqs,
2188         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2189         .main_clk       = "mcspi2_fck",
2190         .prcm = {
2191                 .omap4 = {
2192                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2193                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2194                         .modulemode   = MODULEMODE_SWCTRL,
2195                 },
2196         },
2197         .dev_attr       = &mcspi2_dev_attr,
2198 };
2199
2200 /* mcspi3 */
2201 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2202         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2203         { .irq = -1 }
2204 };
2205
2206 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2207         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2208         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2209         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2210         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2211         { .dma_req = -1 }
2212 };
2213
2214 /* mcspi3 dev_attr */
2215 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2216         .num_chipselect = 2,
2217 };
2218
2219 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2220         .name           = "mcspi3",
2221         .class          = &omap44xx_mcspi_hwmod_class,
2222         .clkdm_name     = "l4_per_clkdm",
2223         .mpu_irqs       = omap44xx_mcspi3_irqs,
2224         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2225         .main_clk       = "mcspi3_fck",
2226         .prcm = {
2227                 .omap4 = {
2228                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2229                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2230                         .modulemode   = MODULEMODE_SWCTRL,
2231                 },
2232         },
2233         .dev_attr       = &mcspi3_dev_attr,
2234 };
2235
2236 /* mcspi4 */
2237 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2238         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2239         { .irq = -1 }
2240 };
2241
2242 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2243         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2244         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2245         { .dma_req = -1 }
2246 };
2247
2248 /* mcspi4 dev_attr */
2249 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2250         .num_chipselect = 1,
2251 };
2252
2253 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2254         .name           = "mcspi4",
2255         .class          = &omap44xx_mcspi_hwmod_class,
2256         .clkdm_name     = "l4_per_clkdm",
2257         .mpu_irqs       = omap44xx_mcspi4_irqs,
2258         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2259         .main_clk       = "mcspi4_fck",
2260         .prcm = {
2261                 .omap4 = {
2262                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2263                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2264                         .modulemode   = MODULEMODE_SWCTRL,
2265                 },
2266         },
2267         .dev_attr       = &mcspi4_dev_attr,
2268 };
2269
2270 /*
2271  * 'mmc' class
2272  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2273  */
2274
2275 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2276         .rev_offs       = 0x0000,
2277         .sysc_offs      = 0x0010,
2278         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2279                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2280                            SYSC_HAS_SOFTRESET),
2281         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2282                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2283                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2284         .sysc_fields    = &omap_hwmod_sysc_type2,
2285 };
2286
2287 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2288         .name   = "mmc",
2289         .sysc   = &omap44xx_mmc_sysc,
2290 };
2291
2292 /* mmc1 */
2293 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2294         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2295         { .irq = -1 }
2296 };
2297
2298 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2299         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2300         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2301         { .dma_req = -1 }
2302 };
2303
2304 /* mmc1 dev_attr */
2305 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2306         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2307 };
2308
2309 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2310         .name           = "mmc1",
2311         .class          = &omap44xx_mmc_hwmod_class,
2312         .clkdm_name     = "l3_init_clkdm",
2313         .mpu_irqs       = omap44xx_mmc1_irqs,
2314         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2315         .main_clk       = "mmc1_fck",
2316         .prcm = {
2317                 .omap4 = {
2318                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2319                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2320                         .modulemode   = MODULEMODE_SWCTRL,
2321                 },
2322         },
2323         .dev_attr       = &mmc1_dev_attr,
2324 };
2325
2326 /* mmc2 */
2327 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2328         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2329         { .irq = -1 }
2330 };
2331
2332 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2333         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2334         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2335         { .dma_req = -1 }
2336 };
2337
2338 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2339         .name           = "mmc2",
2340         .class          = &omap44xx_mmc_hwmod_class,
2341         .clkdm_name     = "l3_init_clkdm",
2342         .mpu_irqs       = omap44xx_mmc2_irqs,
2343         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2344         .main_clk       = "mmc2_fck",
2345         .prcm = {
2346                 .omap4 = {
2347                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2348                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2349                         .modulemode   = MODULEMODE_SWCTRL,
2350                 },
2351         },
2352 };
2353
2354 /* mmc3 */
2355 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2356         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2357         { .irq = -1 }
2358 };
2359
2360 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2361         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2362         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2363         { .dma_req = -1 }
2364 };
2365
2366 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2367         .name           = "mmc3",
2368         .class          = &omap44xx_mmc_hwmod_class,
2369         .clkdm_name     = "l4_per_clkdm",
2370         .mpu_irqs       = omap44xx_mmc3_irqs,
2371         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2372         .main_clk       = "mmc3_fck",
2373         .prcm = {
2374                 .omap4 = {
2375                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2376                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2377                         .modulemode   = MODULEMODE_SWCTRL,
2378                 },
2379         },
2380 };
2381
2382 /* mmc4 */
2383 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2384         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2385         { .irq = -1 }
2386 };
2387
2388 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2389         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2390         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2391         { .dma_req = -1 }
2392 };
2393
2394 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2395         .name           = "mmc4",
2396         .class          = &omap44xx_mmc_hwmod_class,
2397         .clkdm_name     = "l4_per_clkdm",
2398         .mpu_irqs       = omap44xx_mmc4_irqs,
2399         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2400         .main_clk       = "mmc4_fck",
2401         .prcm = {
2402                 .omap4 = {
2403                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2404                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2405                         .modulemode   = MODULEMODE_SWCTRL,
2406                 },
2407         },
2408 };
2409
2410 /* mmc5 */
2411 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2412         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2413         { .irq = -1 }
2414 };
2415
2416 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2417         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2418         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2419         { .dma_req = -1 }
2420 };
2421
2422 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2423         .name           = "mmc5",
2424         .class          = &omap44xx_mmc_hwmod_class,
2425         .clkdm_name     = "l4_per_clkdm",
2426         .mpu_irqs       = omap44xx_mmc5_irqs,
2427         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2428         .main_clk       = "mmc5_fck",
2429         .prcm = {
2430                 .omap4 = {
2431                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2432                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2433                         .modulemode   = MODULEMODE_SWCTRL,
2434                 },
2435         },
2436 };
2437
2438 /*
2439  * 'mpu' class
2440  * mpu sub-system
2441  */
2442
2443 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2444         .name   = "mpu",
2445 };
2446
2447 /* mpu */
2448 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2449         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2450         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2451         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2452         { .irq = -1 }
2453 };
2454
2455 static struct omap_hwmod omap44xx_mpu_hwmod = {
2456         .name           = "mpu",
2457         .class          = &omap44xx_mpu_hwmod_class,
2458         .clkdm_name     = "mpuss_clkdm",
2459         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2460         .mpu_irqs       = omap44xx_mpu_irqs,
2461         .main_clk       = "dpll_mpu_m2_ck",
2462         .prcm = {
2463                 .omap4 = {
2464                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2465                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2466                 },
2467         },
2468 };
2469
2470 /*
2471  * 'ocmc_ram' class
2472  * top-level core on-chip ram
2473  */
2474
2475 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2476         .name   = "ocmc_ram",
2477 };
2478
2479 /* ocmc_ram */
2480 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2481         .name           = "ocmc_ram",
2482         .class          = &omap44xx_ocmc_ram_hwmod_class,
2483         .clkdm_name     = "l3_2_clkdm",
2484         .prcm = {
2485                 .omap4 = {
2486                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2487                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2488                 },
2489         },
2490 };
2491
2492 /*
2493  * 'ocp2scp' class
2494  * bridge to transform ocp interface protocol to scp (serial control port)
2495  * protocol
2496  */
2497
2498 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2499         .name   = "ocp2scp",
2500 };
2501
2502 /* ocp2scp_usb_phy */
2503 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2504         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2505 };
2506
2507 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2508         .name           = "ocp2scp_usb_phy",
2509         .class          = &omap44xx_ocp2scp_hwmod_class,
2510         .clkdm_name     = "l3_init_clkdm",
2511         .prcm = {
2512                 .omap4 = {
2513                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2514                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2515                         .modulemode   = MODULEMODE_HWCTRL,
2516                 },
2517         },
2518         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2519         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2520 };
2521
2522 /*
2523  * 'prcm' class
2524  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2525  * + clock manager 1 (in always on power domain) + local prm in mpu
2526  */
2527
2528 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2529         .name   = "prcm",
2530 };
2531
2532 /* prcm_mpu */
2533 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2534         .name           = "prcm_mpu",
2535         .class          = &omap44xx_prcm_hwmod_class,
2536         .clkdm_name     = "l4_wkup_clkdm",
2537 };
2538
2539 /* cm_core_aon */
2540 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2541         .name           = "cm_core_aon",
2542         .class          = &omap44xx_prcm_hwmod_class,
2543         .clkdm_name     = "cm_clkdm",
2544 };
2545
2546 /* cm_core */
2547 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2548         .name           = "cm_core",
2549         .class          = &omap44xx_prcm_hwmod_class,
2550         .clkdm_name     = "cm_clkdm",
2551 };
2552
2553 /* prm */
2554 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2555         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2556         { .irq = -1 }
2557 };
2558
2559 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2560         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2561         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2562 };
2563
2564 static struct omap_hwmod omap44xx_prm_hwmod = {
2565         .name           = "prm",
2566         .class          = &omap44xx_prcm_hwmod_class,
2567         .clkdm_name     = "prm_clkdm",
2568         .mpu_irqs       = omap44xx_prm_irqs,
2569         .rst_lines      = omap44xx_prm_resets,
2570         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2571 };
2572
2573 /*
2574  * 'scrm' class
2575  * system clock and reset manager
2576  */
2577
2578 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2579         .name   = "scrm",
2580 };
2581
2582 /* scrm */
2583 static struct omap_hwmod omap44xx_scrm_hwmod = {
2584         .name           = "scrm",
2585         .class          = &omap44xx_scrm_hwmod_class,
2586         .clkdm_name     = "l4_wkup_clkdm",
2587 };
2588
2589 /*
2590  * 'sl2if' class
2591  * shared level 2 memory interface
2592  */
2593
2594 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2595         .name   = "sl2if",
2596 };
2597
2598 /* sl2if */
2599 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2600         .name           = "sl2if",
2601         .class          = &omap44xx_sl2if_hwmod_class,
2602         .clkdm_name     = "ivahd_clkdm",
2603         .prcm = {
2604                 .omap4 = {
2605                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2606                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2607                         .modulemode   = MODULEMODE_HWCTRL,
2608                 },
2609         },
2610 };
2611
2612 /*
2613  * 'slimbus' class
2614  * bidirectional, multi-drop, multi-channel two-line serial interface between
2615  * the device and external components
2616  */
2617
2618 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2619         .rev_offs       = 0x0000,
2620         .sysc_offs      = 0x0010,
2621         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2622                            SYSC_HAS_SOFTRESET),
2623         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2624                            SIDLE_SMART_WKUP),
2625         .sysc_fields    = &omap_hwmod_sysc_type2,
2626 };
2627
2628 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2629         .name   = "slimbus",
2630         .sysc   = &omap44xx_slimbus_sysc,
2631 };
2632
2633 /* slimbus1 */
2634 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2635         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2636         { .irq = -1 }
2637 };
2638
2639 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2640         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2641         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2642         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2643         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2644         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2645         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2646         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2647         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2648         { .dma_req = -1 }
2649 };
2650
2651 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2652         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2653         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2654         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2655         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2656 };
2657
2658 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2659         .name           = "slimbus1",
2660         .class          = &omap44xx_slimbus_hwmod_class,
2661         .clkdm_name     = "abe_clkdm",
2662         .mpu_irqs       = omap44xx_slimbus1_irqs,
2663         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2664         .prcm = {
2665                 .omap4 = {
2666                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2667                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2668                         .modulemode   = MODULEMODE_SWCTRL,
2669                 },
2670         },
2671         .opt_clks       = slimbus1_opt_clks,
2672         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2673 };
2674
2675 /* slimbus2 */
2676 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2677         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2678         { .irq = -1 }
2679 };
2680
2681 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2682         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2683         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2684         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2685         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2686         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2687         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2688         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2689         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2690         { .dma_req = -1 }
2691 };
2692
2693 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2694         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2695         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2696         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2697 };
2698
2699 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2700         .name           = "slimbus2",
2701         .class          = &omap44xx_slimbus_hwmod_class,
2702         .clkdm_name     = "l4_per_clkdm",
2703         .mpu_irqs       = omap44xx_slimbus2_irqs,
2704         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2705         .prcm = {
2706                 .omap4 = {
2707                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2708                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2709                         .modulemode   = MODULEMODE_SWCTRL,
2710                 },
2711         },
2712         .opt_clks       = slimbus2_opt_clks,
2713         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2714 };
2715
2716 /*
2717  * 'smartreflex' class
2718  * smartreflex module (monitor silicon performance and outputs a measure of
2719  * performance error)
2720  */
2721
2722 /* The IP is not compliant to type1 / type2 scheme */
2723 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2724         .sidle_shift    = 24,
2725         .enwkup_shift   = 26,
2726 };
2727
2728 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2729         .sysc_offs      = 0x0038,
2730         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2731         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2732                            SIDLE_SMART_WKUP),
2733         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2734 };
2735
2736 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2737         .name   = "smartreflex",
2738         .sysc   = &omap44xx_smartreflex_sysc,
2739         .rev    = 2,
2740 };
2741
2742 /* smartreflex_core */
2743 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2744         .sensor_voltdm_name   = "core",
2745 };
2746
2747 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2748         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2749         { .irq = -1 }
2750 };
2751
2752 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2753         .name           = "smartreflex_core",
2754         .class          = &omap44xx_smartreflex_hwmod_class,
2755         .clkdm_name     = "l4_ao_clkdm",
2756         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2757
2758         .main_clk       = "smartreflex_core_fck",
2759         .prcm = {
2760                 .omap4 = {
2761                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2762                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2763                         .modulemode   = MODULEMODE_SWCTRL,
2764                 },
2765         },
2766         .dev_attr       = &smartreflex_core_dev_attr,
2767 };
2768
2769 /* smartreflex_iva */
2770 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2771         .sensor_voltdm_name     = "iva",
2772 };
2773
2774 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2775         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2776         { .irq = -1 }
2777 };
2778
2779 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2780         .name           = "smartreflex_iva",
2781         .class          = &omap44xx_smartreflex_hwmod_class,
2782         .clkdm_name     = "l4_ao_clkdm",
2783         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2784         .main_clk       = "smartreflex_iva_fck",
2785         .prcm = {
2786                 .omap4 = {
2787                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2788                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2789                         .modulemode   = MODULEMODE_SWCTRL,
2790                 },
2791         },
2792         .dev_attr       = &smartreflex_iva_dev_attr,
2793 };
2794
2795 /* smartreflex_mpu */
2796 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2797         .sensor_voltdm_name     = "mpu",
2798 };
2799
2800 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2801         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2802         { .irq = -1 }
2803 };
2804
2805 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2806         .name           = "smartreflex_mpu",
2807         .class          = &omap44xx_smartreflex_hwmod_class,
2808         .clkdm_name     = "l4_ao_clkdm",
2809         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2810         .main_clk       = "smartreflex_mpu_fck",
2811         .prcm = {
2812                 .omap4 = {
2813                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2814                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2815                         .modulemode   = MODULEMODE_SWCTRL,
2816                 },
2817         },
2818         .dev_attr       = &smartreflex_mpu_dev_attr,
2819 };
2820
2821 /*
2822  * 'spinlock' class
2823  * spinlock provides hardware assistance for synchronizing the processes
2824  * running on multiple processors
2825  */
2826
2827 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2828         .rev_offs       = 0x0000,
2829         .sysc_offs      = 0x0010,
2830         .syss_offs      = 0x0014,
2831         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2832                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2833                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2834         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2835                            SIDLE_SMART_WKUP),
2836         .sysc_fields    = &omap_hwmod_sysc_type1,
2837 };
2838
2839 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2840         .name   = "spinlock",
2841         .sysc   = &omap44xx_spinlock_sysc,
2842 };
2843
2844 /* spinlock */
2845 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2846         .name           = "spinlock",
2847         .class          = &omap44xx_spinlock_hwmod_class,
2848         .clkdm_name     = "l4_cfg_clkdm",
2849         .prcm = {
2850                 .omap4 = {
2851                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2852                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2853                 },
2854         },
2855 };
2856
2857 /*
2858  * 'timer' class
2859  * general purpose timer module with accurate 1ms tick
2860  * This class contains several variants: ['timer_1ms', 'timer']
2861  */
2862
2863 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2864         .rev_offs       = 0x0000,
2865         .sysc_offs      = 0x0010,
2866         .syss_offs      = 0x0014,
2867         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2868                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2869                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2870                            SYSS_HAS_RESET_STATUS),
2871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2872         .sysc_fields    = &omap_hwmod_sysc_type1,
2873 };
2874
2875 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2876         .name   = "timer",
2877         .sysc   = &omap44xx_timer_1ms_sysc,
2878 };
2879
2880 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2881         .rev_offs       = 0x0000,
2882         .sysc_offs      = 0x0010,
2883         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2884                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2885         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2886                            SIDLE_SMART_WKUP),
2887         .sysc_fields    = &omap_hwmod_sysc_type2,
2888 };
2889
2890 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2891         .name   = "timer",
2892         .sysc   = &omap44xx_timer_sysc,
2893 };
2894
2895 /* always-on timers dev attribute */
2896 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2897         .timer_capability       = OMAP_TIMER_ALWON,
2898 };
2899
2900 /* pwm timers dev attribute */
2901 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2902         .timer_capability       = OMAP_TIMER_HAS_PWM,
2903 };
2904
2905 /* timer1 */
2906 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2907         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2908         { .irq = -1 }
2909 };
2910
2911 static struct omap_hwmod omap44xx_timer1_hwmod = {
2912         .name           = "timer1",
2913         .class          = &omap44xx_timer_1ms_hwmod_class,
2914         .clkdm_name     = "l4_wkup_clkdm",
2915         .mpu_irqs       = omap44xx_timer1_irqs,
2916         .main_clk       = "timer1_fck",
2917         .prcm = {
2918                 .omap4 = {
2919                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2920                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2921                         .modulemode   = MODULEMODE_SWCTRL,
2922                 },
2923         },
2924         .dev_attr       = &capability_alwon_dev_attr,
2925 };
2926
2927 /* timer2 */
2928 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2929         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2930         { .irq = -1 }
2931 };
2932
2933 static struct omap_hwmod omap44xx_timer2_hwmod = {
2934         .name           = "timer2",
2935         .class          = &omap44xx_timer_1ms_hwmod_class,
2936         .clkdm_name     = "l4_per_clkdm",
2937         .mpu_irqs       = omap44xx_timer2_irqs,
2938         .main_clk       = "timer2_fck",
2939         .prcm = {
2940                 .omap4 = {
2941                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2942                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2943                         .modulemode   = MODULEMODE_SWCTRL,
2944                 },
2945         },
2946         .dev_attr       = &capability_alwon_dev_attr,
2947 };
2948
2949 /* timer3 */
2950 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2951         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2952         { .irq = -1 }
2953 };
2954
2955 static struct omap_hwmod omap44xx_timer3_hwmod = {
2956         .name           = "timer3",
2957         .class          = &omap44xx_timer_hwmod_class,
2958         .clkdm_name     = "l4_per_clkdm",
2959         .mpu_irqs       = omap44xx_timer3_irqs,
2960         .main_clk       = "timer3_fck",
2961         .prcm = {
2962                 .omap4 = {
2963                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2964                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2965                         .modulemode   = MODULEMODE_SWCTRL,
2966                 },
2967         },
2968         .dev_attr       = &capability_alwon_dev_attr,
2969 };
2970
2971 /* timer4 */
2972 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2973         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2974         { .irq = -1 }
2975 };
2976
2977 static struct omap_hwmod omap44xx_timer4_hwmod = {
2978         .name           = "timer4",
2979         .class          = &omap44xx_timer_hwmod_class,
2980         .clkdm_name     = "l4_per_clkdm",
2981         .mpu_irqs       = omap44xx_timer4_irqs,
2982         .main_clk       = "timer4_fck",
2983         .prcm = {
2984                 .omap4 = {
2985                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2986                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2987                         .modulemode   = MODULEMODE_SWCTRL,
2988                 },
2989         },
2990         .dev_attr       = &capability_alwon_dev_attr,
2991 };
2992
2993 /* timer5 */
2994 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2995         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2996         { .irq = -1 }
2997 };
2998
2999 static struct omap_hwmod omap44xx_timer5_hwmod = {
3000         .name           = "timer5",
3001         .class          = &omap44xx_timer_hwmod_class,
3002         .clkdm_name     = "abe_clkdm",
3003         .mpu_irqs       = omap44xx_timer5_irqs,
3004         .main_clk       = "timer5_fck",
3005         .prcm = {
3006                 .omap4 = {
3007                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3008                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3009                         .modulemode   = MODULEMODE_SWCTRL,
3010                 },
3011         },
3012         .dev_attr       = &capability_alwon_dev_attr,
3013 };
3014
3015 /* timer6 */
3016 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3017         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3018         { .irq = -1 }
3019 };
3020
3021 static struct omap_hwmod omap44xx_timer6_hwmod = {
3022         .name           = "timer6",
3023         .class          = &omap44xx_timer_hwmod_class,
3024         .clkdm_name     = "abe_clkdm",
3025         .mpu_irqs       = omap44xx_timer6_irqs,
3026
3027         .main_clk       = "timer6_fck",
3028         .prcm = {
3029                 .omap4 = {
3030                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3031                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3032                         .modulemode   = MODULEMODE_SWCTRL,
3033                 },
3034         },
3035         .dev_attr       = &capability_alwon_dev_attr,
3036 };
3037
3038 /* timer7 */
3039 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3040         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3041         { .irq = -1 }
3042 };
3043
3044 static struct omap_hwmod omap44xx_timer7_hwmod = {
3045         .name           = "timer7",
3046         .class          = &omap44xx_timer_hwmod_class,
3047         .clkdm_name     = "abe_clkdm",
3048         .mpu_irqs       = omap44xx_timer7_irqs,
3049         .main_clk       = "timer7_fck",
3050         .prcm = {
3051                 .omap4 = {
3052                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3053                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3054                         .modulemode   = MODULEMODE_SWCTRL,
3055                 },
3056         },
3057         .dev_attr       = &capability_alwon_dev_attr,
3058 };
3059
3060 /* timer8 */
3061 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3062         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3063         { .irq = -1 }
3064 };
3065
3066 static struct omap_hwmod omap44xx_timer8_hwmod = {
3067         .name           = "timer8",
3068         .class          = &omap44xx_timer_hwmod_class,
3069         .clkdm_name     = "abe_clkdm",
3070         .mpu_irqs       = omap44xx_timer8_irqs,
3071         .main_clk       = "timer8_fck",
3072         .prcm = {
3073                 .omap4 = {
3074                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3075                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3076                         .modulemode   = MODULEMODE_SWCTRL,
3077                 },
3078         },
3079         .dev_attr       = &capability_pwm_dev_attr,
3080 };
3081
3082 /* timer9 */
3083 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3084         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3085         { .irq = -1 }
3086 };
3087
3088 static struct omap_hwmod omap44xx_timer9_hwmod = {
3089         .name           = "timer9",
3090         .class          = &omap44xx_timer_hwmod_class,
3091         .clkdm_name     = "l4_per_clkdm",
3092         .mpu_irqs       = omap44xx_timer9_irqs,
3093         .main_clk       = "timer9_fck",
3094         .prcm = {
3095                 .omap4 = {
3096                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3097                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3098                         .modulemode   = MODULEMODE_SWCTRL,
3099                 },
3100         },
3101         .dev_attr       = &capability_pwm_dev_attr,
3102 };
3103
3104 /* timer10 */
3105 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3106         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3107         { .irq = -1 }
3108 };
3109
3110 static struct omap_hwmod omap44xx_timer10_hwmod = {
3111         .name           = "timer10",
3112         .class          = &omap44xx_timer_1ms_hwmod_class,
3113         .clkdm_name     = "l4_per_clkdm",
3114         .mpu_irqs       = omap44xx_timer10_irqs,
3115         .main_clk       = "timer10_fck",
3116         .prcm = {
3117                 .omap4 = {
3118                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3119                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3120                         .modulemode   = MODULEMODE_SWCTRL,
3121                 },
3122         },
3123         .dev_attr       = &capability_pwm_dev_attr,
3124 };
3125
3126 /* timer11 */
3127 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3128         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3129         { .irq = -1 }
3130 };
3131
3132 static struct omap_hwmod omap44xx_timer11_hwmod = {
3133         .name           = "timer11",
3134         .class          = &omap44xx_timer_hwmod_class,
3135         .clkdm_name     = "l4_per_clkdm",
3136         .mpu_irqs       = omap44xx_timer11_irqs,
3137         .main_clk       = "timer11_fck",
3138         .prcm = {
3139                 .omap4 = {
3140                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3141                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3142                         .modulemode   = MODULEMODE_SWCTRL,
3143                 },
3144         },
3145         .dev_attr       = &capability_pwm_dev_attr,
3146 };
3147
3148 /*
3149  * 'uart' class
3150  * universal asynchronous receiver/transmitter (uart)
3151  */
3152
3153 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3154         .rev_offs       = 0x0050,
3155         .sysc_offs      = 0x0054,
3156         .syss_offs      = 0x0058,
3157         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3158                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3159                            SYSS_HAS_RESET_STATUS),
3160         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3161                            SIDLE_SMART_WKUP),
3162         .sysc_fields    = &omap_hwmod_sysc_type1,
3163 };
3164
3165 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3166         .name   = "uart",
3167         .sysc   = &omap44xx_uart_sysc,
3168 };
3169
3170 /* uart1 */
3171 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3172         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3173         { .irq = -1 }
3174 };
3175
3176 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3177         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3178         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3179         { .dma_req = -1 }
3180 };
3181
3182 static struct omap_hwmod omap44xx_uart1_hwmod = {
3183         .name           = "uart1",
3184         .class          = &omap44xx_uart_hwmod_class,
3185         .clkdm_name     = "l4_per_clkdm",
3186         .mpu_irqs       = omap44xx_uart1_irqs,
3187         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3188         .main_clk       = "uart1_fck",
3189         .prcm = {
3190                 .omap4 = {
3191                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3192                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3193                         .modulemode   = MODULEMODE_SWCTRL,
3194                 },
3195         },
3196 };
3197
3198 /* uart2 */
3199 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3200         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3201         { .irq = -1 }
3202 };
3203
3204 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3205         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3206         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3207         { .dma_req = -1 }
3208 };
3209
3210 static struct omap_hwmod omap44xx_uart2_hwmod = {
3211         .name           = "uart2",
3212         .class          = &omap44xx_uart_hwmod_class,
3213         .clkdm_name     = "l4_per_clkdm",
3214         .mpu_irqs       = omap44xx_uart2_irqs,
3215         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3216         .main_clk       = "uart2_fck",
3217         .prcm = {
3218                 .omap4 = {
3219                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3220                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3221                         .modulemode   = MODULEMODE_SWCTRL,
3222                 },
3223         },
3224 };
3225
3226 /* uart3 */
3227 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3228         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3229         { .irq = -1 }
3230 };
3231
3232 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3233         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3234         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3235         { .dma_req = -1 }
3236 };
3237
3238 static struct omap_hwmod omap44xx_uart3_hwmod = {
3239         .name           = "uart3",
3240         .class          = &omap44xx_uart_hwmod_class,
3241         .clkdm_name     = "l4_per_clkdm",
3242         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3243         .mpu_irqs       = omap44xx_uart3_irqs,
3244         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3245         .main_clk       = "uart3_fck",
3246         .prcm = {
3247                 .omap4 = {
3248                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3249                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3250                         .modulemode   = MODULEMODE_SWCTRL,
3251                 },
3252         },
3253 };
3254
3255 /* uart4 */
3256 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3257         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3258         { .irq = -1 }
3259 };
3260
3261 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3262         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3263         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3264         { .dma_req = -1 }
3265 };
3266
3267 static struct omap_hwmod omap44xx_uart4_hwmod = {
3268         .name           = "uart4",
3269         .class          = &omap44xx_uart_hwmod_class,
3270         .clkdm_name     = "l4_per_clkdm",
3271         .mpu_irqs       = omap44xx_uart4_irqs,
3272         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3273         .main_clk       = "uart4_fck",
3274         .prcm = {
3275                 .omap4 = {
3276                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3277                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3278                         .modulemode   = MODULEMODE_SWCTRL,
3279                 },
3280         },
3281 };
3282
3283 /*
3284  * 'usb_host_fs' class
3285  * full-speed usb host controller
3286  */
3287
3288 /* The IP is not compliant to type1 / type2 scheme */
3289 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3290         .midle_shift    = 4,
3291         .sidle_shift    = 2,
3292         .srst_shift     = 1,
3293 };
3294
3295 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3296         .rev_offs       = 0x0000,
3297         .sysc_offs      = 0x0210,
3298         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3299                            SYSC_HAS_SOFTRESET),
3300         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3301                            SIDLE_SMART_WKUP),
3302         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3303 };
3304
3305 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3306         .name   = "usb_host_fs",
3307         .sysc   = &omap44xx_usb_host_fs_sysc,
3308 };
3309
3310 /* usb_host_fs */
3311 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3312         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3313         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3314         { .irq = -1 }
3315 };
3316
3317 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3318         .name           = "usb_host_fs",
3319         .class          = &omap44xx_usb_host_fs_hwmod_class,
3320         .clkdm_name     = "l3_init_clkdm",
3321         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3322         .main_clk       = "usb_host_fs_fck",
3323         .prcm = {
3324                 .omap4 = {
3325                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3326                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3327                         .modulemode   = MODULEMODE_SWCTRL,
3328                 },
3329         },
3330 };
3331
3332 /*
3333  * 'usb_host_hs' class
3334  * high-speed multi-port usb host controller
3335  */
3336
3337 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3338         .rev_offs       = 0x0000,
3339         .sysc_offs      = 0x0010,
3340         .syss_offs      = 0x0014,
3341         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3342                            SYSC_HAS_SOFTRESET),
3343         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3344                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3345                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3346         .sysc_fields    = &omap_hwmod_sysc_type2,
3347 };
3348
3349 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3350         .name   = "usb_host_hs",
3351         .sysc   = &omap44xx_usb_host_hs_sysc,
3352 };
3353
3354 /* usb_host_hs */
3355 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3356         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3357         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3358         { .irq = -1 }
3359 };
3360
3361 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3362         .name           = "usb_host_hs",
3363         .class          = &omap44xx_usb_host_hs_hwmod_class,
3364         .clkdm_name     = "l3_init_clkdm",
3365         .main_clk       = "usb_host_hs_fck",
3366         .prcm = {
3367                 .omap4 = {
3368                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3369                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3370                         .modulemode   = MODULEMODE_SWCTRL,
3371                 },
3372         },
3373         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3374
3375         /*
3376          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3377          * id: i660
3378          *
3379          * Description:
3380          * In the following configuration :
3381          * - USBHOST module is set to smart-idle mode
3382          * - PRCM asserts idle_req to the USBHOST module ( This typically
3383          *   happens when the system is going to a low power mode : all ports
3384          *   have been suspended, the master part of the USBHOST module has
3385          *   entered the standby state, and SW has cut the functional clocks)
3386          * - an USBHOST interrupt occurs before the module is able to answer
3387          *   idle_ack, typically a remote wakeup IRQ.
3388          * Then the USB HOST module will enter a deadlock situation where it
3389          * is no more accessible nor functional.
3390          *
3391          * Workaround:
3392          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3393          */
3394
3395         /*
3396          * Errata: USB host EHCI may stall when entering smart-standby mode
3397          * Id: i571
3398          *
3399          * Description:
3400          * When the USBHOST module is set to smart-standby mode, and when it is
3401          * ready to enter the standby state (i.e. all ports are suspended and
3402          * all attached devices are in suspend mode), then it can wrongly assert
3403          * the Mstandby signal too early while there are still some residual OCP
3404          * transactions ongoing. If this condition occurs, the internal state
3405          * machine may go to an undefined state and the USB link may be stuck
3406          * upon the next resume.
3407          *
3408          * Workaround:
3409          * Don't use smart standby; use only force standby,
3410          * hence HWMOD_SWSUP_MSTANDBY
3411          */
3412
3413         /*
3414          * During system boot; If the hwmod framework resets the module
3415          * the module will have smart idle settings; which can lead to deadlock
3416          * (above Errata Id:i660); so, dont reset the module during boot;
3417          * Use HWMOD_INIT_NO_RESET.
3418          */
3419
3420         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3421                           HWMOD_INIT_NO_RESET,
3422 };
3423
3424 /*
3425  * 'usb_otg_hs' class
3426  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3427  */
3428
3429 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3430         .rev_offs       = 0x0400,
3431         .sysc_offs      = 0x0404,
3432         .syss_offs      = 0x0408,
3433         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3434                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3435                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3436         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3437                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3438                            MSTANDBY_SMART),
3439         .sysc_fields    = &omap_hwmod_sysc_type1,
3440 };
3441
3442 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3443         .name   = "usb_otg_hs",
3444         .sysc   = &omap44xx_usb_otg_hs_sysc,
3445 };
3446
3447 /* usb_otg_hs */
3448 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3449         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3450         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3451         { .irq = -1 }
3452 };
3453
3454 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3455         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3456 };
3457
3458 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3459         .name           = "usb_otg_hs",
3460         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3461         .clkdm_name     = "l3_init_clkdm",
3462         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3463         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3464         .main_clk       = "usb_otg_hs_ick",
3465         .prcm = {
3466                 .omap4 = {
3467                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3468                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3469                         .modulemode   = MODULEMODE_HWCTRL,
3470                 },
3471         },
3472         .opt_clks       = usb_otg_hs_opt_clks,
3473         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3474 };
3475
3476 /*
3477  * 'usb_tll_hs' class
3478  * usb_tll_hs module is the adapter on the usb_host_hs ports
3479  */
3480
3481 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3482         .rev_offs       = 0x0000,
3483         .sysc_offs      = 0x0010,
3484         .syss_offs      = 0x0014,
3485         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3486                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3487                            SYSC_HAS_AUTOIDLE),
3488         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3489         .sysc_fields    = &omap_hwmod_sysc_type1,
3490 };
3491
3492 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3493         .name   = "usb_tll_hs",
3494         .sysc   = &omap44xx_usb_tll_hs_sysc,
3495 };
3496
3497 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3498         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3499         { .irq = -1 }
3500 };
3501
3502 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3503         .name           = "usb_tll_hs",
3504         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3505         .clkdm_name     = "l3_init_clkdm",
3506         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3507         .main_clk       = "usb_tll_hs_ick",
3508         .prcm = {
3509                 .omap4 = {
3510                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3511                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3512                         .modulemode   = MODULEMODE_HWCTRL,
3513                 },
3514         },
3515 };
3516
3517 /*
3518  * 'wd_timer' class
3519  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3520  * overflow condition
3521  */
3522
3523 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3524         .rev_offs       = 0x0000,
3525         .sysc_offs      = 0x0010,
3526         .syss_offs      = 0x0014,
3527         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3528                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3529         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3530                            SIDLE_SMART_WKUP),
3531         .sysc_fields    = &omap_hwmod_sysc_type1,
3532 };
3533
3534 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3535         .name           = "wd_timer",
3536         .sysc           = &omap44xx_wd_timer_sysc,
3537         .pre_shutdown   = &omap2_wd_timer_disable,
3538         .reset          = &omap2_wd_timer_reset,
3539 };
3540
3541 /* wd_timer2 */
3542 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3543         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3544         { .irq = -1 }
3545 };
3546
3547 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3548         .name           = "wd_timer2",
3549         .class          = &omap44xx_wd_timer_hwmod_class,
3550         .clkdm_name     = "l4_wkup_clkdm",
3551         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3552         .main_clk       = "wd_timer2_fck",
3553         .prcm = {
3554                 .omap4 = {
3555                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3556                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3557                         .modulemode   = MODULEMODE_SWCTRL,
3558                 },
3559         },
3560 };
3561
3562 /* wd_timer3 */
3563 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3564         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3565         { .irq = -1 }
3566 };
3567
3568 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3569         .name           = "wd_timer3",
3570         .class          = &omap44xx_wd_timer_hwmod_class,
3571         .clkdm_name     = "abe_clkdm",
3572         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3573         .main_clk       = "wd_timer3_fck",
3574         .prcm = {
3575                 .omap4 = {
3576                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3577                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3578                         .modulemode   = MODULEMODE_SWCTRL,
3579                 },
3580         },
3581 };
3582
3583
3584 /*
3585  * interfaces
3586  */
3587
3588 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3589         {
3590                 .pa_start       = 0x4a204000,
3591                 .pa_end         = 0x4a2040ff,
3592                 .flags          = ADDR_TYPE_RT
3593         },
3594         { }
3595 };
3596
3597 /* c2c -> c2c_target_fw */
3598 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3599         .master         = &omap44xx_c2c_hwmod,
3600         .slave          = &omap44xx_c2c_target_fw_hwmod,
3601         .clk            = "div_core_ck",
3602         .addr           = omap44xx_c2c_target_fw_addrs,
3603         .user           = OCP_USER_MPU,
3604 };
3605
3606 /* l4_cfg -> c2c_target_fw */
3607 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3608         .master         = &omap44xx_l4_cfg_hwmod,
3609         .slave          = &omap44xx_c2c_target_fw_hwmod,
3610         .clk            = "l4_div_ck",
3611         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3612 };
3613
3614 /* l3_main_1 -> dmm */
3615 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3616         .master         = &omap44xx_l3_main_1_hwmod,
3617         .slave          = &omap44xx_dmm_hwmod,
3618         .clk            = "l3_div_ck",
3619         .user           = OCP_USER_SDMA,
3620 };
3621
3622 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3623         {
3624                 .pa_start       = 0x4e000000,
3625                 .pa_end         = 0x4e0007ff,
3626                 .flags          = ADDR_TYPE_RT
3627         },
3628         { }
3629 };
3630
3631 /* mpu -> dmm */
3632 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3633         .master         = &omap44xx_mpu_hwmod,
3634         .slave          = &omap44xx_dmm_hwmod,
3635         .clk            = "l3_div_ck",
3636         .addr           = omap44xx_dmm_addrs,
3637         .user           = OCP_USER_MPU,
3638 };
3639
3640 /* c2c -> emif_fw */
3641 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3642         .master         = &omap44xx_c2c_hwmod,
3643         .slave          = &omap44xx_emif_fw_hwmod,
3644         .clk            = "div_core_ck",
3645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3646 };
3647
3648 /* dmm -> emif_fw */
3649 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3650         .master         = &omap44xx_dmm_hwmod,
3651         .slave          = &omap44xx_emif_fw_hwmod,
3652         .clk            = "l3_div_ck",
3653         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3654 };
3655
3656 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3657         {
3658                 .pa_start       = 0x4a20c000,
3659                 .pa_end         = 0x4a20c0ff,
3660                 .flags          = ADDR_TYPE_RT
3661         },
3662         { }
3663 };
3664
3665 /* l4_cfg -> emif_fw */
3666 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3667         .master         = &omap44xx_l4_cfg_hwmod,
3668         .slave          = &omap44xx_emif_fw_hwmod,
3669         .clk            = "l4_div_ck",
3670         .addr           = omap44xx_emif_fw_addrs,
3671         .user           = OCP_USER_MPU,
3672 };
3673
3674 /* iva -> l3_instr */
3675 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3676         .master         = &omap44xx_iva_hwmod,
3677         .slave          = &omap44xx_l3_instr_hwmod,
3678         .clk            = "l3_div_ck",
3679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3680 };
3681
3682 /* l3_main_3 -> l3_instr */
3683 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3684         .master         = &omap44xx_l3_main_3_hwmod,
3685         .slave          = &omap44xx_l3_instr_hwmod,
3686         .clk            = "l3_div_ck",
3687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3688 };
3689
3690 /* ocp_wp_noc -> l3_instr */
3691 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3692         .master         = &omap44xx_ocp_wp_noc_hwmod,
3693         .slave          = &omap44xx_l3_instr_hwmod,
3694         .clk            = "l3_div_ck",
3695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3696 };
3697
3698 /* dsp -> l3_main_1 */
3699 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3700         .master         = &omap44xx_dsp_hwmod,
3701         .slave          = &omap44xx_l3_main_1_hwmod,
3702         .clk            = "l3_div_ck",
3703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3704 };
3705
3706 /* dss -> l3_main_1 */
3707 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3708         .master         = &omap44xx_dss_hwmod,
3709         .slave          = &omap44xx_l3_main_1_hwmod,
3710         .clk            = "l3_div_ck",
3711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3712 };
3713
3714 /* l3_main_2 -> l3_main_1 */
3715 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3716         .master         = &omap44xx_l3_main_2_hwmod,
3717         .slave          = &omap44xx_l3_main_1_hwmod,
3718         .clk            = "l3_div_ck",
3719         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3720 };
3721
3722 /* l4_cfg -> l3_main_1 */
3723 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3724         .master         = &omap44xx_l4_cfg_hwmod,
3725         .slave          = &omap44xx_l3_main_1_hwmod,
3726         .clk            = "l4_div_ck",
3727         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3728 };
3729
3730 /* mmc1 -> l3_main_1 */
3731 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3732         .master         = &omap44xx_mmc1_hwmod,
3733         .slave          = &omap44xx_l3_main_1_hwmod,
3734         .clk            = "l3_div_ck",
3735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3736 };
3737
3738 /* mmc2 -> l3_main_1 */
3739 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3740         .master         = &omap44xx_mmc2_hwmod,
3741         .slave          = &omap44xx_l3_main_1_hwmod,
3742         .clk            = "l3_div_ck",
3743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3744 };
3745
3746 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3747         {
3748                 .pa_start       = 0x44000000,
3749                 .pa_end         = 0x44000fff,
3750                 .flags          = ADDR_TYPE_RT
3751         },
3752         { }
3753 };
3754
3755 /* mpu -> l3_main_1 */
3756 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3757         .master         = &omap44xx_mpu_hwmod,
3758         .slave          = &omap44xx_l3_main_1_hwmod,
3759         .clk            = "l3_div_ck",
3760         .addr           = omap44xx_l3_main_1_addrs,
3761         .user           = OCP_USER_MPU,
3762 };
3763
3764 /* c2c_target_fw -> l3_main_2 */
3765 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3766         .master         = &omap44xx_c2c_target_fw_hwmod,
3767         .slave          = &omap44xx_l3_main_2_hwmod,
3768         .clk            = "l3_div_ck",
3769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3770 };
3771
3772 /* debugss -> l3_main_2 */
3773 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3774         .master         = &omap44xx_debugss_hwmod,
3775         .slave          = &omap44xx_l3_main_2_hwmod,
3776         .clk            = "dbgclk_mux_ck",
3777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3778 };
3779
3780 /* dma_system -> l3_main_2 */
3781 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3782         .master         = &omap44xx_dma_system_hwmod,
3783         .slave          = &omap44xx_l3_main_2_hwmod,
3784         .clk            = "l3_div_ck",
3785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3786 };
3787
3788 /* fdif -> l3_main_2 */
3789 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3790         .master         = &omap44xx_fdif_hwmod,
3791         .slave          = &omap44xx_l3_main_2_hwmod,
3792         .clk            = "l3_div_ck",
3793         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3794 };
3795
3796 /* gpu -> l3_main_2 */
3797 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3798         .master         = &omap44xx_gpu_hwmod,
3799         .slave          = &omap44xx_l3_main_2_hwmod,
3800         .clk            = "l3_div_ck",
3801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3802 };
3803
3804 /* hsi -> l3_main_2 */
3805 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3806         .master         = &omap44xx_hsi_hwmod,
3807         .slave          = &omap44xx_l3_main_2_hwmod,
3808         .clk            = "l3_div_ck",
3809         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3810 };
3811
3812 /* ipu -> l3_main_2 */
3813 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3814         .master         = &omap44xx_ipu_hwmod,
3815         .slave          = &omap44xx_l3_main_2_hwmod,
3816         .clk            = "l3_div_ck",
3817         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3818 };
3819
3820 /* iss -> l3_main_2 */
3821 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3822         .master         = &omap44xx_iss_hwmod,
3823         .slave          = &omap44xx_l3_main_2_hwmod,
3824         .clk            = "l3_div_ck",
3825         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3826 };
3827
3828 /* iva -> l3_main_2 */
3829 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3830         .master         = &omap44xx_iva_hwmod,
3831         .slave          = &omap44xx_l3_main_2_hwmod,
3832         .clk            = "l3_div_ck",
3833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3834 };
3835
3836 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3837         {
3838                 .pa_start       = 0x44800000,
3839                 .pa_end         = 0x44801fff,
3840                 .flags          = ADDR_TYPE_RT
3841         },
3842         { }
3843 };
3844
3845 /* l3_main_1 -> l3_main_2 */
3846 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3847         .master         = &omap44xx_l3_main_1_hwmod,
3848         .slave          = &omap44xx_l3_main_2_hwmod,
3849         .clk            = "l3_div_ck",
3850         .addr           = omap44xx_l3_main_2_addrs,
3851         .user           = OCP_USER_MPU,
3852 };
3853
3854 /* l4_cfg -> l3_main_2 */
3855 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3856         .master         = &omap44xx_l4_cfg_hwmod,
3857         .slave          = &omap44xx_l3_main_2_hwmod,
3858         .clk            = "l4_div_ck",
3859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3860 };
3861
3862 /* usb_host_fs -> l3_main_2 */
3863 static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
3864         .master         = &omap44xx_usb_host_fs_hwmod,
3865         .slave          = &omap44xx_l3_main_2_hwmod,
3866         .clk            = "l3_div_ck",
3867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3868 };
3869
3870 /* usb_host_hs -> l3_main_2 */
3871 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3872         .master         = &omap44xx_usb_host_hs_hwmod,
3873         .slave          = &omap44xx_l3_main_2_hwmod,
3874         .clk            = "l3_div_ck",
3875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3876 };
3877
3878 /* usb_otg_hs -> l3_main_2 */
3879 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3880         .master         = &omap44xx_usb_otg_hs_hwmod,
3881         .slave          = &omap44xx_l3_main_2_hwmod,
3882         .clk            = "l3_div_ck",
3883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3884 };
3885
3886 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3887         {
3888                 .pa_start       = 0x45000000,
3889                 .pa_end         = 0x45000fff,
3890                 .flags          = ADDR_TYPE_RT
3891         },
3892         { }
3893 };
3894
3895 /* l3_main_1 -> l3_main_3 */
3896 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3897         .master         = &omap44xx_l3_main_1_hwmod,
3898         .slave          = &omap44xx_l3_main_3_hwmod,
3899         .clk            = "l3_div_ck",
3900         .addr           = omap44xx_l3_main_3_addrs,
3901         .user           = OCP_USER_MPU,
3902 };
3903
3904 /* l3_main_2 -> l3_main_3 */
3905 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3906         .master         = &omap44xx_l3_main_2_hwmod,
3907         .slave          = &omap44xx_l3_main_3_hwmod,
3908         .clk            = "l3_div_ck",
3909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3910 };
3911
3912 /* l4_cfg -> l3_main_3 */
3913 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3914         .master         = &omap44xx_l4_cfg_hwmod,
3915         .slave          = &omap44xx_l3_main_3_hwmod,
3916         .clk            = "l4_div_ck",
3917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3918 };
3919
3920 /* aess -> l4_abe */
3921 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
3922         .master         = &omap44xx_aess_hwmod,
3923         .slave          = &omap44xx_l4_abe_hwmod,
3924         .clk            = "ocp_abe_iclk",
3925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3926 };
3927
3928 /* dsp -> l4_abe */
3929 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3930         .master         = &omap44xx_dsp_hwmod,
3931         .slave          = &omap44xx_l4_abe_hwmod,
3932         .clk            = "ocp_abe_iclk",
3933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3934 };
3935
3936 /* l3_main_1 -> l4_abe */
3937 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3938         .master         = &omap44xx_l3_main_1_hwmod,
3939         .slave          = &omap44xx_l4_abe_hwmod,
3940         .clk            = "l3_div_ck",
3941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3942 };
3943
3944 /* mpu -> l4_abe */
3945 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3946         .master         = &omap44xx_mpu_hwmod,
3947         .slave          = &omap44xx_l4_abe_hwmod,
3948         .clk            = "ocp_abe_iclk",
3949         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3950 };
3951
3952 /* l3_main_1 -> l4_cfg */
3953 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3954         .master         = &omap44xx_l3_main_1_hwmod,
3955         .slave          = &omap44xx_l4_cfg_hwmod,
3956         .clk            = "l3_div_ck",
3957         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3958 };
3959
3960 /* l3_main_2 -> l4_per */
3961 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3962         .master         = &omap44xx_l3_main_2_hwmod,
3963         .slave          = &omap44xx_l4_per_hwmod,
3964         .clk            = "l3_div_ck",
3965         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3966 };
3967
3968 /* l4_cfg -> l4_wkup */
3969 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3970         .master         = &omap44xx_l4_cfg_hwmod,
3971         .slave          = &omap44xx_l4_wkup_hwmod,
3972         .clk            = "l4_div_ck",
3973         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3974 };
3975
3976 /* mpu -> mpu_private */
3977 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3978         .master         = &omap44xx_mpu_hwmod,
3979         .slave          = &omap44xx_mpu_private_hwmod,
3980         .clk            = "l3_div_ck",
3981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3982 };
3983
3984 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3985         {
3986                 .pa_start       = 0x4a102000,
3987                 .pa_end         = 0x4a10207f,
3988                 .flags          = ADDR_TYPE_RT
3989         },
3990         { }
3991 };
3992
3993 /* l4_cfg -> ocp_wp_noc */
3994 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3995         .master         = &omap44xx_l4_cfg_hwmod,
3996         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3997         .clk            = "l4_div_ck",
3998         .addr           = omap44xx_ocp_wp_noc_addrs,
3999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4000 };
4001
4002 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4003         {
4004                 .pa_start       = 0x401f1000,
4005                 .pa_end         = 0x401f13ff,
4006                 .flags          = ADDR_TYPE_RT
4007         },
4008         { }
4009 };
4010
4011 /* l4_abe -> aess */
4012 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
4013         .master         = &omap44xx_l4_abe_hwmod,
4014         .slave          = &omap44xx_aess_hwmod,
4015         .clk            = "ocp_abe_iclk",
4016         .addr           = omap44xx_aess_addrs,
4017         .user           = OCP_USER_MPU,
4018 };
4019
4020 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4021         {
4022                 .pa_start       = 0x490f1000,
4023                 .pa_end         = 0x490f13ff,
4024                 .flags          = ADDR_TYPE_RT
4025         },
4026         { }
4027 };
4028
4029 /* l4_abe -> aess (dma) */
4030 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
4031         .master         = &omap44xx_l4_abe_hwmod,
4032         .slave          = &omap44xx_aess_hwmod,
4033         .clk            = "ocp_abe_iclk",
4034         .addr           = omap44xx_aess_dma_addrs,
4035         .user           = OCP_USER_SDMA,
4036 };
4037
4038 /* l3_main_2 -> c2c */
4039 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4040         .master         = &omap44xx_l3_main_2_hwmod,
4041         .slave          = &omap44xx_c2c_hwmod,
4042         .clk            = "l3_div_ck",
4043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4044 };
4045
4046 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4047         {
4048                 .pa_start       = 0x4a304000,
4049                 .pa_end         = 0x4a30401f,
4050                 .flags          = ADDR_TYPE_RT
4051         },
4052         { }
4053 };
4054
4055 /* l4_wkup -> counter_32k */
4056 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4057         .master         = &omap44xx_l4_wkup_hwmod,
4058         .slave          = &omap44xx_counter_32k_hwmod,
4059         .clk            = "l4_wkup_clk_mux_ck",
4060         .addr           = omap44xx_counter_32k_addrs,
4061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4062 };
4063
4064 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4065         {
4066                 .pa_start       = 0x4a002000,
4067                 .pa_end         = 0x4a0027ff,
4068                 .flags          = ADDR_TYPE_RT
4069         },
4070         { }
4071 };
4072
4073 /* l4_cfg -> ctrl_module_core */
4074 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4075         .master         = &omap44xx_l4_cfg_hwmod,
4076         .slave          = &omap44xx_ctrl_module_core_hwmod,
4077         .clk            = "l4_div_ck",
4078         .addr           = omap44xx_ctrl_module_core_addrs,
4079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4080 };
4081
4082 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4083         {
4084                 .pa_start       = 0x4a100000,
4085                 .pa_end         = 0x4a1007ff,
4086                 .flags          = ADDR_TYPE_RT
4087         },
4088         { }
4089 };
4090
4091 /* l4_cfg -> ctrl_module_pad_core */
4092 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4093         .master         = &omap44xx_l4_cfg_hwmod,
4094         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4095         .clk            = "l4_div_ck",
4096         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4097         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4098 };
4099
4100 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4101         {
4102                 .pa_start       = 0x4a30c000,
4103                 .pa_end         = 0x4a30c7ff,
4104                 .flags          = ADDR_TYPE_RT
4105         },
4106         { }
4107 };
4108
4109 /* l4_wkup -> ctrl_module_wkup */
4110 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4111         .master         = &omap44xx_l4_wkup_hwmod,
4112         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4113         .clk            = "l4_wkup_clk_mux_ck",
4114         .addr           = omap44xx_ctrl_module_wkup_addrs,
4115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4116 };
4117
4118 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4119         {
4120                 .pa_start       = 0x4a31e000,
4121                 .pa_end         = 0x4a31e7ff,
4122                 .flags          = ADDR_TYPE_RT
4123         },
4124         { }
4125 };
4126
4127 /* l4_wkup -> ctrl_module_pad_wkup */
4128 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4129         .master         = &omap44xx_l4_wkup_hwmod,
4130         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4131         .clk            = "l4_wkup_clk_mux_ck",
4132         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4134 };
4135
4136 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4137         {
4138                 .pa_start       = 0x54160000,
4139                 .pa_end         = 0x54167fff,
4140                 .flags          = ADDR_TYPE_RT
4141         },
4142         { }
4143 };
4144
4145 /* l3_instr -> debugss */
4146 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4147         .master         = &omap44xx_l3_instr_hwmod,
4148         .slave          = &omap44xx_debugss_hwmod,
4149         .clk            = "l3_div_ck",
4150         .addr           = omap44xx_debugss_addrs,
4151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4152 };
4153
4154 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4155         {
4156                 .pa_start       = 0x4a056000,
4157                 .pa_end         = 0x4a056fff,
4158                 .flags          = ADDR_TYPE_RT
4159         },
4160         { }
4161 };
4162
4163 /* l4_cfg -> dma_system */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4165         .master         = &omap44xx_l4_cfg_hwmod,
4166         .slave          = &omap44xx_dma_system_hwmod,
4167         .clk            = "l4_div_ck",
4168         .addr           = omap44xx_dma_system_addrs,
4169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4170 };
4171
4172 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4173         {
4174                 .name           = "mpu",
4175                 .pa_start       = 0x4012e000,
4176                 .pa_end         = 0x4012e07f,
4177                 .flags          = ADDR_TYPE_RT
4178         },
4179         { }
4180 };
4181
4182 /* l4_abe -> dmic */
4183 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4184         .master         = &omap44xx_l4_abe_hwmod,
4185         .slave          = &omap44xx_dmic_hwmod,
4186         .clk            = "ocp_abe_iclk",
4187         .addr           = omap44xx_dmic_addrs,
4188         .user           = OCP_USER_MPU,
4189 };
4190
4191 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4192         {
4193                 .name           = "dma",
4194                 .pa_start       = 0x4902e000,
4195                 .pa_end         = 0x4902e07f,
4196                 .flags          = ADDR_TYPE_RT
4197         },
4198         { }
4199 };
4200
4201 /* l4_abe -> dmic (dma) */
4202 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4203         .master         = &omap44xx_l4_abe_hwmod,
4204         .slave          = &omap44xx_dmic_hwmod,
4205         .clk            = "ocp_abe_iclk",
4206         .addr           = omap44xx_dmic_dma_addrs,
4207         .user           = OCP_USER_SDMA,
4208 };
4209
4210 /* dsp -> iva */
4211 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4212         .master         = &omap44xx_dsp_hwmod,
4213         .slave          = &omap44xx_iva_hwmod,
4214         .clk            = "dpll_iva_m5x2_ck",
4215         .user           = OCP_USER_DSP,
4216 };
4217
4218 /* dsp -> sl2if */
4219 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4220         .master         = &omap44xx_dsp_hwmod,
4221         .slave          = &omap44xx_sl2if_hwmod,
4222         .clk            = "dpll_iva_m5x2_ck",
4223         .user           = OCP_USER_DSP,
4224 };
4225
4226 /* l4_cfg -> dsp */
4227 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4228         .master         = &omap44xx_l4_cfg_hwmod,
4229         .slave          = &omap44xx_dsp_hwmod,
4230         .clk            = "l4_div_ck",
4231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4232 };
4233
4234 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4235         {
4236                 .pa_start       = 0x58000000,
4237                 .pa_end         = 0x5800007f,
4238                 .flags          = ADDR_TYPE_RT
4239         },
4240         { }
4241 };
4242
4243 /* l3_main_2 -> dss */
4244 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4245         .master         = &omap44xx_l3_main_2_hwmod,
4246         .slave          = &omap44xx_dss_hwmod,
4247         .clk            = "dss_fck",
4248         .addr           = omap44xx_dss_dma_addrs,
4249         .user           = OCP_USER_SDMA,
4250 };
4251
4252 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4253         {
4254                 .pa_start       = 0x48040000,
4255                 .pa_end         = 0x4804007f,
4256                 .flags          = ADDR_TYPE_RT
4257         },
4258         { }
4259 };
4260
4261 /* l4_per -> dss */
4262 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4263         .master         = &omap44xx_l4_per_hwmod,
4264         .slave          = &omap44xx_dss_hwmod,
4265         .clk            = "l4_div_ck",
4266         .addr           = omap44xx_dss_addrs,
4267         .user           = OCP_USER_MPU,
4268 };
4269
4270 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4271         {
4272                 .pa_start       = 0x58001000,
4273                 .pa_end         = 0x58001fff,
4274                 .flags          = ADDR_TYPE_RT
4275         },
4276         { }
4277 };
4278
4279 /* l3_main_2 -> dss_dispc */
4280 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4281         .master         = &omap44xx_l3_main_2_hwmod,
4282         .slave          = &omap44xx_dss_dispc_hwmod,
4283         .clk            = "dss_fck",
4284         .addr           = omap44xx_dss_dispc_dma_addrs,
4285         .user           = OCP_USER_SDMA,
4286 };
4287
4288 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4289         {
4290                 .pa_start       = 0x48041000,
4291                 .pa_end         = 0x48041fff,
4292                 .flags          = ADDR_TYPE_RT
4293         },
4294         { }
4295 };
4296
4297 /* l4_per -> dss_dispc */
4298 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4299         .master         = &omap44xx_l4_per_hwmod,
4300         .slave          = &omap44xx_dss_dispc_hwmod,
4301         .clk            = "l4_div_ck",
4302         .addr           = omap44xx_dss_dispc_addrs,
4303         .user           = OCP_USER_MPU,
4304 };
4305
4306 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4307         {
4308                 .pa_start       = 0x58004000,
4309                 .pa_end         = 0x580041ff,
4310                 .flags          = ADDR_TYPE_RT
4311         },
4312         { }
4313 };
4314
4315 /* l3_main_2 -> dss_dsi1 */
4316 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4317         .master         = &omap44xx_l3_main_2_hwmod,
4318         .slave          = &omap44xx_dss_dsi1_hwmod,
4319         .clk            = "dss_fck",
4320         .addr           = omap44xx_dss_dsi1_dma_addrs,
4321         .user           = OCP_USER_SDMA,
4322 };
4323
4324 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4325         {
4326                 .pa_start       = 0x48044000,
4327                 .pa_end         = 0x480441ff,
4328                 .flags          = ADDR_TYPE_RT
4329         },
4330         { }
4331 };
4332
4333 /* l4_per -> dss_dsi1 */
4334 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4335         .master         = &omap44xx_l4_per_hwmod,
4336         .slave          = &omap44xx_dss_dsi1_hwmod,
4337         .clk            = "l4_div_ck",
4338         .addr           = omap44xx_dss_dsi1_addrs,
4339         .user           = OCP_USER_MPU,
4340 };
4341
4342 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4343         {
4344                 .pa_start       = 0x58005000,
4345                 .pa_end         = 0x580051ff,
4346                 .flags          = ADDR_TYPE_RT
4347         },
4348         { }
4349 };
4350
4351 /* l3_main_2 -> dss_dsi2 */
4352 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4353         .master         = &omap44xx_l3_main_2_hwmod,
4354         .slave          = &omap44xx_dss_dsi2_hwmod,
4355         .clk            = "dss_fck",
4356         .addr           = omap44xx_dss_dsi2_dma_addrs,
4357         .user           = OCP_USER_SDMA,
4358 };
4359
4360 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4361         {
4362                 .pa_start       = 0x48045000,
4363                 .pa_end         = 0x480451ff,
4364                 .flags          = ADDR_TYPE_RT
4365         },
4366         { }
4367 };
4368
4369 /* l4_per -> dss_dsi2 */
4370 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4371         .master         = &omap44xx_l4_per_hwmod,
4372         .slave          = &omap44xx_dss_dsi2_hwmod,
4373         .clk            = "l4_div_ck",
4374         .addr           = omap44xx_dss_dsi2_addrs,
4375         .user           = OCP_USER_MPU,
4376 };
4377
4378 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4379         {
4380                 .pa_start       = 0x58006000,
4381                 .pa_end         = 0x58006fff,
4382                 .flags          = ADDR_TYPE_RT
4383         },
4384         { }
4385 };
4386
4387 /* l3_main_2 -> dss_hdmi */
4388 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4389         .master         = &omap44xx_l3_main_2_hwmod,
4390         .slave          = &omap44xx_dss_hdmi_hwmod,
4391         .clk            = "dss_fck",
4392         .addr           = omap44xx_dss_hdmi_dma_addrs,
4393         .user           = OCP_USER_SDMA,
4394 };
4395
4396 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4397         {
4398                 .pa_start       = 0x48046000,
4399                 .pa_end         = 0x48046fff,
4400                 .flags          = ADDR_TYPE_RT
4401         },
4402         { }
4403 };
4404
4405 /* l4_per -> dss_hdmi */
4406 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4407         .master         = &omap44xx_l4_per_hwmod,
4408         .slave          = &omap44xx_dss_hdmi_hwmod,
4409         .clk            = "l4_div_ck",
4410         .addr           = omap44xx_dss_hdmi_addrs,
4411         .user           = OCP_USER_MPU,
4412 };
4413
4414 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4415         {
4416                 .pa_start       = 0x58002000,
4417                 .pa_end         = 0x580020ff,
4418                 .flags          = ADDR_TYPE_RT
4419         },
4420         { }
4421 };
4422
4423 /* l3_main_2 -> dss_rfbi */
4424 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4425         .master         = &omap44xx_l3_main_2_hwmod,
4426         .slave          = &omap44xx_dss_rfbi_hwmod,
4427         .clk            = "dss_fck",
4428         .addr           = omap44xx_dss_rfbi_dma_addrs,
4429         .user           = OCP_USER_SDMA,
4430 };
4431
4432 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4433         {
4434                 .pa_start       = 0x48042000,
4435                 .pa_end         = 0x480420ff,
4436                 .flags          = ADDR_TYPE_RT
4437         },
4438         { }
4439 };
4440
4441 /* l4_per -> dss_rfbi */
4442 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4443         .master         = &omap44xx_l4_per_hwmod,
4444         .slave          = &omap44xx_dss_rfbi_hwmod,
4445         .clk            = "l4_div_ck",
4446         .addr           = omap44xx_dss_rfbi_addrs,
4447         .user           = OCP_USER_MPU,
4448 };
4449
4450 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4451         {
4452                 .pa_start       = 0x58003000,
4453                 .pa_end         = 0x580030ff,
4454                 .flags          = ADDR_TYPE_RT
4455         },
4456         { }
4457 };
4458
4459 /* l3_main_2 -> dss_venc */
4460 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4461         .master         = &omap44xx_l3_main_2_hwmod,
4462         .slave          = &omap44xx_dss_venc_hwmod,
4463         .clk            = "dss_fck",
4464         .addr           = omap44xx_dss_venc_dma_addrs,
4465         .user           = OCP_USER_SDMA,
4466 };
4467
4468 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4469         {
4470                 .pa_start       = 0x48043000,
4471                 .pa_end         = 0x480430ff,
4472                 .flags          = ADDR_TYPE_RT
4473         },
4474         { }
4475 };
4476
4477 /* l4_per -> dss_venc */
4478 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4479         .master         = &omap44xx_l4_per_hwmod,
4480         .slave          = &omap44xx_dss_venc_hwmod,
4481         .clk            = "l4_div_ck",
4482         .addr           = omap44xx_dss_venc_addrs,
4483         .user           = OCP_USER_MPU,
4484 };
4485
4486 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4487         {
4488                 .pa_start       = 0x48078000,
4489                 .pa_end         = 0x48078fff,
4490                 .flags          = ADDR_TYPE_RT
4491         },
4492         { }
4493 };
4494
4495 /* l4_per -> elm */
4496 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4497         .master         = &omap44xx_l4_per_hwmod,
4498         .slave          = &omap44xx_elm_hwmod,
4499         .clk            = "l4_div_ck",
4500         .addr           = omap44xx_elm_addrs,
4501         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4502 };
4503
4504 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4505         {
4506                 .pa_start       = 0x4c000000,
4507                 .pa_end         = 0x4c0000ff,
4508                 .flags          = ADDR_TYPE_RT
4509         },
4510         { }
4511 };
4512
4513 /* emif_fw -> emif1 */
4514 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4515         .master         = &omap44xx_emif_fw_hwmod,
4516         .slave          = &omap44xx_emif1_hwmod,
4517         .clk            = "l3_div_ck",
4518         .addr           = omap44xx_emif1_addrs,
4519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4520 };
4521
4522 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4523         {
4524                 .pa_start       = 0x4d000000,
4525                 .pa_end         = 0x4d0000ff,
4526                 .flags          = ADDR_TYPE_RT
4527         },
4528         { }
4529 };
4530
4531 /* emif_fw -> emif2 */
4532 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4533         .master         = &omap44xx_emif_fw_hwmod,
4534         .slave          = &omap44xx_emif2_hwmod,
4535         .clk            = "l3_div_ck",
4536         .addr           = omap44xx_emif2_addrs,
4537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4538 };
4539
4540 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4541         {
4542                 .pa_start       = 0x4a10a000,
4543                 .pa_end         = 0x4a10a1ff,
4544                 .flags          = ADDR_TYPE_RT
4545         },
4546         { }
4547 };
4548
4549 /* l4_cfg -> fdif */
4550 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4551         .master         = &omap44xx_l4_cfg_hwmod,
4552         .slave          = &omap44xx_fdif_hwmod,
4553         .clk            = "l4_div_ck",
4554         .addr           = omap44xx_fdif_addrs,
4555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4556 };
4557
4558 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4559         {
4560                 .pa_start       = 0x4a310000,
4561                 .pa_end         = 0x4a3101ff,
4562                 .flags          = ADDR_TYPE_RT
4563         },
4564         { }
4565 };
4566
4567 /* l4_wkup -> gpio1 */
4568 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4569         .master         = &omap44xx_l4_wkup_hwmod,
4570         .slave          = &omap44xx_gpio1_hwmod,
4571         .clk            = "l4_wkup_clk_mux_ck",
4572         .addr           = omap44xx_gpio1_addrs,
4573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4574 };
4575
4576 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4577         {
4578                 .pa_start       = 0x48055000,
4579                 .pa_end         = 0x480551ff,
4580                 .flags          = ADDR_TYPE_RT
4581         },
4582         { }
4583 };
4584
4585 /* l4_per -> gpio2 */
4586 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4587         .master         = &omap44xx_l4_per_hwmod,
4588         .slave          = &omap44xx_gpio2_hwmod,
4589         .clk            = "l4_div_ck",
4590         .addr           = omap44xx_gpio2_addrs,
4591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4592 };
4593
4594 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4595         {
4596                 .pa_start       = 0x48057000,
4597                 .pa_end         = 0x480571ff,
4598                 .flags          = ADDR_TYPE_RT
4599         },
4600         { }
4601 };
4602
4603 /* l4_per -> gpio3 */
4604 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4605         .master         = &omap44xx_l4_per_hwmod,
4606         .slave          = &omap44xx_gpio3_hwmod,
4607         .clk            = "l4_div_ck",
4608         .addr           = omap44xx_gpio3_addrs,
4609         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4610 };
4611
4612 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4613         {
4614                 .pa_start       = 0x48059000,
4615                 .pa_end         = 0x480591ff,
4616                 .flags          = ADDR_TYPE_RT
4617         },
4618         { }
4619 };
4620
4621 /* l4_per -> gpio4 */
4622 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4623         .master         = &omap44xx_l4_per_hwmod,
4624         .slave          = &omap44xx_gpio4_hwmod,
4625         .clk            = "l4_div_ck",
4626         .addr           = omap44xx_gpio4_addrs,
4627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4628 };
4629
4630 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4631         {
4632                 .pa_start       = 0x4805b000,
4633                 .pa_end         = 0x4805b1ff,
4634                 .flags          = ADDR_TYPE_RT
4635         },
4636         { }
4637 };
4638
4639 /* l4_per -> gpio5 */
4640 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4641         .master         = &omap44xx_l4_per_hwmod,
4642         .slave          = &omap44xx_gpio5_hwmod,
4643         .clk            = "l4_div_ck",
4644         .addr           = omap44xx_gpio5_addrs,
4645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4646 };
4647
4648 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4649         {
4650                 .pa_start       = 0x4805d000,
4651                 .pa_end         = 0x4805d1ff,
4652                 .flags          = ADDR_TYPE_RT
4653         },
4654         { }
4655 };
4656
4657 /* l4_per -> gpio6 */
4658 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4659         .master         = &omap44xx_l4_per_hwmod,
4660         .slave          = &omap44xx_gpio6_hwmod,
4661         .clk            = "l4_div_ck",
4662         .addr           = omap44xx_gpio6_addrs,
4663         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4664 };
4665
4666 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4667         {
4668                 .pa_start       = 0x50000000,
4669                 .pa_end         = 0x500003ff,
4670                 .flags          = ADDR_TYPE_RT
4671         },
4672         { }
4673 };
4674
4675 /* l3_main_2 -> gpmc */
4676 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4677         .master         = &omap44xx_l3_main_2_hwmod,
4678         .slave          = &omap44xx_gpmc_hwmod,
4679         .clk            = "l3_div_ck",
4680         .addr           = omap44xx_gpmc_addrs,
4681         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4682 };
4683
4684 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4685         {
4686                 .pa_start       = 0x56000000,
4687                 .pa_end         = 0x5600ffff,
4688                 .flags          = ADDR_TYPE_RT
4689         },
4690         { }
4691 };
4692
4693 /* l3_main_2 -> gpu */
4694 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4695         .master         = &omap44xx_l3_main_2_hwmod,
4696         .slave          = &omap44xx_gpu_hwmod,
4697         .clk            = "l3_div_ck",
4698         .addr           = omap44xx_gpu_addrs,
4699         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4700 };
4701
4702 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4703         {
4704                 .pa_start       = 0x480b2000,
4705                 .pa_end         = 0x480b201f,
4706                 .flags          = ADDR_TYPE_RT
4707         },
4708         { }
4709 };
4710
4711 /* l4_per -> hdq1w */
4712 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4713         .master         = &omap44xx_l4_per_hwmod,
4714         .slave          = &omap44xx_hdq1w_hwmod,
4715         .clk            = "l4_div_ck",
4716         .addr           = omap44xx_hdq1w_addrs,
4717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4718 };
4719
4720 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4721         {
4722                 .pa_start       = 0x4a058000,
4723                 .pa_end         = 0x4a05bfff,
4724                 .flags          = ADDR_TYPE_RT
4725         },
4726         { }
4727 };
4728
4729 /* l4_cfg -> hsi */
4730 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4731         .master         = &omap44xx_l4_cfg_hwmod,
4732         .slave          = &omap44xx_hsi_hwmod,
4733         .clk            = "l4_div_ck",
4734         .addr           = omap44xx_hsi_addrs,
4735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4736 };
4737
4738 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4739         {
4740                 .pa_start       = 0x48070000,
4741                 .pa_end         = 0x480700ff,
4742                 .flags          = ADDR_TYPE_RT
4743         },
4744         { }
4745 };
4746
4747 /* l4_per -> i2c1 */
4748 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4749         .master         = &omap44xx_l4_per_hwmod,
4750         .slave          = &omap44xx_i2c1_hwmod,
4751         .clk            = "l4_div_ck",
4752         .addr           = omap44xx_i2c1_addrs,
4753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4754 };
4755
4756 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4757         {
4758                 .pa_start       = 0x48072000,
4759                 .pa_end         = 0x480720ff,
4760                 .flags          = ADDR_TYPE_RT
4761         },
4762         { }
4763 };
4764
4765 /* l4_per -> i2c2 */
4766 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4767         .master         = &omap44xx_l4_per_hwmod,
4768         .slave          = &omap44xx_i2c2_hwmod,
4769         .clk            = "l4_div_ck",
4770         .addr           = omap44xx_i2c2_addrs,
4771         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4772 };
4773
4774 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4775         {
4776                 .pa_start       = 0x48060000,
4777                 .pa_end         = 0x480600ff,
4778                 .flags          = ADDR_TYPE_RT
4779         },
4780         { }
4781 };
4782
4783 /* l4_per -> i2c3 */
4784 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4785         .master         = &omap44xx_l4_per_hwmod,
4786         .slave          = &omap44xx_i2c3_hwmod,
4787         .clk            = "l4_div_ck",
4788         .addr           = omap44xx_i2c3_addrs,
4789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4790 };
4791
4792 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4793         {
4794                 .pa_start       = 0x48350000,
4795                 .pa_end         = 0x483500ff,
4796                 .flags          = ADDR_TYPE_RT
4797         },
4798         { }
4799 };
4800
4801 /* l4_per -> i2c4 */
4802 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4803         .master         = &omap44xx_l4_per_hwmod,
4804         .slave          = &omap44xx_i2c4_hwmod,
4805         .clk            = "l4_div_ck",
4806         .addr           = omap44xx_i2c4_addrs,
4807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4808 };
4809
4810 /* l3_main_2 -> ipu */
4811 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4812         .master         = &omap44xx_l3_main_2_hwmod,
4813         .slave          = &omap44xx_ipu_hwmod,
4814         .clk            = "l3_div_ck",
4815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4816 };
4817
4818 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4819         {
4820                 .pa_start       = 0x52000000,
4821                 .pa_end         = 0x520000ff,
4822                 .flags          = ADDR_TYPE_RT
4823         },
4824         { }
4825 };
4826
4827 /* l3_main_2 -> iss */
4828 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4829         .master         = &omap44xx_l3_main_2_hwmod,
4830         .slave          = &omap44xx_iss_hwmod,
4831         .clk            = "l3_div_ck",
4832         .addr           = omap44xx_iss_addrs,
4833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4834 };
4835
4836 /* iva -> sl2if */
4837 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4838         .master         = &omap44xx_iva_hwmod,
4839         .slave          = &omap44xx_sl2if_hwmod,
4840         .clk            = "dpll_iva_m5x2_ck",
4841         .user           = OCP_USER_IVA,
4842 };
4843
4844 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4845         {
4846                 .pa_start       = 0x5a000000,
4847                 .pa_end         = 0x5a07ffff,
4848                 .flags          = ADDR_TYPE_RT
4849         },
4850         { }
4851 };
4852
4853 /* l3_main_2 -> iva */
4854 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4855         .master         = &omap44xx_l3_main_2_hwmod,
4856         .slave          = &omap44xx_iva_hwmod,
4857         .clk            = "l3_div_ck",
4858         .addr           = omap44xx_iva_addrs,
4859         .user           = OCP_USER_MPU,
4860 };
4861
4862 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4863         {
4864                 .pa_start       = 0x4a31c000,
4865                 .pa_end         = 0x4a31c07f,
4866                 .flags          = ADDR_TYPE_RT
4867         },
4868         { }
4869 };
4870
4871 /* l4_wkup -> kbd */
4872 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4873         .master         = &omap44xx_l4_wkup_hwmod,
4874         .slave          = &omap44xx_kbd_hwmod,
4875         .clk            = "l4_wkup_clk_mux_ck",
4876         .addr           = omap44xx_kbd_addrs,
4877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4878 };
4879
4880 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4881         {
4882                 .pa_start       = 0x4a0f4000,
4883                 .pa_end         = 0x4a0f41ff,
4884                 .flags          = ADDR_TYPE_RT
4885         },
4886         { }
4887 };
4888
4889 /* l4_cfg -> mailbox */
4890 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4891         .master         = &omap44xx_l4_cfg_hwmod,
4892         .slave          = &omap44xx_mailbox_hwmod,
4893         .clk            = "l4_div_ck",
4894         .addr           = omap44xx_mailbox_addrs,
4895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4896 };
4897
4898 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4899         {
4900                 .pa_start       = 0x40128000,
4901                 .pa_end         = 0x401283ff,
4902                 .flags          = ADDR_TYPE_RT
4903         },
4904         { }
4905 };
4906
4907 /* l4_abe -> mcasp */
4908 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4909         .master         = &omap44xx_l4_abe_hwmod,
4910         .slave          = &omap44xx_mcasp_hwmod,
4911         .clk            = "ocp_abe_iclk",
4912         .addr           = omap44xx_mcasp_addrs,
4913         .user           = OCP_USER_MPU,
4914 };
4915
4916 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4917         {
4918                 .pa_start       = 0x49028000,
4919                 .pa_end         = 0x490283ff,
4920                 .flags          = ADDR_TYPE_RT
4921         },
4922         { }
4923 };
4924
4925 /* l4_abe -> mcasp (dma) */
4926 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4927         .master         = &omap44xx_l4_abe_hwmod,
4928         .slave          = &omap44xx_mcasp_hwmod,
4929         .clk            = "ocp_abe_iclk",
4930         .addr           = omap44xx_mcasp_dma_addrs,
4931         .user           = OCP_USER_SDMA,
4932 };
4933
4934 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4935         {
4936                 .name           = "mpu",
4937                 .pa_start       = 0x40122000,
4938                 .pa_end         = 0x401220ff,
4939                 .flags          = ADDR_TYPE_RT
4940         },
4941         { }
4942 };
4943
4944 /* l4_abe -> mcbsp1 */
4945 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4946         .master         = &omap44xx_l4_abe_hwmod,
4947         .slave          = &omap44xx_mcbsp1_hwmod,
4948         .clk            = "ocp_abe_iclk",
4949         .addr           = omap44xx_mcbsp1_addrs,
4950         .user           = OCP_USER_MPU,
4951 };
4952
4953 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4954         {
4955                 .name           = "dma",
4956                 .pa_start       = 0x49022000,
4957                 .pa_end         = 0x490220ff,
4958                 .flags          = ADDR_TYPE_RT
4959         },
4960         { }
4961 };
4962
4963 /* l4_abe -> mcbsp1 (dma) */
4964 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4965         .master         = &omap44xx_l4_abe_hwmod,
4966         .slave          = &omap44xx_mcbsp1_hwmod,
4967         .clk            = "ocp_abe_iclk",
4968         .addr           = omap44xx_mcbsp1_dma_addrs,
4969         .user           = OCP_USER_SDMA,
4970 };
4971
4972 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4973         {
4974                 .name           = "mpu",
4975                 .pa_start       = 0x40124000,
4976                 .pa_end         = 0x401240ff,
4977                 .flags          = ADDR_TYPE_RT
4978         },
4979         { }
4980 };
4981
4982 /* l4_abe -> mcbsp2 */
4983 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4984         .master         = &omap44xx_l4_abe_hwmod,
4985         .slave          = &omap44xx_mcbsp2_hwmod,
4986         .clk            = "ocp_abe_iclk",
4987         .addr           = omap44xx_mcbsp2_addrs,
4988         .user           = OCP_USER_MPU,
4989 };
4990
4991 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4992         {
4993                 .name           = "dma",
4994                 .pa_start       = 0x49024000,
4995                 .pa_end         = 0x490240ff,
4996                 .flags          = ADDR_TYPE_RT
4997         },
4998         { }
4999 };
5000
5001 /* l4_abe -> mcbsp2 (dma) */
5002 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5003         .master         = &omap44xx_l4_abe_hwmod,
5004         .slave          = &omap44xx_mcbsp2_hwmod,
5005         .clk            = "ocp_abe_iclk",
5006         .addr           = omap44xx_mcbsp2_dma_addrs,
5007         .user           = OCP_USER_SDMA,
5008 };
5009
5010 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5011         {
5012                 .name           = "mpu",
5013                 .pa_start       = 0x40126000,
5014                 .pa_end         = 0x401260ff,
5015                 .flags          = ADDR_TYPE_RT
5016         },
5017         { }
5018 };
5019
5020 /* l4_abe -> mcbsp3 */
5021 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5022         .master         = &omap44xx_l4_abe_hwmod,
5023         .slave          = &omap44xx_mcbsp3_hwmod,
5024         .clk            = "ocp_abe_iclk",
5025         .addr           = omap44xx_mcbsp3_addrs,
5026         .user           = OCP_USER_MPU,
5027 };
5028
5029 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5030         {
5031                 .name           = "dma",
5032                 .pa_start       = 0x49026000,
5033                 .pa_end         = 0x490260ff,
5034                 .flags          = ADDR_TYPE_RT
5035         },
5036         { }
5037 };
5038
5039 /* l4_abe -> mcbsp3 (dma) */
5040 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5041         .master         = &omap44xx_l4_abe_hwmod,
5042         .slave          = &omap44xx_mcbsp3_hwmod,
5043         .clk            = "ocp_abe_iclk",
5044         .addr           = omap44xx_mcbsp3_dma_addrs,
5045         .user           = OCP_USER_SDMA,
5046 };
5047
5048 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5049         {
5050                 .pa_start       = 0x48096000,
5051                 .pa_end         = 0x480960ff,
5052                 .flags          = ADDR_TYPE_RT
5053         },
5054         { }
5055 };
5056
5057 /* l4_per -> mcbsp4 */
5058 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5059         .master         = &omap44xx_l4_per_hwmod,
5060         .slave          = &omap44xx_mcbsp4_hwmod,
5061         .clk            = "l4_div_ck",
5062         .addr           = omap44xx_mcbsp4_addrs,
5063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5064 };
5065
5066 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5067         {
5068                 .pa_start       = 0x40132000,
5069                 .pa_end         = 0x4013207f,
5070                 .flags          = ADDR_TYPE_RT
5071         },
5072         { }
5073 };
5074
5075 /* l4_abe -> mcpdm */
5076 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5077         .master         = &omap44xx_l4_abe_hwmod,
5078         .slave          = &omap44xx_mcpdm_hwmod,
5079         .clk            = "ocp_abe_iclk",
5080         .addr           = omap44xx_mcpdm_addrs,
5081         .user           = OCP_USER_MPU,
5082 };
5083
5084 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5085         {
5086                 .pa_start       = 0x49032000,
5087                 .pa_end         = 0x4903207f,
5088                 .flags          = ADDR_TYPE_RT
5089         },
5090         { }
5091 };
5092
5093 /* l4_abe -> mcpdm (dma) */
5094 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5095         .master         = &omap44xx_l4_abe_hwmod,
5096         .slave          = &omap44xx_mcpdm_hwmod,
5097         .clk            = "ocp_abe_iclk",
5098         .addr           = omap44xx_mcpdm_dma_addrs,
5099         .user           = OCP_USER_SDMA,
5100 };
5101
5102 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5103         {
5104                 .pa_start       = 0x48098000,
5105                 .pa_end         = 0x480981ff,
5106                 .flags          = ADDR_TYPE_RT
5107         },
5108         { }
5109 };
5110
5111 /* l4_per -> mcspi1 */
5112 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5113         .master         = &omap44xx_l4_per_hwmod,
5114         .slave          = &omap44xx_mcspi1_hwmod,
5115         .clk            = "l4_div_ck",
5116         .addr           = omap44xx_mcspi1_addrs,
5117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5118 };
5119
5120 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5121         {
5122                 .pa_start       = 0x4809a000,
5123                 .pa_end         = 0x4809a1ff,
5124                 .flags          = ADDR_TYPE_RT
5125         },
5126         { }
5127 };
5128
5129 /* l4_per -> mcspi2 */
5130 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5131         .master         = &omap44xx_l4_per_hwmod,
5132         .slave          = &omap44xx_mcspi2_hwmod,
5133         .clk            = "l4_div_ck",
5134         .addr           = omap44xx_mcspi2_addrs,
5135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5136 };
5137
5138 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5139         {
5140                 .pa_start       = 0x480b8000,
5141                 .pa_end         = 0x480b81ff,
5142                 .flags          = ADDR_TYPE_RT
5143         },
5144         { }
5145 };
5146
5147 /* l4_per -> mcspi3 */
5148 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5149         .master         = &omap44xx_l4_per_hwmod,
5150         .slave          = &omap44xx_mcspi3_hwmod,
5151         .clk            = "l4_div_ck",
5152         .addr           = omap44xx_mcspi3_addrs,
5153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5154 };
5155
5156 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5157         {
5158                 .pa_start       = 0x480ba000,
5159                 .pa_end         = 0x480ba1ff,
5160                 .flags          = ADDR_TYPE_RT
5161         },
5162         { }
5163 };
5164
5165 /* l4_per -> mcspi4 */
5166 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5167         .master         = &omap44xx_l4_per_hwmod,
5168         .slave          = &omap44xx_mcspi4_hwmod,
5169         .clk            = "l4_div_ck",
5170         .addr           = omap44xx_mcspi4_addrs,
5171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5172 };
5173
5174 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5175         {
5176                 .pa_start       = 0x4809c000,
5177                 .pa_end         = 0x4809c3ff,
5178                 .flags          = ADDR_TYPE_RT
5179         },
5180         { }
5181 };
5182
5183 /* l4_per -> mmc1 */
5184 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5185         .master         = &omap44xx_l4_per_hwmod,
5186         .slave          = &omap44xx_mmc1_hwmod,
5187         .clk            = "l4_div_ck",
5188         .addr           = omap44xx_mmc1_addrs,
5189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5190 };
5191
5192 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5193         {
5194                 .pa_start       = 0x480b4000,
5195                 .pa_end         = 0x480b43ff,
5196                 .flags          = ADDR_TYPE_RT
5197         },
5198         { }
5199 };
5200
5201 /* l4_per -> mmc2 */
5202 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5203         .master         = &omap44xx_l4_per_hwmod,
5204         .slave          = &omap44xx_mmc2_hwmod,
5205         .clk            = "l4_div_ck",
5206         .addr           = omap44xx_mmc2_addrs,
5207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5208 };
5209
5210 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5211         {
5212                 .pa_start       = 0x480ad000,
5213                 .pa_end         = 0x480ad3ff,
5214                 .flags          = ADDR_TYPE_RT
5215         },
5216         { }
5217 };
5218
5219 /* l4_per -> mmc3 */
5220 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5221         .master         = &omap44xx_l4_per_hwmod,
5222         .slave          = &omap44xx_mmc3_hwmod,
5223         .clk            = "l4_div_ck",
5224         .addr           = omap44xx_mmc3_addrs,
5225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5226 };
5227
5228 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5229         {
5230                 .pa_start       = 0x480d1000,
5231                 .pa_end         = 0x480d13ff,
5232                 .flags          = ADDR_TYPE_RT
5233         },
5234         { }
5235 };
5236
5237 /* l4_per -> mmc4 */
5238 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5239         .master         = &omap44xx_l4_per_hwmod,
5240         .slave          = &omap44xx_mmc4_hwmod,
5241         .clk            = "l4_div_ck",
5242         .addr           = omap44xx_mmc4_addrs,
5243         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5244 };
5245
5246 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5247         {
5248                 .pa_start       = 0x480d5000,
5249                 .pa_end         = 0x480d53ff,
5250                 .flags          = ADDR_TYPE_RT
5251         },
5252         { }
5253 };
5254
5255 /* l4_per -> mmc5 */
5256 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5257         .master         = &omap44xx_l4_per_hwmod,
5258         .slave          = &omap44xx_mmc5_hwmod,
5259         .clk            = "l4_div_ck",
5260         .addr           = omap44xx_mmc5_addrs,
5261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5262 };
5263
5264 /* l3_main_2 -> ocmc_ram */
5265 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5266         .master         = &omap44xx_l3_main_2_hwmod,
5267         .slave          = &omap44xx_ocmc_ram_hwmod,
5268         .clk            = "l3_div_ck",
5269         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5270 };
5271
5272 /* l4_cfg -> ocp2scp_usb_phy */
5273 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5274         .master         = &omap44xx_l4_cfg_hwmod,
5275         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5276         .clk            = "l4_div_ck",
5277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5278 };
5279
5280 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5281         {
5282                 .pa_start       = 0x48243000,
5283                 .pa_end         = 0x48243fff,
5284                 .flags          = ADDR_TYPE_RT
5285         },
5286         { }
5287 };
5288
5289 /* mpu_private -> prcm_mpu */
5290 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5291         .master         = &omap44xx_mpu_private_hwmod,
5292         .slave          = &omap44xx_prcm_mpu_hwmod,
5293         .clk            = "l3_div_ck",
5294         .addr           = omap44xx_prcm_mpu_addrs,
5295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5296 };
5297
5298 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5299         {
5300                 .pa_start       = 0x4a004000,
5301                 .pa_end         = 0x4a004fff,
5302                 .flags          = ADDR_TYPE_RT
5303         },
5304         { }
5305 };
5306
5307 /* l4_wkup -> cm_core_aon */
5308 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5309         .master         = &omap44xx_l4_wkup_hwmod,
5310         .slave          = &omap44xx_cm_core_aon_hwmod,
5311         .clk            = "l4_wkup_clk_mux_ck",
5312         .addr           = omap44xx_cm_core_aon_addrs,
5313         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5314 };
5315
5316 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5317         {
5318                 .pa_start       = 0x4a008000,
5319                 .pa_end         = 0x4a009fff,
5320                 .flags          = ADDR_TYPE_RT
5321         },
5322         { }
5323 };
5324
5325 /* l4_cfg -> cm_core */
5326 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5327         .master         = &omap44xx_l4_cfg_hwmod,
5328         .slave          = &omap44xx_cm_core_hwmod,
5329         .clk            = "l4_div_ck",
5330         .addr           = omap44xx_cm_core_addrs,
5331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5332 };
5333
5334 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5335         {
5336                 .pa_start       = 0x4a306000,
5337                 .pa_end         = 0x4a307fff,
5338                 .flags          = ADDR_TYPE_RT
5339         },
5340         { }
5341 };
5342
5343 /* l4_wkup -> prm */
5344 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5345         .master         = &omap44xx_l4_wkup_hwmod,
5346         .slave          = &omap44xx_prm_hwmod,
5347         .clk            = "l4_wkup_clk_mux_ck",
5348         .addr           = omap44xx_prm_addrs,
5349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5350 };
5351
5352 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5353         {
5354                 .pa_start       = 0x4a30a000,
5355                 .pa_end         = 0x4a30a7ff,
5356                 .flags          = ADDR_TYPE_RT
5357         },
5358         { }
5359 };
5360
5361 /* l4_wkup -> scrm */
5362 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5363         .master         = &omap44xx_l4_wkup_hwmod,
5364         .slave          = &omap44xx_scrm_hwmod,
5365         .clk            = "l4_wkup_clk_mux_ck",
5366         .addr           = omap44xx_scrm_addrs,
5367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5368 };
5369
5370 /* l3_main_2 -> sl2if */
5371 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5372         .master         = &omap44xx_l3_main_2_hwmod,
5373         .slave          = &omap44xx_sl2if_hwmod,
5374         .clk            = "l3_div_ck",
5375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5376 };
5377
5378 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5379         {
5380                 .pa_start       = 0x4012c000,
5381                 .pa_end         = 0x4012c3ff,
5382                 .flags          = ADDR_TYPE_RT
5383         },
5384         { }
5385 };
5386
5387 /* l4_abe -> slimbus1 */
5388 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5389         .master         = &omap44xx_l4_abe_hwmod,
5390         .slave          = &omap44xx_slimbus1_hwmod,
5391         .clk            = "ocp_abe_iclk",
5392         .addr           = omap44xx_slimbus1_addrs,
5393         .user           = OCP_USER_MPU,
5394 };
5395
5396 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5397         {
5398                 .pa_start       = 0x4902c000,
5399                 .pa_end         = 0x4902c3ff,
5400                 .flags          = ADDR_TYPE_RT
5401         },
5402         { }
5403 };
5404
5405 /* l4_abe -> slimbus1 (dma) */
5406 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5407         .master         = &omap44xx_l4_abe_hwmod,
5408         .slave          = &omap44xx_slimbus1_hwmod,
5409         .clk            = "ocp_abe_iclk",
5410         .addr           = omap44xx_slimbus1_dma_addrs,
5411         .user           = OCP_USER_SDMA,
5412 };
5413
5414 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5415         {
5416                 .pa_start       = 0x48076000,
5417                 .pa_end         = 0x480763ff,
5418                 .flags          = ADDR_TYPE_RT
5419         },
5420         { }
5421 };
5422
5423 /* l4_per -> slimbus2 */
5424 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5425         .master         = &omap44xx_l4_per_hwmod,
5426         .slave          = &omap44xx_slimbus2_hwmod,
5427         .clk            = "l4_div_ck",
5428         .addr           = omap44xx_slimbus2_addrs,
5429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5430 };
5431
5432 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5433         {
5434                 .pa_start       = 0x4a0dd000,
5435                 .pa_end         = 0x4a0dd03f,
5436                 .flags          = ADDR_TYPE_RT
5437         },
5438         { }
5439 };
5440
5441 /* l4_cfg -> smartreflex_core */
5442 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5443         .master         = &omap44xx_l4_cfg_hwmod,
5444         .slave          = &omap44xx_smartreflex_core_hwmod,
5445         .clk            = "l4_div_ck",
5446         .addr           = omap44xx_smartreflex_core_addrs,
5447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5448 };
5449
5450 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5451         {
5452                 .pa_start       = 0x4a0db000,
5453                 .pa_end         = 0x4a0db03f,
5454                 .flags          = ADDR_TYPE_RT
5455         },
5456         { }
5457 };
5458
5459 /* l4_cfg -> smartreflex_iva */
5460 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5461         .master         = &omap44xx_l4_cfg_hwmod,
5462         .slave          = &omap44xx_smartreflex_iva_hwmod,
5463         .clk            = "l4_div_ck",
5464         .addr           = omap44xx_smartreflex_iva_addrs,
5465         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5466 };
5467
5468 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5469         {
5470                 .pa_start       = 0x4a0d9000,
5471                 .pa_end         = 0x4a0d903f,
5472                 .flags          = ADDR_TYPE_RT
5473         },
5474         { }
5475 };
5476
5477 /* l4_cfg -> smartreflex_mpu */
5478 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5479         .master         = &omap44xx_l4_cfg_hwmod,
5480         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5481         .clk            = "l4_div_ck",
5482         .addr           = omap44xx_smartreflex_mpu_addrs,
5483         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5484 };
5485
5486 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5487         {
5488                 .pa_start       = 0x4a0f6000,
5489                 .pa_end         = 0x4a0f6fff,
5490                 .flags          = ADDR_TYPE_RT
5491         },
5492         { }
5493 };
5494
5495 /* l4_cfg -> spinlock */
5496 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5497         .master         = &omap44xx_l4_cfg_hwmod,
5498         .slave          = &omap44xx_spinlock_hwmod,
5499         .clk            = "l4_div_ck",
5500         .addr           = omap44xx_spinlock_addrs,
5501         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5502 };
5503
5504 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5505         {
5506                 .pa_start       = 0x4a318000,
5507                 .pa_end         = 0x4a31807f,
5508                 .flags          = ADDR_TYPE_RT
5509         },
5510         { }
5511 };
5512
5513 /* l4_wkup -> timer1 */
5514 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5515         .master         = &omap44xx_l4_wkup_hwmod,
5516         .slave          = &omap44xx_timer1_hwmod,
5517         .clk            = "l4_wkup_clk_mux_ck",
5518         .addr           = omap44xx_timer1_addrs,
5519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5520 };
5521
5522 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5523         {
5524                 .pa_start       = 0x48032000,
5525                 .pa_end         = 0x4803207f,
5526                 .flags          = ADDR_TYPE_RT
5527         },
5528         { }
5529 };
5530
5531 /* l4_per -> timer2 */
5532 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5533         .master         = &omap44xx_l4_per_hwmod,
5534         .slave          = &omap44xx_timer2_hwmod,
5535         .clk            = "l4_div_ck",
5536         .addr           = omap44xx_timer2_addrs,
5537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5538 };
5539
5540 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5541         {
5542                 .pa_start       = 0x48034000,
5543                 .pa_end         = 0x4803407f,
5544                 .flags          = ADDR_TYPE_RT
5545         },
5546         { }
5547 };
5548
5549 /* l4_per -> timer3 */
5550 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5551         .master         = &omap44xx_l4_per_hwmod,
5552         .slave          = &omap44xx_timer3_hwmod,
5553         .clk            = "l4_div_ck",
5554         .addr           = omap44xx_timer3_addrs,
5555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5556 };
5557
5558 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5559         {
5560                 .pa_start       = 0x48036000,
5561                 .pa_end         = 0x4803607f,
5562                 .flags          = ADDR_TYPE_RT
5563         },
5564         { }
5565 };
5566
5567 /* l4_per -> timer4 */
5568 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5569         .master         = &omap44xx_l4_per_hwmod,
5570         .slave          = &omap44xx_timer4_hwmod,
5571         .clk            = "l4_div_ck",
5572         .addr           = omap44xx_timer4_addrs,
5573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5574 };
5575
5576 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5577         {
5578                 .pa_start       = 0x40138000,
5579                 .pa_end         = 0x4013807f,
5580                 .flags          = ADDR_TYPE_RT
5581         },
5582         { }
5583 };
5584
5585 /* l4_abe -> timer5 */
5586 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5587         .master         = &omap44xx_l4_abe_hwmod,
5588         .slave          = &omap44xx_timer5_hwmod,
5589         .clk            = "ocp_abe_iclk",
5590         .addr           = omap44xx_timer5_addrs,
5591         .user           = OCP_USER_MPU,
5592 };
5593
5594 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5595         {
5596                 .pa_start       = 0x49038000,
5597                 .pa_end         = 0x4903807f,
5598                 .flags          = ADDR_TYPE_RT
5599         },
5600         { }
5601 };
5602
5603 /* l4_abe -> timer5 (dma) */
5604 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5605         .master         = &omap44xx_l4_abe_hwmod,
5606         .slave          = &omap44xx_timer5_hwmod,
5607         .clk            = "ocp_abe_iclk",
5608         .addr           = omap44xx_timer5_dma_addrs,
5609         .user           = OCP_USER_SDMA,
5610 };
5611
5612 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5613         {
5614                 .pa_start       = 0x4013a000,
5615                 .pa_end         = 0x4013a07f,
5616                 .flags          = ADDR_TYPE_RT
5617         },
5618         { }
5619 };
5620
5621 /* l4_abe -> timer6 */
5622 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5623         .master         = &omap44xx_l4_abe_hwmod,
5624         .slave          = &omap44xx_timer6_hwmod,
5625         .clk            = "ocp_abe_iclk",
5626         .addr           = omap44xx_timer6_addrs,
5627         .user           = OCP_USER_MPU,
5628 };
5629
5630 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5631         {
5632                 .pa_start       = 0x4903a000,
5633                 .pa_end         = 0x4903a07f,
5634                 .flags          = ADDR_TYPE_RT
5635         },
5636         { }
5637 };
5638
5639 /* l4_abe -> timer6 (dma) */
5640 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5641         .master         = &omap44xx_l4_abe_hwmod,
5642         .slave          = &omap44xx_timer6_hwmod,
5643         .clk            = "ocp_abe_iclk",
5644         .addr           = omap44xx_timer6_dma_addrs,
5645         .user           = OCP_USER_SDMA,
5646 };
5647
5648 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5649         {
5650                 .pa_start       = 0x4013c000,
5651                 .pa_end         = 0x4013c07f,
5652                 .flags          = ADDR_TYPE_RT
5653         },
5654         { }
5655 };
5656
5657 /* l4_abe -> timer7 */
5658 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5659         .master         = &omap44xx_l4_abe_hwmod,
5660         .slave          = &omap44xx_timer7_hwmod,
5661         .clk            = "ocp_abe_iclk",
5662         .addr           = omap44xx_timer7_addrs,
5663         .user           = OCP_USER_MPU,
5664 };
5665
5666 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5667         {
5668                 .pa_start       = 0x4903c000,
5669                 .pa_end         = 0x4903c07f,
5670                 .flags          = ADDR_TYPE_RT
5671         },
5672         { }
5673 };
5674
5675 /* l4_abe -> timer7 (dma) */
5676 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5677         .master         = &omap44xx_l4_abe_hwmod,
5678         .slave          = &omap44xx_timer7_hwmod,
5679         .clk            = "ocp_abe_iclk",
5680         .addr           = omap44xx_timer7_dma_addrs,
5681         .user           = OCP_USER_SDMA,
5682 };
5683
5684 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5685         {
5686                 .pa_start       = 0x4013e000,
5687                 .pa_end         = 0x4013e07f,
5688                 .flags          = ADDR_TYPE_RT
5689         },
5690         { }
5691 };
5692
5693 /* l4_abe -> timer8 */
5694 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5695         .master         = &omap44xx_l4_abe_hwmod,
5696         .slave          = &omap44xx_timer8_hwmod,
5697         .clk            = "ocp_abe_iclk",
5698         .addr           = omap44xx_timer8_addrs,
5699         .user           = OCP_USER_MPU,
5700 };
5701
5702 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5703         {
5704                 .pa_start       = 0x4903e000,
5705                 .pa_end         = 0x4903e07f,
5706                 .flags          = ADDR_TYPE_RT
5707         },
5708         { }
5709 };
5710
5711 /* l4_abe -> timer8 (dma) */
5712 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5713         .master         = &omap44xx_l4_abe_hwmod,
5714         .slave          = &omap44xx_timer8_hwmod,
5715         .clk            = "ocp_abe_iclk",
5716         .addr           = omap44xx_timer8_dma_addrs,
5717         .user           = OCP_USER_SDMA,
5718 };
5719
5720 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5721         {
5722                 .pa_start       = 0x4803e000,
5723                 .pa_end         = 0x4803e07f,
5724                 .flags          = ADDR_TYPE_RT
5725         },
5726         { }
5727 };
5728
5729 /* l4_per -> timer9 */
5730 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5731         .master         = &omap44xx_l4_per_hwmod,
5732         .slave          = &omap44xx_timer9_hwmod,
5733         .clk            = "l4_div_ck",
5734         .addr           = omap44xx_timer9_addrs,
5735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5736 };
5737
5738 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5739         {
5740                 .pa_start       = 0x48086000,
5741                 .pa_end         = 0x4808607f,
5742                 .flags          = ADDR_TYPE_RT
5743         },
5744         { }
5745 };
5746
5747 /* l4_per -> timer10 */
5748 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5749         .master         = &omap44xx_l4_per_hwmod,
5750         .slave          = &omap44xx_timer10_hwmod,
5751         .clk            = "l4_div_ck",
5752         .addr           = omap44xx_timer10_addrs,
5753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5754 };
5755
5756 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5757         {
5758                 .pa_start       = 0x48088000,
5759                 .pa_end         = 0x4808807f,
5760                 .flags          = ADDR_TYPE_RT
5761         },
5762         { }
5763 };
5764
5765 /* l4_per -> timer11 */
5766 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5767         .master         = &omap44xx_l4_per_hwmod,
5768         .slave          = &omap44xx_timer11_hwmod,
5769         .clk            = "l4_div_ck",
5770         .addr           = omap44xx_timer11_addrs,
5771         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5772 };
5773
5774 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5775         {
5776                 .pa_start       = 0x4806a000,
5777                 .pa_end         = 0x4806a0ff,
5778                 .flags          = ADDR_TYPE_RT
5779         },
5780         { }
5781 };
5782
5783 /* l4_per -> uart1 */
5784 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5785         .master         = &omap44xx_l4_per_hwmod,
5786         .slave          = &omap44xx_uart1_hwmod,
5787         .clk            = "l4_div_ck",
5788         .addr           = omap44xx_uart1_addrs,
5789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5790 };
5791
5792 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5793         {
5794                 .pa_start       = 0x4806c000,
5795                 .pa_end         = 0x4806c0ff,
5796                 .flags          = ADDR_TYPE_RT
5797         },
5798         { }
5799 };
5800
5801 /* l4_per -> uart2 */
5802 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5803         .master         = &omap44xx_l4_per_hwmod,
5804         .slave          = &omap44xx_uart2_hwmod,
5805         .clk            = "l4_div_ck",
5806         .addr           = omap44xx_uart2_addrs,
5807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5808 };
5809
5810 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5811         {
5812                 .pa_start       = 0x48020000,
5813                 .pa_end         = 0x480200ff,
5814                 .flags          = ADDR_TYPE_RT
5815         },
5816         { }
5817 };
5818
5819 /* l4_per -> uart3 */
5820 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5821         .master         = &omap44xx_l4_per_hwmod,
5822         .slave          = &omap44xx_uart3_hwmod,
5823         .clk            = "l4_div_ck",
5824         .addr           = omap44xx_uart3_addrs,
5825         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5826 };
5827
5828 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5829         {
5830                 .pa_start       = 0x4806e000,
5831                 .pa_end         = 0x4806e0ff,
5832                 .flags          = ADDR_TYPE_RT
5833         },
5834         { }
5835 };
5836
5837 /* l4_per -> uart4 */
5838 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5839         .master         = &omap44xx_l4_per_hwmod,
5840         .slave          = &omap44xx_uart4_hwmod,
5841         .clk            = "l4_div_ck",
5842         .addr           = omap44xx_uart4_addrs,
5843         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5844 };
5845
5846 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5847         {
5848                 .pa_start       = 0x4a0a9000,
5849                 .pa_end         = 0x4a0a93ff,
5850                 .flags          = ADDR_TYPE_RT
5851         },
5852         { }
5853 };
5854
5855 /* l4_cfg -> usb_host_fs */
5856 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
5857         .master         = &omap44xx_l4_cfg_hwmod,
5858         .slave          = &omap44xx_usb_host_fs_hwmod,
5859         .clk            = "l4_div_ck",
5860         .addr           = omap44xx_usb_host_fs_addrs,
5861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5862 };
5863
5864 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5865         {
5866                 .name           = "uhh",
5867                 .pa_start       = 0x4a064000,
5868                 .pa_end         = 0x4a0647ff,
5869                 .flags          = ADDR_TYPE_RT
5870         },
5871         {
5872                 .name           = "ohci",
5873                 .pa_start       = 0x4a064800,
5874                 .pa_end         = 0x4a064bff,
5875         },
5876         {
5877                 .name           = "ehci",
5878                 .pa_start       = 0x4a064c00,
5879                 .pa_end         = 0x4a064fff,
5880         },
5881         {}
5882 };
5883
5884 /* l4_cfg -> usb_host_hs */
5885 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5886         .master         = &omap44xx_l4_cfg_hwmod,
5887         .slave          = &omap44xx_usb_host_hs_hwmod,
5888         .clk            = "l4_div_ck",
5889         .addr           = omap44xx_usb_host_hs_addrs,
5890         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5891 };
5892
5893 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5894         {
5895                 .pa_start       = 0x4a0ab000,
5896                 .pa_end         = 0x4a0ab003,
5897                 .flags          = ADDR_TYPE_RT
5898         },
5899         { }
5900 };
5901
5902 /* l4_cfg -> usb_otg_hs */
5903 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5904         .master         = &omap44xx_l4_cfg_hwmod,
5905         .slave          = &omap44xx_usb_otg_hs_hwmod,
5906         .clk            = "l4_div_ck",
5907         .addr           = omap44xx_usb_otg_hs_addrs,
5908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5909 };
5910
5911 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5912         {
5913                 .name           = "tll",
5914                 .pa_start       = 0x4a062000,
5915                 .pa_end         = 0x4a063fff,
5916                 .flags          = ADDR_TYPE_RT
5917         },
5918         {}
5919 };
5920
5921 /* l4_cfg -> usb_tll_hs */
5922 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5923         .master         = &omap44xx_l4_cfg_hwmod,
5924         .slave          = &omap44xx_usb_tll_hs_hwmod,
5925         .clk            = "l4_div_ck",
5926         .addr           = omap44xx_usb_tll_hs_addrs,
5927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5928 };
5929
5930 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5931         {
5932                 .pa_start       = 0x4a314000,
5933                 .pa_end         = 0x4a31407f,
5934                 .flags          = ADDR_TYPE_RT
5935         },
5936         { }
5937 };
5938
5939 /* l4_wkup -> wd_timer2 */
5940 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5941         .master         = &omap44xx_l4_wkup_hwmod,
5942         .slave          = &omap44xx_wd_timer2_hwmod,
5943         .clk            = "l4_wkup_clk_mux_ck",
5944         .addr           = omap44xx_wd_timer2_addrs,
5945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5946 };
5947
5948 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5949         {
5950                 .pa_start       = 0x40130000,
5951                 .pa_end         = 0x4013007f,
5952                 .flags          = ADDR_TYPE_RT
5953         },
5954         { }
5955 };
5956
5957 /* l4_abe -> wd_timer3 */
5958 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5959         .master         = &omap44xx_l4_abe_hwmod,
5960         .slave          = &omap44xx_wd_timer3_hwmod,
5961         .clk            = "ocp_abe_iclk",
5962         .addr           = omap44xx_wd_timer3_addrs,
5963         .user           = OCP_USER_MPU,
5964 };
5965
5966 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5967         {
5968                 .pa_start       = 0x49030000,
5969                 .pa_end         = 0x4903007f,
5970                 .flags          = ADDR_TYPE_RT
5971         },
5972         { }
5973 };
5974
5975 /* l4_abe -> wd_timer3 (dma) */
5976 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5977         .master         = &omap44xx_l4_abe_hwmod,
5978         .slave          = &omap44xx_wd_timer3_hwmod,
5979         .clk            = "ocp_abe_iclk",
5980         .addr           = omap44xx_wd_timer3_dma_addrs,
5981         .user           = OCP_USER_SDMA,
5982 };
5983
5984 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5985         &omap44xx_c2c__c2c_target_fw,
5986         &omap44xx_l4_cfg__c2c_target_fw,
5987         &omap44xx_l3_main_1__dmm,
5988         &omap44xx_mpu__dmm,
5989         &omap44xx_c2c__emif_fw,
5990         &omap44xx_dmm__emif_fw,
5991         &omap44xx_l4_cfg__emif_fw,
5992         &omap44xx_iva__l3_instr,
5993         &omap44xx_l3_main_3__l3_instr,
5994         &omap44xx_ocp_wp_noc__l3_instr,
5995         &omap44xx_dsp__l3_main_1,
5996         &omap44xx_dss__l3_main_1,
5997         &omap44xx_l3_main_2__l3_main_1,
5998         &omap44xx_l4_cfg__l3_main_1,
5999         &omap44xx_mmc1__l3_main_1,
6000         &omap44xx_mmc2__l3_main_1,
6001         &omap44xx_mpu__l3_main_1,
6002         &omap44xx_c2c_target_fw__l3_main_2,
6003         &omap44xx_debugss__l3_main_2,
6004         &omap44xx_dma_system__l3_main_2,
6005         &omap44xx_fdif__l3_main_2,
6006         &omap44xx_gpu__l3_main_2,
6007         &omap44xx_hsi__l3_main_2,
6008         &omap44xx_ipu__l3_main_2,
6009         &omap44xx_iss__l3_main_2,
6010         &omap44xx_iva__l3_main_2,
6011         &omap44xx_l3_main_1__l3_main_2,
6012         &omap44xx_l4_cfg__l3_main_2,
6013         &omap44xx_usb_host_fs__l3_main_2,
6014         &omap44xx_usb_host_hs__l3_main_2,
6015         &omap44xx_usb_otg_hs__l3_main_2,
6016         &omap44xx_l3_main_1__l3_main_3,
6017         &omap44xx_l3_main_2__l3_main_3,
6018         &omap44xx_l4_cfg__l3_main_3,
6019         &omap44xx_aess__l4_abe,
6020         &omap44xx_dsp__l4_abe,
6021         &omap44xx_l3_main_1__l4_abe,
6022         &omap44xx_mpu__l4_abe,
6023         &omap44xx_l3_main_1__l4_cfg,
6024         &omap44xx_l3_main_2__l4_per,
6025         &omap44xx_l4_cfg__l4_wkup,
6026         &omap44xx_mpu__mpu_private,
6027         &omap44xx_l4_cfg__ocp_wp_noc,
6028         &omap44xx_l4_abe__aess,
6029         &omap44xx_l4_abe__aess_dma,
6030         &omap44xx_l3_main_2__c2c,
6031         &omap44xx_l4_wkup__counter_32k,
6032         &omap44xx_l4_cfg__ctrl_module_core,
6033         &omap44xx_l4_cfg__ctrl_module_pad_core,
6034         &omap44xx_l4_wkup__ctrl_module_wkup,
6035         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6036         &omap44xx_l3_instr__debugss,
6037         &omap44xx_l4_cfg__dma_system,
6038         &omap44xx_l4_abe__dmic,
6039         &omap44xx_l4_abe__dmic_dma,
6040         &omap44xx_dsp__iva,
6041         &omap44xx_dsp__sl2if,
6042         &omap44xx_l4_cfg__dsp,
6043         &omap44xx_l3_main_2__dss,
6044         &omap44xx_l4_per__dss,
6045         &omap44xx_l3_main_2__dss_dispc,
6046         &omap44xx_l4_per__dss_dispc,
6047         &omap44xx_l3_main_2__dss_dsi1,
6048         &omap44xx_l4_per__dss_dsi1,
6049         &omap44xx_l3_main_2__dss_dsi2,
6050         &omap44xx_l4_per__dss_dsi2,
6051         &omap44xx_l3_main_2__dss_hdmi,
6052         &omap44xx_l4_per__dss_hdmi,
6053         &omap44xx_l3_main_2__dss_rfbi,
6054         &omap44xx_l4_per__dss_rfbi,
6055         &omap44xx_l3_main_2__dss_venc,
6056         &omap44xx_l4_per__dss_venc,
6057         &omap44xx_l4_per__elm,
6058         &omap44xx_emif_fw__emif1,
6059         &omap44xx_emif_fw__emif2,
6060         &omap44xx_l4_cfg__fdif,
6061         &omap44xx_l4_wkup__gpio1,
6062         &omap44xx_l4_per__gpio2,
6063         &omap44xx_l4_per__gpio3,
6064         &omap44xx_l4_per__gpio4,
6065         &omap44xx_l4_per__gpio5,
6066         &omap44xx_l4_per__gpio6,
6067         &omap44xx_l3_main_2__gpmc,
6068         &omap44xx_l3_main_2__gpu,
6069         &omap44xx_l4_per__hdq1w,
6070         &omap44xx_l4_cfg__hsi,
6071         &omap44xx_l4_per__i2c1,
6072         &omap44xx_l4_per__i2c2,
6073         &omap44xx_l4_per__i2c3,
6074         &omap44xx_l4_per__i2c4,
6075         &omap44xx_l3_main_2__ipu,
6076         &omap44xx_l3_main_2__iss,
6077         &omap44xx_iva__sl2if,
6078         &omap44xx_l3_main_2__iva,
6079         &omap44xx_l4_wkup__kbd,
6080         &omap44xx_l4_cfg__mailbox,
6081         &omap44xx_l4_abe__mcasp,
6082         &omap44xx_l4_abe__mcasp_dma,
6083         &omap44xx_l4_abe__mcbsp1,
6084         &omap44xx_l4_abe__mcbsp1_dma,
6085         &omap44xx_l4_abe__mcbsp2,
6086         &omap44xx_l4_abe__mcbsp2_dma,
6087         &omap44xx_l4_abe__mcbsp3,
6088         &omap44xx_l4_abe__mcbsp3_dma,
6089         &omap44xx_l4_per__mcbsp4,
6090         &omap44xx_l4_abe__mcpdm,
6091         &omap44xx_l4_abe__mcpdm_dma,
6092         &omap44xx_l4_per__mcspi1,
6093         &omap44xx_l4_per__mcspi2,
6094         &omap44xx_l4_per__mcspi3,
6095         &omap44xx_l4_per__mcspi4,
6096         &omap44xx_l4_per__mmc1,
6097         &omap44xx_l4_per__mmc2,
6098         &omap44xx_l4_per__mmc3,
6099         &omap44xx_l4_per__mmc4,
6100         &omap44xx_l4_per__mmc5,
6101         &omap44xx_l3_main_2__ocmc_ram,
6102         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6103         &omap44xx_mpu_private__prcm_mpu,
6104         &omap44xx_l4_wkup__cm_core_aon,
6105         &omap44xx_l4_cfg__cm_core,
6106         &omap44xx_l4_wkup__prm,
6107         &omap44xx_l4_wkup__scrm,
6108         &omap44xx_l3_main_2__sl2if,
6109         &omap44xx_l4_abe__slimbus1,
6110         &omap44xx_l4_abe__slimbus1_dma,
6111         &omap44xx_l4_per__slimbus2,
6112         &omap44xx_l4_cfg__smartreflex_core,
6113         &omap44xx_l4_cfg__smartreflex_iva,
6114         &omap44xx_l4_cfg__smartreflex_mpu,
6115         &omap44xx_l4_cfg__spinlock,
6116         &omap44xx_l4_wkup__timer1,
6117         &omap44xx_l4_per__timer2,
6118         &omap44xx_l4_per__timer3,
6119         &omap44xx_l4_per__timer4,
6120         &omap44xx_l4_abe__timer5,
6121         &omap44xx_l4_abe__timer5_dma,
6122         &omap44xx_l4_abe__timer6,
6123         &omap44xx_l4_abe__timer6_dma,
6124         &omap44xx_l4_abe__timer7,
6125         &omap44xx_l4_abe__timer7_dma,
6126         &omap44xx_l4_abe__timer8,
6127         &omap44xx_l4_abe__timer8_dma,
6128         &omap44xx_l4_per__timer9,
6129         &omap44xx_l4_per__timer10,
6130         &omap44xx_l4_per__timer11,
6131         &omap44xx_l4_per__uart1,
6132         &omap44xx_l4_per__uart2,
6133         &omap44xx_l4_per__uart3,
6134         &omap44xx_l4_per__uart4,
6135         &omap44xx_l4_cfg__usb_host_fs,
6136         &omap44xx_l4_cfg__usb_host_hs,
6137         &omap44xx_l4_cfg__usb_otg_hs,
6138         &omap44xx_l4_cfg__usb_tll_hs,
6139         &omap44xx_l4_wkup__wd_timer2,
6140         &omap44xx_l4_abe__wd_timer3,
6141         &omap44xx_l4_abe__wd_timer3_dma,
6142         NULL,
6143 };
6144
6145 int __init omap44xx_hwmod_init(void)
6146 {
6147         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6148 }
6149