Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "smartreflex.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /*
  54  * 'c2c_target_fw' class
  55  * instance(s): c2c_target_fw
  56  */
  57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58         .name   = "c2c_target_fw",
  59 };
  60
  61 /* c2c_target_fw */
  62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63         .name           = "c2c_target_fw",
  64         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  65         .clkdm_name     = "d2d_clkdm",
  66         .prcm = {
  67                 .omap4 = {
  68                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm */
  83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85         { .irq = -1 }
  86 };
  87
  88 static struct omap_hwmod omap44xx_dmm_hwmod = {
  89         .name           = "dmm",
  90         .class          = &omap44xx_dmm_hwmod_class,
  91         .clkdm_name     = "l3_emif_clkdm",
  92         .mpu_irqs       = omap44xx_dmm_irqs,
  93         .prcm = {
  94                 .omap4 = {
  95                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97                 },
  98         },
  99 };
 100
 101 /*
 102  * 'emif_fw' class
 103  * instance(s): emif_fw
 104  */
 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106         .name   = "emif_fw",
 107 };
 108
 109 /* emif_fw */
 110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111         .name           = "emif_fw",
 112         .class          = &omap44xx_emif_fw_hwmod_class,
 113         .clkdm_name     = "l3_emif_clkdm",
 114         .prcm = {
 115                 .omap4 = {
 116                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'l3' class
 124  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125  */
 126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127         .name   = "l3",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &omap44xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_instr_clkdm",
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139                         .modulemode   = MODULEMODE_HWCTRL,
 140                 },
 141         },
 142 };
 143
 144 /* l3_main_1 */
 145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148         { .irq = -1 }
 149 };
 150
 151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152         .name           = "l3_main_1",
 153         .class          = &omap44xx_l3_hwmod_class,
 154         .clkdm_name     = "l3_1_clkdm",
 155         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160                 },
 161         },
 162 };
 163
 164 /* l3_main_2 */
 165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166         .name           = "l3_main_2",
 167         .class          = &omap44xx_l3_hwmod_class,
 168         .clkdm_name     = "l3_2_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173                 },
 174         },
 175 };
 176
 177 /* l3_main_3 */
 178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179         .name           = "l3_main_3",
 180         .class          = &omap44xx_l3_hwmod_class,
 181         .clkdm_name     = "l3_instr_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186                         .modulemode   = MODULEMODE_HWCTRL,
 187                 },
 188         },
 189 };
 190
 191 /*
 192  * 'l4' class
 193  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194  */
 195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196         .name   = "l4",
 197 };
 198
 199 /* l4_abe */
 200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201         .name           = "l4_abe",
 202         .class          = &omap44xx_l4_hwmod_class,
 203         .clkdm_name     = "abe_clkdm",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207                 },
 208         },
 209 };
 210
 211 /* l4_cfg */
 212 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 213         .name           = "l4_cfg",
 214         .class          = &omap44xx_l4_hwmod_class,
 215         .clkdm_name     = "l4_cfg_clkdm",
 216         .prcm = {
 217                 .omap4 = {
 218                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 219                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 220                 },
 221         },
 222 };
 223
 224 /* l4_per */
 225 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 226         .name           = "l4_per",
 227         .class          = &omap44xx_l4_hwmod_class,
 228         .clkdm_name     = "l4_per_clkdm",
 229         .prcm = {
 230                 .omap4 = {
 231                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 232                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 233                 },
 234         },
 235 };
 236
 237 /* l4_wkup */
 238 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 239         .name           = "l4_wkup",
 240         .class          = &omap44xx_l4_hwmod_class,
 241         .clkdm_name     = "l4_wkup_clkdm",
 242         .prcm = {
 243                 .omap4 = {
 244                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 245                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 246                 },
 247         },
 248 };
 249
 250 /*
 251  * 'mpu_bus' class
 252  * instance(s): mpu_private
 253  */
 254 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 255         .name   = "mpu_bus",
 256 };
 257
 258 /* mpu_private */
 259 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 260         .name           = "mpu_private",
 261         .class          = &omap44xx_mpu_bus_hwmod_class,
 262         .clkdm_name     = "mpuss_clkdm",
 263 };
 264
 265 /*
 266  * 'ocp_wp_noc' class
 267  * instance(s): ocp_wp_noc
 268  */
 269 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 270         .name   = "ocp_wp_noc",
 271 };
 272
 273 /* ocp_wp_noc */
 274 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 275         .name           = "ocp_wp_noc",
 276         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 277         .clkdm_name     = "l3_instr_clkdm",
 278         .prcm = {
 279                 .omap4 = {
 280                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 281                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 282                         .modulemode   = MODULEMODE_HWCTRL,
 283                 },
 284         },
 285 };
 286
 287 /*
 288  * Modules omap_hwmod structures
 289  *
 290  * The following IPs are excluded for the moment because:
 291  * - They do not need an explicit SW control using omap_hwmod API.
 292  * - They still need to be validated with the driver
 293  *   properly adapted to omap_hwmod / omap_device
 294  *
 295  * usim
 296  */
 297
 298 /*
 299  * 'aess' class
 300  * audio engine sub system
 301  */
 302
 303 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 304         .rev_offs       = 0x0000,
 305         .sysc_offs      = 0x0010,
 306         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 308                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 309                            MSTANDBY_SMART_WKUP),
 310         .sysc_fields    = &omap_hwmod_sysc_type2,
 311 };
 312
 313 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 314         .name   = "aess",
 315         .sysc   = &omap44xx_aess_sysc,
 316 };
 317
 318 /* aess */
 319 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 320         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 321         { .irq = -1 }
 322 };
 323
 324 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 325         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 326         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 327         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 328         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 329         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 330         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 331         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 332         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 333         { .dma_req = -1 }
 334 };
 335
 336 static struct omap_hwmod omap44xx_aess_hwmod = {
 337         .name           = "aess",
 338         .class          = &omap44xx_aess_hwmod_class,
 339         .clkdm_name     = "abe_clkdm",
 340         .mpu_irqs       = omap44xx_aess_irqs,
 341         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 342         .main_clk       = "aess_fck",
 343         .prcm = {
 344                 .omap4 = {
 345                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 346                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 347                         .modulemode   = MODULEMODE_SWCTRL,
 348                 },
 349         },
 350 };
 351
 352 /*
 353  * 'c2c' class
 354  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 355  * soc
 356  */
 357
 358 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 359         .name   = "c2c",
 360 };
 361
 362 /* c2c */
 363 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 364         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 365         { .irq = -1 }
 366 };
 367
 368 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 369         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 370         { .dma_req = -1 }
 371 };
 372
 373 static struct omap_hwmod omap44xx_c2c_hwmod = {
 374         .name           = "c2c",
 375         .class          = &omap44xx_c2c_hwmod_class,
 376         .clkdm_name     = "d2d_clkdm",
 377         .mpu_irqs       = omap44xx_c2c_irqs,
 378         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 382                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 383                 },
 384         },
 385 };
 386
 387 /*
 388  * 'counter' class
 389  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 390  */
 391
 392 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 393         .rev_offs       = 0x0000,
 394         .sysc_offs      = 0x0004,
 395         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 396         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 397         .sysc_fields    = &omap_hwmod_sysc_type1,
 398 };
 399
 400 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 401         .name   = "counter",
 402         .sysc   = &omap44xx_counter_sysc,
 403 };
 404
 405 /* counter_32k */
 406 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 407         .name           = "counter_32k",
 408         .class          = &omap44xx_counter_hwmod_class,
 409         .clkdm_name     = "l4_wkup_clkdm",
 410         .flags          = HWMOD_SWSUP_SIDLE,
 411         .main_clk       = "sys_32k_ck",
 412         .prcm = {
 413                 .omap4 = {
 414                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 415                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 416                 },
 417         },
 418 };
 419
 420 /*
 421  * 'ctrl_module' class
 422  * attila core control module + core pad control module + wkup pad control
 423  * module + attila wkup control module
 424  */
 425
 426 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 427         .rev_offs       = 0x0000,
 428         .sysc_offs      = 0x0010,
 429         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 430         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 431                            SIDLE_SMART_WKUP),
 432         .sysc_fields    = &omap_hwmod_sysc_type2,
 433 };
 434
 435 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 436         .name   = "ctrl_module",
 437         .sysc   = &omap44xx_ctrl_module_sysc,
 438 };
 439
 440 /* ctrl_module_core */
 441 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 442         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 443         { .irq = -1 }
 444 };
 445
 446 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 447         .name           = "ctrl_module_core",
 448         .class          = &omap44xx_ctrl_module_hwmod_class,
 449         .clkdm_name     = "l4_cfg_clkdm",
 450         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 451 };
 452
 453 /* ctrl_module_pad_core */
 454 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 455         .name           = "ctrl_module_pad_core",
 456         .class          = &omap44xx_ctrl_module_hwmod_class,
 457         .clkdm_name     = "l4_cfg_clkdm",
 458 };
 459
 460 /* ctrl_module_wkup */
 461 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 462         .name           = "ctrl_module_wkup",
 463         .class          = &omap44xx_ctrl_module_hwmod_class,
 464         .clkdm_name     = "l4_wkup_clkdm",
 465 };
 466
 467 /* ctrl_module_pad_wkup */
 468 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 469         .name           = "ctrl_module_pad_wkup",
 470         .class          = &omap44xx_ctrl_module_hwmod_class,
 471         .clkdm_name     = "l4_wkup_clkdm",
 472 };
 473
 474 /*
 475  * 'debugss' class
 476  * debug and emulation sub system
 477  */
 478
 479 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 480         .name   = "debugss",
 481 };
 482
 483 /* debugss */
 484 static struct omap_hwmod omap44xx_debugss_hwmod = {
 485         .name           = "debugss",
 486         .class          = &omap44xx_debugss_hwmod_class,
 487         .clkdm_name     = "emu_sys_clkdm",
 488         .main_clk       = "trace_clk_div_ck",
 489         .prcm = {
 490                 .omap4 = {
 491                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 492                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 493                 },
 494         },
 495 };
 496
 497 /*
 498  * 'dma' class
 499  * dma controller for data exchange between memory to memory (i.e. internal or
 500  * external memory) and gp peripherals to memory or memory to gp peripherals
 501  */
 502
 503 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 504         .rev_offs       = 0x0000,
 505         .sysc_offs      = 0x002c,
 506         .syss_offs      = 0x0028,
 507         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 508                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 509                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 510                            SYSS_HAS_RESET_STATUS),
 511         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 512                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 513         .sysc_fields    = &omap_hwmod_sysc_type1,
 514 };
 515
 516 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 517         .name   = "dma",
 518         .sysc   = &omap44xx_dma_sysc,
 519 };
 520
 521 /* dma dev_attr */
 522 static struct omap_dma_dev_attr dma_dev_attr = {
 523         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 524                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 525         .lch_count      = 32,
 526 };
 527
 528 /* dma_system */
 529 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 530         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 531         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 532         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 533         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 534         { .irq = -1 }
 535 };
 536
 537 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 538         .name           = "dma_system",
 539         .class          = &omap44xx_dma_hwmod_class,
 540         .clkdm_name     = "l3_dma_clkdm",
 541         .mpu_irqs       = omap44xx_dma_system_irqs,
 542         .main_clk       = "l3_div_ck",
 543         .prcm = {
 544                 .omap4 = {
 545                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 546                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 547                 },
 548         },
 549         .dev_attr       = &dma_dev_attr,
 550 };
 551
 552 /*
 553  * 'dmic' class
 554  * digital microphone controller
 555  */
 556
 557 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 558         .rev_offs       = 0x0000,
 559         .sysc_offs      = 0x0010,
 560         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 561                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 562         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 563                            SIDLE_SMART_WKUP),
 564         .sysc_fields    = &omap_hwmod_sysc_type2,
 565 };
 566
 567 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 568         .name   = "dmic",
 569         .sysc   = &omap44xx_dmic_sysc,
 570 };
 571
 572 /* dmic */
 573 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 574         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 575         { .irq = -1 }
 576 };
 577
 578 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 579         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 580         { .dma_req = -1 }
 581 };
 582
 583 static struct omap_hwmod omap44xx_dmic_hwmod = {
 584         .name           = "dmic",
 585         .class          = &omap44xx_dmic_hwmod_class,
 586         .clkdm_name     = "abe_clkdm",
 587         .mpu_irqs       = omap44xx_dmic_irqs,
 588         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 589         .main_clk       = "dmic_fck",
 590         .prcm = {
 591                 .omap4 = {
 592                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 593                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 594                         .modulemode   = MODULEMODE_SWCTRL,
 595                 },
 596         },
 597 };
 598
 599 /*
 600  * 'dsp' class
 601  * dsp sub-system
 602  */
 603
 604 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 605         .name   = "dsp",
 606 };
 607
 608 /* dsp */
 609 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 610         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 611         { .irq = -1 }
 612 };
 613
 614 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 615         { .name = "dsp", .rst_shift = 0 },
 616         { .name = "mmu_cache", .rst_shift = 1 },
 617 };
 618
 619 static struct omap_hwmod omap44xx_dsp_hwmod = {
 620         .name           = "dsp",
 621         .class          = &omap44xx_dsp_hwmod_class,
 622         .clkdm_name     = "tesla_clkdm",
 623         .mpu_irqs       = omap44xx_dsp_irqs,
 624         .rst_lines      = omap44xx_dsp_resets,
 625         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 626         .main_clk       = "dsp_fck",
 627         .prcm = {
 628                 .omap4 = {
 629                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 630                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 631                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 632                         .modulemode   = MODULEMODE_HWCTRL,
 633                 },
 634         },
 635 };
 636
 637 /*
 638  * 'dss' class
 639  * display sub-system
 640  */
 641
 642 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 643         .rev_offs       = 0x0000,
 644         .syss_offs      = 0x0014,
 645         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 646 };
 647
 648 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 649         .name   = "dss",
 650         .sysc   = &omap44xx_dss_sysc,
 651         .reset  = omap_dss_reset,
 652 };
 653
 654 /* dss */
 655 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 656         { .role = "sys_clk", .clk = "dss_sys_clk" },
 657         { .role = "tv_clk", .clk = "dss_tv_clk" },
 658         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 659 };
 660
 661 static struct omap_hwmod omap44xx_dss_hwmod = {
 662         .name           = "dss_core",
 663         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 664         .class          = &omap44xx_dss_hwmod_class,
 665         .clkdm_name     = "l3_dss_clkdm",
 666         .main_clk       = "dss_dss_clk",
 667         .prcm = {
 668                 .omap4 = {
 669                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 670                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 671                 },
 672         },
 673         .opt_clks       = dss_opt_clks,
 674         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 675 };
 676
 677 /*
 678  * 'dispc' class
 679  * display controller
 680  */
 681
 682 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 683         .rev_offs       = 0x0000,
 684         .sysc_offs      = 0x0010,
 685         .syss_offs      = 0x0014,
 686         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 687                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 688                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 689                            SYSS_HAS_RESET_STATUS),
 690         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 691                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 692         .sysc_fields    = &omap_hwmod_sysc_type1,
 693 };
 694
 695 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 696         .name   = "dispc",
 697         .sysc   = &omap44xx_dispc_sysc,
 698 };
 699
 700 /* dss_dispc */
 701 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 702         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 703         { .irq = -1 }
 704 };
 705
 706 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 707         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 708         { .dma_req = -1 }
 709 };
 710
 711 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 712         .manager_count          = 3,
 713         .has_framedonetv_irq    = 1
 714 };
 715
 716 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 717         .name           = "dss_dispc",
 718         .class          = &omap44xx_dispc_hwmod_class,
 719         .clkdm_name     = "l3_dss_clkdm",
 720         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 721         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 722         .main_clk       = "dss_dss_clk",
 723         .prcm = {
 724                 .omap4 = {
 725                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 726                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 727                 },
 728         },
 729         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 730 };
 731
 732 /*
 733  * 'dsi' class
 734  * display serial interface controller
 735  */
 736
 737 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 738         .rev_offs       = 0x0000,
 739         .sysc_offs      = 0x0010,
 740         .syss_offs      = 0x0014,
 741         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 742                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 743                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 744         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 745         .sysc_fields    = &omap_hwmod_sysc_type1,
 746 };
 747
 748 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 749         .name   = "dsi",
 750         .sysc   = &omap44xx_dsi_sysc,
 751 };
 752
 753 /* dss_dsi1 */
 754 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 755         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 756         { .irq = -1 }
 757 };
 758
 759 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 760         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 761         { .dma_req = -1 }
 762 };
 763
 764 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 765         { .role = "sys_clk", .clk = "dss_sys_clk" },
 766 };
 767
 768 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 769         .name           = "dss_dsi1",
 770         .class          = &omap44xx_dsi_hwmod_class,
 771         .clkdm_name     = "l3_dss_clkdm",
 772         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 773         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 774         .main_clk       = "dss_dss_clk",
 775         .prcm = {
 776                 .omap4 = {
 777                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 778                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 779                 },
 780         },
 781         .opt_clks       = dss_dsi1_opt_clks,
 782         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 783 };
 784
 785 /* dss_dsi2 */
 786 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 787         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 788         { .irq = -1 }
 789 };
 790
 791 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 792         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 793         { .dma_req = -1 }
 794 };
 795
 796 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 797         { .role = "sys_clk", .clk = "dss_sys_clk" },
 798 };
 799
 800 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 801         .name           = "dss_dsi2",
 802         .class          = &omap44xx_dsi_hwmod_class,
 803         .clkdm_name     = "l3_dss_clkdm",
 804         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 805         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 806         .main_clk       = "dss_dss_clk",
 807         .prcm = {
 808                 .omap4 = {
 809                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 810                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 811                 },
 812         },
 813         .opt_clks       = dss_dsi2_opt_clks,
 814         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 815 };
 816
 817 /*
 818  * 'hdmi' class
 819  * hdmi controller
 820  */
 821
 822 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 823         .rev_offs       = 0x0000,
 824         .sysc_offs      = 0x0010,
 825         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 826                            SYSC_HAS_SOFTRESET),
 827         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 828                            SIDLE_SMART_WKUP),
 829         .sysc_fields    = &omap_hwmod_sysc_type2,
 830 };
 831
 832 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 833         .name   = "hdmi",
 834         .sysc   = &omap44xx_hdmi_sysc,
 835 };
 836
 837 /* dss_hdmi */
 838 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 839         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 840         { .irq = -1 }
 841 };
 842
 843 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 844         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 845         { .dma_req = -1 }
 846 };
 847
 848 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 849         { .role = "sys_clk", .clk = "dss_sys_clk" },
 850 };
 851
 852 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 853         .name           = "dss_hdmi",
 854         .class          = &omap44xx_hdmi_hwmod_class,
 855         .clkdm_name     = "l3_dss_clkdm",
 856         /*
 857          * HDMI audio requires to use no-idle mode. Hence,
 858          * set idle mode by software.
 859          */
 860         .flags          = HWMOD_SWSUP_SIDLE,
 861         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 862         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 863         .main_clk       = "dss_48mhz_clk",
 864         .prcm = {
 865                 .omap4 = {
 866                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 867                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 868                 },
 869         },
 870         .opt_clks       = dss_hdmi_opt_clks,
 871         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 872 };
 873
 874 /*
 875  * 'rfbi' class
 876  * remote frame buffer interface
 877  */
 878
 879 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 880         .rev_offs       = 0x0000,
 881         .sysc_offs      = 0x0010,
 882         .syss_offs      = 0x0014,
 883         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 884                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 885         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 886         .sysc_fields    = &omap_hwmod_sysc_type1,
 887 };
 888
 889 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 890         .name   = "rfbi",
 891         .sysc   = &omap44xx_rfbi_sysc,
 892 };
 893
 894 /* dss_rfbi */
 895 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 896         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 897         { .dma_req = -1 }
 898 };
 899
 900 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 901         { .role = "ick", .clk = "dss_fck" },
 902 };
 903
 904 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 905         .name           = "dss_rfbi",
 906         .class          = &omap44xx_rfbi_hwmod_class,
 907         .clkdm_name     = "l3_dss_clkdm",
 908         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 909         .main_clk       = "dss_dss_clk",
 910         .prcm = {
 911                 .omap4 = {
 912                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 913                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 914                 },
 915         },
 916         .opt_clks       = dss_rfbi_opt_clks,
 917         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 918 };
 919
 920 /*
 921  * 'venc' class
 922  * video encoder
 923  */
 924
 925 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 926         .name   = "venc",
 927 };
 928
 929 /* dss_venc */
 930 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 931         .name           = "dss_venc",
 932         .class          = &omap44xx_venc_hwmod_class,
 933         .clkdm_name     = "l3_dss_clkdm",
 934         .main_clk       = "dss_tv_clk",
 935         .prcm = {
 936                 .omap4 = {
 937                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 938                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 939                 },
 940         },
 941 };
 942
 943 /*
 944  * 'elm' class
 945  * bch error location module
 946  */
 947
 948 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 949         .rev_offs       = 0x0000,
 950         .sysc_offs      = 0x0010,
 951         .syss_offs      = 0x0014,
 952         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 953                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 954                            SYSS_HAS_RESET_STATUS),
 955         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 956         .sysc_fields    = &omap_hwmod_sysc_type1,
 957 };
 958
 959 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 960         .name   = "elm",
 961         .sysc   = &omap44xx_elm_sysc,
 962 };
 963
 964 /* elm */
 965 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 966         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 967         { .irq = -1 }
 968 };
 969
 970 static struct omap_hwmod omap44xx_elm_hwmod = {
 971         .name           = "elm",
 972         .class          = &omap44xx_elm_hwmod_class,
 973         .clkdm_name     = "l4_per_clkdm",
 974         .mpu_irqs       = omap44xx_elm_irqs,
 975         .prcm = {
 976                 .omap4 = {
 977                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 978                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 979                 },
 980         },
 981 };
 982
 983 /*
 984  * 'emif' class
 985  * external memory interface no1
 986  */
 987
 988 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 989         .rev_offs       = 0x0000,
 990 };
 991
 992 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 993         .name   = "emif",
 994         .sysc   = &omap44xx_emif_sysc,
 995 };
 996
 997 /* emif1 */
 998 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
 999         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1000         { .irq = -1 }
1001 };
1002
1003 static struct omap_hwmod omap44xx_emif1_hwmod = {
1004         .name           = "emif1",
1005         .class          = &omap44xx_emif_hwmod_class,
1006         .clkdm_name     = "l3_emif_clkdm",
1007         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1008         .mpu_irqs       = omap44xx_emif1_irqs,
1009         .main_clk       = "ddrphy_ck",
1010         .prcm = {
1011                 .omap4 = {
1012                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1013                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1014                         .modulemode   = MODULEMODE_HWCTRL,
1015                 },
1016         },
1017 };
1018
1019 /* emif2 */
1020 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1021         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1022         { .irq = -1 }
1023 };
1024
1025 static struct omap_hwmod omap44xx_emif2_hwmod = {
1026         .name           = "emif2",
1027         .class          = &omap44xx_emif_hwmod_class,
1028         .clkdm_name     = "l3_emif_clkdm",
1029         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1030         .mpu_irqs       = omap44xx_emif2_irqs,
1031         .main_clk       = "ddrphy_ck",
1032         .prcm = {
1033                 .omap4 = {
1034                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1035                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1036                         .modulemode   = MODULEMODE_HWCTRL,
1037                 },
1038         },
1039 };
1040
1041 /*
1042  * 'fdif' class
1043  * face detection hw accelerator module
1044  */
1045
1046 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1047         .rev_offs       = 0x0000,
1048         .sysc_offs      = 0x0010,
1049         /*
1050          * FDIF needs 100 OCP clk cycles delay after a softreset before
1051          * accessing sysconfig again.
1052          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1053          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1054          *
1055          * TODO: Indicate errata when available.
1056          */
1057         .srst_udelay    = 2,
1058         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1059                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1060         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1061                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1062         .sysc_fields    = &omap_hwmod_sysc_type2,
1063 };
1064
1065 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1066         .name   = "fdif",
1067         .sysc   = &omap44xx_fdif_sysc,
1068 };
1069
1070 /* fdif */
1071 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1072         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1073         { .irq = -1 }
1074 };
1075
1076 static struct omap_hwmod omap44xx_fdif_hwmod = {
1077         .name           = "fdif",
1078         .class          = &omap44xx_fdif_hwmod_class,
1079         .clkdm_name     = "iss_clkdm",
1080         .mpu_irqs       = omap44xx_fdif_irqs,
1081         .main_clk       = "fdif_fck",
1082         .prcm = {
1083                 .omap4 = {
1084                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1085                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1086                         .modulemode   = MODULEMODE_SWCTRL,
1087                 },
1088         },
1089 };
1090
1091 /*
1092  * 'gpio' class
1093  * general purpose io module
1094  */
1095
1096 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1097         .rev_offs       = 0x0000,
1098         .sysc_offs      = 0x0010,
1099         .syss_offs      = 0x0114,
1100         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1101                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1102                            SYSS_HAS_RESET_STATUS),
1103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1104                            SIDLE_SMART_WKUP),
1105         .sysc_fields    = &omap_hwmod_sysc_type1,
1106 };
1107
1108 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1109         .name   = "gpio",
1110         .sysc   = &omap44xx_gpio_sysc,
1111         .rev    = 2,
1112 };
1113
1114 /* gpio dev_attr */
1115 static struct omap_gpio_dev_attr gpio_dev_attr = {
1116         .bank_width     = 32,
1117         .dbck_flag      = true,
1118 };
1119
1120 /* gpio1 */
1121 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1122         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1123         { .irq = -1 }
1124 };
1125
1126 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1127         { .role = "dbclk", .clk = "gpio1_dbclk" },
1128 };
1129
1130 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1131         .name           = "gpio1",
1132         .class          = &omap44xx_gpio_hwmod_class,
1133         .clkdm_name     = "l4_wkup_clkdm",
1134         .mpu_irqs       = omap44xx_gpio1_irqs,
1135         .main_clk       = "gpio1_ick",
1136         .prcm = {
1137                 .omap4 = {
1138                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1139                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1140                         .modulemode   = MODULEMODE_HWCTRL,
1141                 },
1142         },
1143         .opt_clks       = gpio1_opt_clks,
1144         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1145         .dev_attr       = &gpio_dev_attr,
1146 };
1147
1148 /* gpio2 */
1149 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1150         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1151         { .irq = -1 }
1152 };
1153
1154 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1155         { .role = "dbclk", .clk = "gpio2_dbclk" },
1156 };
1157
1158 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1159         .name           = "gpio2",
1160         .class          = &omap44xx_gpio_hwmod_class,
1161         .clkdm_name     = "l4_per_clkdm",
1162         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1163         .mpu_irqs       = omap44xx_gpio2_irqs,
1164         .main_clk       = "gpio2_ick",
1165         .prcm = {
1166                 .omap4 = {
1167                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1168                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1169                         .modulemode   = MODULEMODE_HWCTRL,
1170                 },
1171         },
1172         .opt_clks       = gpio2_opt_clks,
1173         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1174         .dev_attr       = &gpio_dev_attr,
1175 };
1176
1177 /* gpio3 */
1178 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1179         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1180         { .irq = -1 }
1181 };
1182
1183 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1184         { .role = "dbclk", .clk = "gpio3_dbclk" },
1185 };
1186
1187 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1188         .name           = "gpio3",
1189         .class          = &omap44xx_gpio_hwmod_class,
1190         .clkdm_name     = "l4_per_clkdm",
1191         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192         .mpu_irqs       = omap44xx_gpio3_irqs,
1193         .main_clk       = "gpio3_ick",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1197                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_HWCTRL,
1199                 },
1200         },
1201         .opt_clks       = gpio3_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1203         .dev_attr       = &gpio_dev_attr,
1204 };
1205
1206 /* gpio4 */
1207 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1208         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1209         { .irq = -1 }
1210 };
1211
1212 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1213         { .role = "dbclk", .clk = "gpio4_dbclk" },
1214 };
1215
1216 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1217         .name           = "gpio4",
1218         .class          = &omap44xx_gpio_hwmod_class,
1219         .clkdm_name     = "l4_per_clkdm",
1220         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221         .mpu_irqs       = omap44xx_gpio4_irqs,
1222         .main_clk       = "gpio4_ick",
1223         .prcm = {
1224                 .omap4 = {
1225                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1226                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1227                         .modulemode   = MODULEMODE_HWCTRL,
1228                 },
1229         },
1230         .opt_clks       = gpio4_opt_clks,
1231         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1232         .dev_attr       = &gpio_dev_attr,
1233 };
1234
1235 /* gpio5 */
1236 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1237         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1238         { .irq = -1 }
1239 };
1240
1241 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1242         { .role = "dbclk", .clk = "gpio5_dbclk" },
1243 };
1244
1245 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1246         .name           = "gpio5",
1247         .class          = &omap44xx_gpio_hwmod_class,
1248         .clkdm_name     = "l4_per_clkdm",
1249         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250         .mpu_irqs       = omap44xx_gpio5_irqs,
1251         .main_clk       = "gpio5_ick",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1255                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1256                         .modulemode   = MODULEMODE_HWCTRL,
1257                 },
1258         },
1259         .opt_clks       = gpio5_opt_clks,
1260         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1261         .dev_attr       = &gpio_dev_attr,
1262 };
1263
1264 /* gpio6 */
1265 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1266         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1267         { .irq = -1 }
1268 };
1269
1270 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1271         { .role = "dbclk", .clk = "gpio6_dbclk" },
1272 };
1273
1274 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1275         .name           = "gpio6",
1276         .class          = &omap44xx_gpio_hwmod_class,
1277         .clkdm_name     = "l4_per_clkdm",
1278         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279         .mpu_irqs       = omap44xx_gpio6_irqs,
1280         .main_clk       = "gpio6_ick",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1284                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_HWCTRL,
1286                 },
1287         },
1288         .opt_clks       = gpio6_opt_clks,
1289         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1290         .dev_attr       = &gpio_dev_attr,
1291 };
1292
1293 /*
1294  * 'gpmc' class
1295  * general purpose memory controller
1296  */
1297
1298 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1299         .rev_offs       = 0x0000,
1300         .sysc_offs      = 0x0010,
1301         .syss_offs      = 0x0014,
1302         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1303                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1304         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1305         .sysc_fields    = &omap_hwmod_sysc_type1,
1306 };
1307
1308 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1309         .name   = "gpmc",
1310         .sysc   = &omap44xx_gpmc_sysc,
1311 };
1312
1313 /* gpmc */
1314 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1315         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1316         { .irq = -1 }
1317 };
1318
1319 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1320         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1321         { .dma_req = -1 }
1322 };
1323
1324 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1325         .name           = "gpmc",
1326         .class          = &omap44xx_gpmc_hwmod_class,
1327         .clkdm_name     = "l3_2_clkdm",
1328         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1329         .mpu_irqs       = omap44xx_gpmc_irqs,
1330         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1331         .prcm = {
1332                 .omap4 = {
1333                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1334                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1335                         .modulemode   = MODULEMODE_HWCTRL,
1336                 },
1337         },
1338 };
1339
1340 /*
1341  * 'gpu' class
1342  * 2d/3d graphics accelerator
1343  */
1344
1345 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1346         .rev_offs       = 0x1fc00,
1347         .sysc_offs      = 0x1fc10,
1348         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1349         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1350                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1351                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1352         .sysc_fields    = &omap_hwmod_sysc_type2,
1353 };
1354
1355 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1356         .name   = "gpu",
1357         .sysc   = &omap44xx_gpu_sysc,
1358 };
1359
1360 /* gpu */
1361 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1362         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1363         { .irq = -1 }
1364 };
1365
1366 static struct omap_hwmod omap44xx_gpu_hwmod = {
1367         .name           = "gpu",
1368         .class          = &omap44xx_gpu_hwmod_class,
1369         .clkdm_name     = "l3_gfx_clkdm",
1370         .mpu_irqs       = omap44xx_gpu_irqs,
1371         .main_clk       = "gpu_fck",
1372         .prcm = {
1373                 .omap4 = {
1374                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1375                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1376                         .modulemode   = MODULEMODE_SWCTRL,
1377                 },
1378         },
1379 };
1380
1381 /*
1382  * 'hdq1w' class
1383  * hdq / 1-wire serial interface controller
1384  */
1385
1386 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1387         .rev_offs       = 0x0000,
1388         .sysc_offs      = 0x0014,
1389         .syss_offs      = 0x0018,
1390         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1391                            SYSS_HAS_RESET_STATUS),
1392         .sysc_fields    = &omap_hwmod_sysc_type1,
1393 };
1394
1395 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1396         .name   = "hdq1w",
1397         .sysc   = &omap44xx_hdq1w_sysc,
1398 };
1399
1400 /* hdq1w */
1401 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1402         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1403         { .irq = -1 }
1404 };
1405
1406 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1407         .name           = "hdq1w",
1408         .class          = &omap44xx_hdq1w_hwmod_class,
1409         .clkdm_name     = "l4_per_clkdm",
1410         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1411         .mpu_irqs       = omap44xx_hdq1w_irqs,
1412         .main_clk       = "hdq1w_fck",
1413         .prcm = {
1414                 .omap4 = {
1415                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1416                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1417                         .modulemode   = MODULEMODE_SWCTRL,
1418                 },
1419         },
1420 };
1421
1422 /*
1423  * 'hsi' class
1424  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1425  * serial if)
1426  */
1427
1428 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1429         .rev_offs       = 0x0000,
1430         .sysc_offs      = 0x0010,
1431         .syss_offs      = 0x0014,
1432         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1433                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1434                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1435         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1436                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1437                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1438         .sysc_fields    = &omap_hwmod_sysc_type1,
1439 };
1440
1441 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1442         .name   = "hsi",
1443         .sysc   = &omap44xx_hsi_sysc,
1444 };
1445
1446 /* hsi */
1447 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1448         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1449         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1450         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1451         { .irq = -1 }
1452 };
1453
1454 static struct omap_hwmod omap44xx_hsi_hwmod = {
1455         .name           = "hsi",
1456         .class          = &omap44xx_hsi_hwmod_class,
1457         .clkdm_name     = "l3_init_clkdm",
1458         .mpu_irqs       = omap44xx_hsi_irqs,
1459         .main_clk       = "hsi_fck",
1460         .prcm = {
1461                 .omap4 = {
1462                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1463                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1464                         .modulemode   = MODULEMODE_HWCTRL,
1465                 },
1466         },
1467 };
1468
1469 /*
1470  * 'i2c' class
1471  * multimaster high-speed i2c controller
1472  */
1473
1474 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1475         .sysc_offs      = 0x0010,
1476         .syss_offs      = 0x0090,
1477         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1478                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1479                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1480         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1481                            SIDLE_SMART_WKUP),
1482         .clockact       = CLOCKACT_TEST_ICLK,
1483         .sysc_fields    = &omap_hwmod_sysc_type1,
1484 };
1485
1486 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1487         .name   = "i2c",
1488         .sysc   = &omap44xx_i2c_sysc,
1489         .rev    = OMAP_I2C_IP_VERSION_2,
1490         .reset  = &omap_i2c_reset,
1491 };
1492
1493 static struct omap_i2c_dev_attr i2c_dev_attr = {
1494         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1495                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1496 };
1497
1498 /* i2c1 */
1499 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1500         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1501         { .irq = -1 }
1502 };
1503
1504 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1505         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1506         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1507         { .dma_req = -1 }
1508 };
1509
1510 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1511         .name           = "i2c1",
1512         .class          = &omap44xx_i2c_hwmod_class,
1513         .clkdm_name     = "l4_per_clkdm",
1514         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1515         .mpu_irqs       = omap44xx_i2c1_irqs,
1516         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1517         .main_clk       = "i2c1_fck",
1518         .prcm = {
1519                 .omap4 = {
1520                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1521                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1522                         .modulemode   = MODULEMODE_SWCTRL,
1523                 },
1524         },
1525         .dev_attr       = &i2c_dev_attr,
1526 };
1527
1528 /* i2c2 */
1529 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1530         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1531         { .irq = -1 }
1532 };
1533
1534 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1535         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1536         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1537         { .dma_req = -1 }
1538 };
1539
1540 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1541         .name           = "i2c2",
1542         .class          = &omap44xx_i2c_hwmod_class,
1543         .clkdm_name     = "l4_per_clkdm",
1544         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1545         .mpu_irqs       = omap44xx_i2c2_irqs,
1546         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1547         .main_clk       = "i2c2_fck",
1548         .prcm = {
1549                 .omap4 = {
1550                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1551                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1552                         .modulemode   = MODULEMODE_SWCTRL,
1553                 },
1554         },
1555         .dev_attr       = &i2c_dev_attr,
1556 };
1557
1558 /* i2c3 */
1559 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1560         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1561         { .irq = -1 }
1562 };
1563
1564 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1565         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1566         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1567         { .dma_req = -1 }
1568 };
1569
1570 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1571         .name           = "i2c3",
1572         .class          = &omap44xx_i2c_hwmod_class,
1573         .clkdm_name     = "l4_per_clkdm",
1574         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1575         .mpu_irqs       = omap44xx_i2c3_irqs,
1576         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1577         .main_clk       = "i2c3_fck",
1578         .prcm = {
1579                 .omap4 = {
1580                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1581                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1582                         .modulemode   = MODULEMODE_SWCTRL,
1583                 },
1584         },
1585         .dev_attr       = &i2c_dev_attr,
1586 };
1587
1588 /* i2c4 */
1589 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1590         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1591         { .irq = -1 }
1592 };
1593
1594 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1595         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1596         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1597         { .dma_req = -1 }
1598 };
1599
1600 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1601         .name           = "i2c4",
1602         .class          = &omap44xx_i2c_hwmod_class,
1603         .clkdm_name     = "l4_per_clkdm",
1604         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1605         .mpu_irqs       = omap44xx_i2c4_irqs,
1606         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1607         .main_clk       = "i2c4_fck",
1608         .prcm = {
1609                 .omap4 = {
1610                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1611                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1612                         .modulemode   = MODULEMODE_SWCTRL,
1613                 },
1614         },
1615         .dev_attr       = &i2c_dev_attr,
1616 };
1617
1618 /*
1619  * 'ipu' class
1620  * imaging processor unit
1621  */
1622
1623 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1624         .name   = "ipu",
1625 };
1626
1627 /* ipu */
1628 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1629         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1630         { .irq = -1 }
1631 };
1632
1633 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1634         { .name = "cpu0", .rst_shift = 0 },
1635         { .name = "cpu1", .rst_shift = 1 },
1636         { .name = "mmu_cache", .rst_shift = 2 },
1637 };
1638
1639 static struct omap_hwmod omap44xx_ipu_hwmod = {
1640         .name           = "ipu",
1641         .class          = &omap44xx_ipu_hwmod_class,
1642         .clkdm_name     = "ducati_clkdm",
1643         .mpu_irqs       = omap44xx_ipu_irqs,
1644         .rst_lines      = omap44xx_ipu_resets,
1645         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1646         .main_clk       = "ipu_fck",
1647         .prcm = {
1648                 .omap4 = {
1649                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1650                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1651                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1652                         .modulemode   = MODULEMODE_HWCTRL,
1653                 },
1654         },
1655 };
1656
1657 /*
1658  * 'iss' class
1659  * external images sensor pixel data processor
1660  */
1661
1662 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1663         .rev_offs       = 0x0000,
1664         .sysc_offs      = 0x0010,
1665         /*
1666          * ISS needs 100 OCP clk cycles delay after a softreset before
1667          * accessing sysconfig again.
1668          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1669          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1670          *
1671          * TODO: Indicate errata when available.
1672          */
1673         .srst_udelay    = 2,
1674         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1675                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1676         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1677                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1678                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1679         .sysc_fields    = &omap_hwmod_sysc_type2,
1680 };
1681
1682 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1683         .name   = "iss",
1684         .sysc   = &omap44xx_iss_sysc,
1685 };
1686
1687 /* iss */
1688 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1689         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1690         { .irq = -1 }
1691 };
1692
1693 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1694         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1695         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1696         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1697         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1698         { .dma_req = -1 }
1699 };
1700
1701 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1702         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1703 };
1704
1705 static struct omap_hwmod omap44xx_iss_hwmod = {
1706         .name           = "iss",
1707         .class          = &omap44xx_iss_hwmod_class,
1708         .clkdm_name     = "iss_clkdm",
1709         .mpu_irqs       = omap44xx_iss_irqs,
1710         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1711         .main_clk       = "iss_fck",
1712         .prcm = {
1713                 .omap4 = {
1714                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1715                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1716                         .modulemode   = MODULEMODE_SWCTRL,
1717                 },
1718         },
1719         .opt_clks       = iss_opt_clks,
1720         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1721 };
1722
1723 /*
1724  * 'iva' class
1725  * multi-standard video encoder/decoder hardware accelerator
1726  */
1727
1728 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1729         .name   = "iva",
1730 };
1731
1732 /* iva */
1733 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1734         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1735         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1736         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1737         { .irq = -1 }
1738 };
1739
1740 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1741         { .name = "seq0", .rst_shift = 0 },
1742         { .name = "seq1", .rst_shift = 1 },
1743         { .name = "logic", .rst_shift = 2 },
1744 };
1745
1746 static struct omap_hwmod omap44xx_iva_hwmod = {
1747         .name           = "iva",
1748         .class          = &omap44xx_iva_hwmod_class,
1749         .clkdm_name     = "ivahd_clkdm",
1750         .mpu_irqs       = omap44xx_iva_irqs,
1751         .rst_lines      = omap44xx_iva_resets,
1752         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1753         .main_clk       = "iva_fck",
1754         .prcm = {
1755                 .omap4 = {
1756                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1757                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1758                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1759                         .modulemode   = MODULEMODE_HWCTRL,
1760                 },
1761         },
1762 };
1763
1764 /*
1765  * 'kbd' class
1766  * keyboard controller
1767  */
1768
1769 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1770         .rev_offs       = 0x0000,
1771         .sysc_offs      = 0x0010,
1772         .syss_offs      = 0x0014,
1773         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1774                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1775                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1776                            SYSS_HAS_RESET_STATUS),
1777         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1778         .sysc_fields    = &omap_hwmod_sysc_type1,
1779 };
1780
1781 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1782         .name   = "kbd",
1783         .sysc   = &omap44xx_kbd_sysc,
1784 };
1785
1786 /* kbd */
1787 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1788         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1789         { .irq = -1 }
1790 };
1791
1792 static struct omap_hwmod omap44xx_kbd_hwmod = {
1793         .name           = "kbd",
1794         .class          = &omap44xx_kbd_hwmod_class,
1795         .clkdm_name     = "l4_wkup_clkdm",
1796         .mpu_irqs       = omap44xx_kbd_irqs,
1797         .main_clk       = "kbd_fck",
1798         .prcm = {
1799                 .omap4 = {
1800                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1801                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1802                         .modulemode   = MODULEMODE_SWCTRL,
1803                 },
1804         },
1805 };
1806
1807 /*
1808  * 'mailbox' class
1809  * mailbox module allowing communication between the on-chip processors using a
1810  * queued mailbox-interrupt mechanism.
1811  */
1812
1813 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1814         .rev_offs       = 0x0000,
1815         .sysc_offs      = 0x0010,
1816         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1817                            SYSC_HAS_SOFTRESET),
1818         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1819         .sysc_fields    = &omap_hwmod_sysc_type2,
1820 };
1821
1822 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1823         .name   = "mailbox",
1824         .sysc   = &omap44xx_mailbox_sysc,
1825 };
1826
1827 /* mailbox */
1828 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1829         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1830         { .irq = -1 }
1831 };
1832
1833 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1834         .name           = "mailbox",
1835         .class          = &omap44xx_mailbox_hwmod_class,
1836         .clkdm_name     = "l4_cfg_clkdm",
1837         .mpu_irqs       = omap44xx_mailbox_irqs,
1838         .prcm = {
1839                 .omap4 = {
1840                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1841                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1842                 },
1843         },
1844 };
1845
1846 /*
1847  * 'mcasp' class
1848  * multi-channel audio serial port controller
1849  */
1850
1851 /* The IP is not compliant to type1 / type2 scheme */
1852 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1853         .sidle_shift    = 0,
1854 };
1855
1856 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1857         .sysc_offs      = 0x0004,
1858         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1859         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860                            SIDLE_SMART_WKUP),
1861         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1862 };
1863
1864 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1865         .name   = "mcasp",
1866         .sysc   = &omap44xx_mcasp_sysc,
1867 };
1868
1869 /* mcasp */
1870 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1871         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1872         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1873         { .irq = -1 }
1874 };
1875
1876 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1877         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1878         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1879         { .dma_req = -1 }
1880 };
1881
1882 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1883         .name           = "mcasp",
1884         .class          = &omap44xx_mcasp_hwmod_class,
1885         .clkdm_name     = "abe_clkdm",
1886         .mpu_irqs       = omap44xx_mcasp_irqs,
1887         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1888         .main_clk       = "mcasp_fck",
1889         .prcm = {
1890                 .omap4 = {
1891                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1892                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1893                         .modulemode   = MODULEMODE_SWCTRL,
1894                 },
1895         },
1896 };
1897
1898 /*
1899  * 'mcbsp' class
1900  * multi channel buffered serial port controller
1901  */
1902
1903 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1904         .sysc_offs      = 0x008c,
1905         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1906                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1907         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1908         .sysc_fields    = &omap_hwmod_sysc_type1,
1909 };
1910
1911 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1912         .name   = "mcbsp",
1913         .sysc   = &omap44xx_mcbsp_sysc,
1914         .rev    = MCBSP_CONFIG_TYPE4,
1915 };
1916
1917 /* mcbsp1 */
1918 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1919         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1920         { .irq = -1 }
1921 };
1922
1923 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1924         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1925         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1926         { .dma_req = -1 }
1927 };
1928
1929 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1930         { .role = "pad_fck", .clk = "pad_clks_ck" },
1931         { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
1932 };
1933
1934 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1935         .name           = "mcbsp1",
1936         .class          = &omap44xx_mcbsp_hwmod_class,
1937         .clkdm_name     = "abe_clkdm",
1938         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1939         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1940         .main_clk       = "mcbsp1_fck",
1941         .prcm = {
1942                 .omap4 = {
1943                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1944                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1945                         .modulemode   = MODULEMODE_SWCTRL,
1946                 },
1947         },
1948         .opt_clks       = mcbsp1_opt_clks,
1949         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1950 };
1951
1952 /* mcbsp2 */
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1954         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1955         { .irq = -1 }
1956 };
1957
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1959         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1960         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1961         { .dma_req = -1 }
1962 };
1963
1964 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1965         { .role = "pad_fck", .clk = "pad_clks_ck" },
1966         { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
1967 };
1968
1969 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1970         .name           = "mcbsp2",
1971         .class          = &omap44xx_mcbsp_hwmod_class,
1972         .clkdm_name     = "abe_clkdm",
1973         .mpu_irqs       = omap44xx_mcbsp2_irqs,
1974         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
1975         .main_clk       = "mcbsp2_fck",
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1979                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983         .opt_clks       = mcbsp2_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1985 };
1986
1987 /* mcbsp3 */
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1989         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1990         { .irq = -1 }
1991 };
1992
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1994         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1995         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1996         { .dma_req = -1 }
1997 };
1998
1999 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2000         { .role = "pad_fck", .clk = "pad_clks_ck" },
2001         { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
2002 };
2003
2004 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2005         .name           = "mcbsp3",
2006         .class          = &omap44xx_mcbsp_hwmod_class,
2007         .clkdm_name     = "abe_clkdm",
2008         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2009         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2010         .main_clk       = "mcbsp3_fck",
2011         .prcm = {
2012                 .omap4 = {
2013                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2014                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2015                         .modulemode   = MODULEMODE_SWCTRL,
2016                 },
2017         },
2018         .opt_clks       = mcbsp3_opt_clks,
2019         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2020 };
2021
2022 /* mcbsp4 */
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2024         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2025         { .irq = -1 }
2026 };
2027
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2029         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2030         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2031         { .dma_req = -1 }
2032 };
2033
2034 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2035         { .role = "pad_fck", .clk = "pad_clks_ck" },
2036         { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
2037 };
2038
2039 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2040         .name           = "mcbsp4",
2041         .class          = &omap44xx_mcbsp_hwmod_class,
2042         .clkdm_name     = "l4_per_clkdm",
2043         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2044         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2045         .main_clk       = "mcbsp4_fck",
2046         .prcm = {
2047                 .omap4 = {
2048                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2049                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2050                         .modulemode   = MODULEMODE_SWCTRL,
2051                 },
2052         },
2053         .opt_clks       = mcbsp4_opt_clks,
2054         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2055 };
2056
2057 /*
2058  * 'mcpdm' class
2059  * multi channel pdm controller (proprietary interface with phoenix power
2060  * ic)
2061  */
2062
2063 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2064         .rev_offs       = 0x0000,
2065         .sysc_offs      = 0x0010,
2066         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2067                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2068         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2069                            SIDLE_SMART_WKUP),
2070         .sysc_fields    = &omap_hwmod_sysc_type2,
2071 };
2072
2073 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2074         .name   = "mcpdm",
2075         .sysc   = &omap44xx_mcpdm_sysc,
2076 };
2077
2078 /* mcpdm */
2079 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2080         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2081         { .irq = -1 }
2082 };
2083
2084 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2085         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2086         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2087         { .dma_req = -1 }
2088 };
2089
2090 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2091         .name           = "mcpdm",
2092         .class          = &omap44xx_mcpdm_hwmod_class,
2093         .clkdm_name     = "abe_clkdm",
2094         .mpu_irqs       = omap44xx_mcpdm_irqs,
2095         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2096         .main_clk       = "mcpdm_fck",
2097         .prcm = {
2098                 .omap4 = {
2099                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2100                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2101                         .modulemode   = MODULEMODE_SWCTRL,
2102                 },
2103         },
2104 };
2105
2106 /*
2107  * 'mcspi' class
2108  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2109  * bus
2110  */
2111
2112 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2113         .rev_offs       = 0x0000,
2114         .sysc_offs      = 0x0010,
2115         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2116                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2117         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2118                            SIDLE_SMART_WKUP),
2119         .sysc_fields    = &omap_hwmod_sysc_type2,
2120 };
2121
2122 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2123         .name   = "mcspi",
2124         .sysc   = &omap44xx_mcspi_sysc,
2125         .rev    = OMAP4_MCSPI_REV,
2126 };
2127
2128 /* mcspi1 */
2129 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2130         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2131         { .irq = -1 }
2132 };
2133
2134 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2135         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2136         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2137         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2138         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2139         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2140         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2141         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2142         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2143         { .dma_req = -1 }
2144 };
2145
2146 /* mcspi1 dev_attr */
2147 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2148         .num_chipselect = 4,
2149 };
2150
2151 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2152         .name           = "mcspi1",
2153         .class          = &omap44xx_mcspi_hwmod_class,
2154         .clkdm_name     = "l4_per_clkdm",
2155         .mpu_irqs       = omap44xx_mcspi1_irqs,
2156         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2157         .main_clk       = "mcspi1_fck",
2158         .prcm = {
2159                 .omap4 = {
2160                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2161                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2162                         .modulemode   = MODULEMODE_SWCTRL,
2163                 },
2164         },
2165         .dev_attr       = &mcspi1_dev_attr,
2166 };
2167
2168 /* mcspi2 */
2169 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2170         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2171         { .irq = -1 }
2172 };
2173
2174 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2175         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2176         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2177         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2178         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2179         { .dma_req = -1 }
2180 };
2181
2182 /* mcspi2 dev_attr */
2183 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2184         .num_chipselect = 2,
2185 };
2186
2187 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2188         .name           = "mcspi2",
2189         .class          = &omap44xx_mcspi_hwmod_class,
2190         .clkdm_name     = "l4_per_clkdm",
2191         .mpu_irqs       = omap44xx_mcspi2_irqs,
2192         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2193         .main_clk       = "mcspi2_fck",
2194         .prcm = {
2195                 .omap4 = {
2196                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2197                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2198                         .modulemode   = MODULEMODE_SWCTRL,
2199                 },
2200         },
2201         .dev_attr       = &mcspi2_dev_attr,
2202 };
2203
2204 /* mcspi3 */
2205 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2206         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2207         { .irq = -1 }
2208 };
2209
2210 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2211         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2212         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2213         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2214         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2215         { .dma_req = -1 }
2216 };
2217
2218 /* mcspi3 dev_attr */
2219 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2220         .num_chipselect = 2,
2221 };
2222
2223 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2224         .name           = "mcspi3",
2225         .class          = &omap44xx_mcspi_hwmod_class,
2226         .clkdm_name     = "l4_per_clkdm",
2227         .mpu_irqs       = omap44xx_mcspi3_irqs,
2228         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2229         .main_clk       = "mcspi3_fck",
2230         .prcm = {
2231                 .omap4 = {
2232                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2233                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2234                         .modulemode   = MODULEMODE_SWCTRL,
2235                 },
2236         },
2237         .dev_attr       = &mcspi3_dev_attr,
2238 };
2239
2240 /* mcspi4 */
2241 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2242         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2243         { .irq = -1 }
2244 };
2245
2246 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2247         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2248         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2249         { .dma_req = -1 }
2250 };
2251
2252 /* mcspi4 dev_attr */
2253 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2254         .num_chipselect = 1,
2255 };
2256
2257 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2258         .name           = "mcspi4",
2259         .class          = &omap44xx_mcspi_hwmod_class,
2260         .clkdm_name     = "l4_per_clkdm",
2261         .mpu_irqs       = omap44xx_mcspi4_irqs,
2262         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2263         .main_clk       = "mcspi4_fck",
2264         .prcm = {
2265                 .omap4 = {
2266                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2267                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2268                         .modulemode   = MODULEMODE_SWCTRL,
2269                 },
2270         },
2271         .dev_attr       = &mcspi4_dev_attr,
2272 };
2273
2274 /*
2275  * 'mmc' class
2276  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2277  */
2278
2279 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2280         .rev_offs       = 0x0000,
2281         .sysc_offs      = 0x0010,
2282         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2283                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2284                            SYSC_HAS_SOFTRESET),
2285         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2286                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2287                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2288         .sysc_fields    = &omap_hwmod_sysc_type2,
2289 };
2290
2291 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2292         .name   = "mmc",
2293         .sysc   = &omap44xx_mmc_sysc,
2294 };
2295
2296 /* mmc1 */
2297 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2298         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2299         { .irq = -1 }
2300 };
2301
2302 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2303         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2304         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2305         { .dma_req = -1 }
2306 };
2307
2308 /* mmc1 dev_attr */
2309 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2310         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2311 };
2312
2313 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2314         .name           = "mmc1",
2315         .class          = &omap44xx_mmc_hwmod_class,
2316         .clkdm_name     = "l3_init_clkdm",
2317         .mpu_irqs       = omap44xx_mmc1_irqs,
2318         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2319         .main_clk       = "mmc1_fck",
2320         .prcm = {
2321                 .omap4 = {
2322                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2323                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2324                         .modulemode   = MODULEMODE_SWCTRL,
2325                 },
2326         },
2327         .dev_attr       = &mmc1_dev_attr,
2328 };
2329
2330 /* mmc2 */
2331 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2332         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2333         { .irq = -1 }
2334 };
2335
2336 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2337         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2338         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2339         { .dma_req = -1 }
2340 };
2341
2342 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2343         .name           = "mmc2",
2344         .class          = &omap44xx_mmc_hwmod_class,
2345         .clkdm_name     = "l3_init_clkdm",
2346         .mpu_irqs       = omap44xx_mmc2_irqs,
2347         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2348         .main_clk       = "mmc2_fck",
2349         .prcm = {
2350                 .omap4 = {
2351                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2352                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2353                         .modulemode   = MODULEMODE_SWCTRL,
2354                 },
2355         },
2356 };
2357
2358 /* mmc3 */
2359 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2360         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2361         { .irq = -1 }
2362 };
2363
2364 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2365         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2366         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2367         { .dma_req = -1 }
2368 };
2369
2370 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2371         .name           = "mmc3",
2372         .class          = &omap44xx_mmc_hwmod_class,
2373         .clkdm_name     = "l4_per_clkdm",
2374         .mpu_irqs       = omap44xx_mmc3_irqs,
2375         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2376         .main_clk       = "mmc3_fck",
2377         .prcm = {
2378                 .omap4 = {
2379                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2380                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2381                         .modulemode   = MODULEMODE_SWCTRL,
2382                 },
2383         },
2384 };
2385
2386 /* mmc4 */
2387 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2388         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2389         { .irq = -1 }
2390 };
2391
2392 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2393         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2394         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2395         { .dma_req = -1 }
2396 };
2397
2398 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2399         .name           = "mmc4",
2400         .class          = &omap44xx_mmc_hwmod_class,
2401         .clkdm_name     = "l4_per_clkdm",
2402         .mpu_irqs       = omap44xx_mmc4_irqs,
2403         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2404         .main_clk       = "mmc4_fck",
2405         .prcm = {
2406                 .omap4 = {
2407                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2408                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2409                         .modulemode   = MODULEMODE_SWCTRL,
2410                 },
2411         },
2412 };
2413
2414 /* mmc5 */
2415 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2416         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2417         { .irq = -1 }
2418 };
2419
2420 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2421         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2422         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2423         { .dma_req = -1 }
2424 };
2425
2426 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2427         .name           = "mmc5",
2428         .class          = &omap44xx_mmc_hwmod_class,
2429         .clkdm_name     = "l4_per_clkdm",
2430         .mpu_irqs       = omap44xx_mmc5_irqs,
2431         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2432         .main_clk       = "mmc5_fck",
2433         .prcm = {
2434                 .omap4 = {
2435                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2436                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2437                         .modulemode   = MODULEMODE_SWCTRL,
2438                 },
2439         },
2440 };
2441
2442 /*
2443  * 'mpu' class
2444  * mpu sub-system
2445  */
2446
2447 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2448         .name   = "mpu",
2449 };
2450
2451 /* mpu */
2452 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2453         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2454         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2455         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2456         { .irq = -1 }
2457 };
2458
2459 static struct omap_hwmod omap44xx_mpu_hwmod = {
2460         .name           = "mpu",
2461         .class          = &omap44xx_mpu_hwmod_class,
2462         .clkdm_name     = "mpuss_clkdm",
2463         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2464         .mpu_irqs       = omap44xx_mpu_irqs,
2465         .main_clk       = "dpll_mpu_m2_ck",
2466         .prcm = {
2467                 .omap4 = {
2468                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2469                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2470                 },
2471         },
2472 };
2473
2474 /*
2475  * 'ocmc_ram' class
2476  * top-level core on-chip ram
2477  */
2478
2479 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2480         .name   = "ocmc_ram",
2481 };
2482
2483 /* ocmc_ram */
2484 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2485         .name           = "ocmc_ram",
2486         .class          = &omap44xx_ocmc_ram_hwmod_class,
2487         .clkdm_name     = "l3_2_clkdm",
2488         .prcm = {
2489                 .omap4 = {
2490                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2491                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2492                 },
2493         },
2494 };
2495
2496 /*
2497  * 'ocp2scp' class
2498  * bridge to transform ocp interface protocol to scp (serial control port)
2499  * protocol
2500  */
2501
2502 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2503         .name   = "ocp2scp",
2504 };
2505
2506 /* ocp2scp_usb_phy */
2507 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2508         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2509 };
2510
2511 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2512         .name           = "ocp2scp_usb_phy",
2513         .class          = &omap44xx_ocp2scp_hwmod_class,
2514         .clkdm_name     = "l3_init_clkdm",
2515         .prcm = {
2516                 .omap4 = {
2517                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2518                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2519                         .modulemode   = MODULEMODE_HWCTRL,
2520                 },
2521         },
2522         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2523         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2524 };
2525
2526 /*
2527  * 'prcm' class
2528  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2529  * + clock manager 1 (in always on power domain) + local prm in mpu
2530  */
2531
2532 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2533         .name   = "prcm",
2534 };
2535
2536 /* prcm_mpu */
2537 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2538         .name           = "prcm_mpu",
2539         .class          = &omap44xx_prcm_hwmod_class,
2540         .clkdm_name     = "l4_wkup_clkdm",
2541 };
2542
2543 /* cm_core_aon */
2544 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2545         .name           = "cm_core_aon",
2546         .class          = &omap44xx_prcm_hwmod_class,
2547 };
2548
2549 /* cm_core */
2550 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2551         .name           = "cm_core",
2552         .class          = &omap44xx_prcm_hwmod_class,
2553 };
2554
2555 /* prm */
2556 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2557         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2558         { .irq = -1 }
2559 };
2560
2561 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2562         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2563         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2564 };
2565
2566 static struct omap_hwmod omap44xx_prm_hwmod = {
2567         .name           = "prm",
2568         .class          = &omap44xx_prcm_hwmod_class,
2569         .mpu_irqs       = omap44xx_prm_irqs,
2570         .rst_lines      = omap44xx_prm_resets,
2571         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2572 };
2573
2574 /*
2575  * 'scrm' class
2576  * system clock and reset manager
2577  */
2578
2579 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2580         .name   = "scrm",
2581 };
2582
2583 /* scrm */
2584 static struct omap_hwmod omap44xx_scrm_hwmod = {
2585         .name           = "scrm",
2586         .class          = &omap44xx_scrm_hwmod_class,
2587         .clkdm_name     = "l4_wkup_clkdm",
2588 };
2589
2590 /*
2591  * 'sl2if' class
2592  * shared level 2 memory interface
2593  */
2594
2595 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2596         .name   = "sl2if",
2597 };
2598
2599 /* sl2if */
2600 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2601         .name           = "sl2if",
2602         .class          = &omap44xx_sl2if_hwmod_class,
2603         .clkdm_name     = "ivahd_clkdm",
2604         .prcm = {
2605                 .omap4 = {
2606                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2607                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2608                         .modulemode   = MODULEMODE_HWCTRL,
2609                 },
2610         },
2611 };
2612
2613 /*
2614  * 'slimbus' class
2615  * bidirectional, multi-drop, multi-channel two-line serial interface between
2616  * the device and external components
2617  */
2618
2619 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2620         .rev_offs       = 0x0000,
2621         .sysc_offs      = 0x0010,
2622         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2623                            SYSC_HAS_SOFTRESET),
2624         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2625                            SIDLE_SMART_WKUP),
2626         .sysc_fields    = &omap_hwmod_sysc_type2,
2627 };
2628
2629 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2630         .name   = "slimbus",
2631         .sysc   = &omap44xx_slimbus_sysc,
2632 };
2633
2634 /* slimbus1 */
2635 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2636         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2637         { .irq = -1 }
2638 };
2639
2640 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2641         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2642         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2643         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2644         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2645         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2646         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2647         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2648         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2649         { .dma_req = -1 }
2650 };
2651
2652 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2653         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2654         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2655         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2656         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2657 };
2658
2659 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2660         .name           = "slimbus1",
2661         .class          = &omap44xx_slimbus_hwmod_class,
2662         .clkdm_name     = "abe_clkdm",
2663         .mpu_irqs       = omap44xx_slimbus1_irqs,
2664         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2665         .prcm = {
2666                 .omap4 = {
2667                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2668                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2669                         .modulemode   = MODULEMODE_SWCTRL,
2670                 },
2671         },
2672         .opt_clks       = slimbus1_opt_clks,
2673         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2674 };
2675
2676 /* slimbus2 */
2677 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2678         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2679         { .irq = -1 }
2680 };
2681
2682 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2683         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2684         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2685         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2686         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2687         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2688         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2689         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2690         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2691         { .dma_req = -1 }
2692 };
2693
2694 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2695         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2696         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2697         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2698 };
2699
2700 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2701         .name           = "slimbus2",
2702         .class          = &omap44xx_slimbus_hwmod_class,
2703         .clkdm_name     = "l4_per_clkdm",
2704         .mpu_irqs       = omap44xx_slimbus2_irqs,
2705         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2706         .prcm = {
2707                 .omap4 = {
2708                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2709                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2710                         .modulemode   = MODULEMODE_SWCTRL,
2711                 },
2712         },
2713         .opt_clks       = slimbus2_opt_clks,
2714         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2715 };
2716
2717 /*
2718  * 'smartreflex' class
2719  * smartreflex module (monitor silicon performance and outputs a measure of
2720  * performance error)
2721  */
2722
2723 /* The IP is not compliant to type1 / type2 scheme */
2724 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2725         .sidle_shift    = 24,
2726         .enwkup_shift   = 26,
2727 };
2728
2729 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2730         .sysc_offs      = 0x0038,
2731         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2732         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2733                            SIDLE_SMART_WKUP),
2734         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2735 };
2736
2737 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2738         .name   = "smartreflex",
2739         .sysc   = &omap44xx_smartreflex_sysc,
2740         .rev    = 2,
2741 };
2742
2743 /* smartreflex_core */
2744 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2745         .sensor_voltdm_name   = "core",
2746 };
2747
2748 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2749         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2750         { .irq = -1 }
2751 };
2752
2753 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2754         .name           = "smartreflex_core",
2755         .class          = &omap44xx_smartreflex_hwmod_class,
2756         .clkdm_name     = "l4_ao_clkdm",
2757         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2758
2759         .main_clk       = "smartreflex_core_fck",
2760         .prcm = {
2761                 .omap4 = {
2762                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2763                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2764                         .modulemode   = MODULEMODE_SWCTRL,
2765                 },
2766         },
2767         .dev_attr       = &smartreflex_core_dev_attr,
2768 };
2769
2770 /* smartreflex_iva */
2771 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2772         .sensor_voltdm_name     = "iva",
2773 };
2774
2775 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2776         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2777         { .irq = -1 }
2778 };
2779
2780 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2781         .name           = "smartreflex_iva",
2782         .class          = &omap44xx_smartreflex_hwmod_class,
2783         .clkdm_name     = "l4_ao_clkdm",
2784         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2785         .main_clk       = "smartreflex_iva_fck",
2786         .prcm = {
2787                 .omap4 = {
2788                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2789                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2790                         .modulemode   = MODULEMODE_SWCTRL,
2791                 },
2792         },
2793         .dev_attr       = &smartreflex_iva_dev_attr,
2794 };
2795
2796 /* smartreflex_mpu */
2797 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2798         .sensor_voltdm_name     = "mpu",
2799 };
2800
2801 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2802         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2803         { .irq = -1 }
2804 };
2805
2806 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2807         .name           = "smartreflex_mpu",
2808         .class          = &omap44xx_smartreflex_hwmod_class,
2809         .clkdm_name     = "l4_ao_clkdm",
2810         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2811         .main_clk       = "smartreflex_mpu_fck",
2812         .prcm = {
2813                 .omap4 = {
2814                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2815                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2816                         .modulemode   = MODULEMODE_SWCTRL,
2817                 },
2818         },
2819         .dev_attr       = &smartreflex_mpu_dev_attr,
2820 };
2821
2822 /*
2823  * 'spinlock' class
2824  * spinlock provides hardware assistance for synchronizing the processes
2825  * running on multiple processors
2826  */
2827
2828 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2829         .rev_offs       = 0x0000,
2830         .sysc_offs      = 0x0010,
2831         .syss_offs      = 0x0014,
2832         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2833                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2834                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2835         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2836                            SIDLE_SMART_WKUP),
2837         .sysc_fields    = &omap_hwmod_sysc_type1,
2838 };
2839
2840 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2841         .name   = "spinlock",
2842         .sysc   = &omap44xx_spinlock_sysc,
2843 };
2844
2845 /* spinlock */
2846 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2847         .name           = "spinlock",
2848         .class          = &omap44xx_spinlock_hwmod_class,
2849         .clkdm_name     = "l4_cfg_clkdm",
2850         .prcm = {
2851                 .omap4 = {
2852                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2853                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2854                 },
2855         },
2856 };
2857
2858 /*
2859  * 'timer' class
2860  * general purpose timer module with accurate 1ms tick
2861  * This class contains several variants: ['timer_1ms', 'timer']
2862  */
2863
2864 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2865         .rev_offs       = 0x0000,
2866         .sysc_offs      = 0x0010,
2867         .syss_offs      = 0x0014,
2868         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2869                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2870                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2871                            SYSS_HAS_RESET_STATUS),
2872         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2873         .sysc_fields    = &omap_hwmod_sysc_type1,
2874 };
2875
2876 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2877         .name   = "timer",
2878         .sysc   = &omap44xx_timer_1ms_sysc,
2879 };
2880
2881 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2882         .rev_offs       = 0x0000,
2883         .sysc_offs      = 0x0010,
2884         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2885                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2886         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2887                            SIDLE_SMART_WKUP),
2888         .sysc_fields    = &omap_hwmod_sysc_type2,
2889 };
2890
2891 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2892         .name   = "timer",
2893         .sysc   = &omap44xx_timer_sysc,
2894 };
2895
2896 /* always-on timers dev attribute */
2897 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2898         .timer_capability       = OMAP_TIMER_ALWON,
2899 };
2900
2901 /* pwm timers dev attribute */
2902 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2903         .timer_capability       = OMAP_TIMER_HAS_PWM,
2904 };
2905
2906 /* timer1 */
2907 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2908         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2909         { .irq = -1 }
2910 };
2911
2912 static struct omap_hwmod omap44xx_timer1_hwmod = {
2913         .name           = "timer1",
2914         .class          = &omap44xx_timer_1ms_hwmod_class,
2915         .clkdm_name     = "l4_wkup_clkdm",
2916         .mpu_irqs       = omap44xx_timer1_irqs,
2917         .main_clk       = "timer1_fck",
2918         .prcm = {
2919                 .omap4 = {
2920                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2921                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2922                         .modulemode   = MODULEMODE_SWCTRL,
2923                 },
2924         },
2925         .dev_attr       = &capability_alwon_dev_attr,
2926 };
2927
2928 /* timer2 */
2929 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2930         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2931         { .irq = -1 }
2932 };
2933
2934 static struct omap_hwmod omap44xx_timer2_hwmod = {
2935         .name           = "timer2",
2936         .class          = &omap44xx_timer_1ms_hwmod_class,
2937         .clkdm_name     = "l4_per_clkdm",
2938         .mpu_irqs       = omap44xx_timer2_irqs,
2939         .main_clk       = "timer2_fck",
2940         .prcm = {
2941                 .omap4 = {
2942                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2943                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2944                         .modulemode   = MODULEMODE_SWCTRL,
2945                 },
2946         },
2947 };
2948
2949 /* timer3 */
2950 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2951         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2952         { .irq = -1 }
2953 };
2954
2955 static struct omap_hwmod omap44xx_timer3_hwmod = {
2956         .name           = "timer3",
2957         .class          = &omap44xx_timer_hwmod_class,
2958         .clkdm_name     = "l4_per_clkdm",
2959         .mpu_irqs       = omap44xx_timer3_irqs,
2960         .main_clk       = "timer3_fck",
2961         .prcm = {
2962                 .omap4 = {
2963                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2964                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2965                         .modulemode   = MODULEMODE_SWCTRL,
2966                 },
2967         },
2968 };
2969
2970 /* timer4 */
2971 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2972         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2973         { .irq = -1 }
2974 };
2975
2976 static struct omap_hwmod omap44xx_timer4_hwmod = {
2977         .name           = "timer4",
2978         .class          = &omap44xx_timer_hwmod_class,
2979         .clkdm_name     = "l4_per_clkdm",
2980         .mpu_irqs       = omap44xx_timer4_irqs,
2981         .main_clk       = "timer4_fck",
2982         .prcm = {
2983                 .omap4 = {
2984                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2985                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2986                         .modulemode   = MODULEMODE_SWCTRL,
2987                 },
2988         },
2989 };
2990
2991 /* timer5 */
2992 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2993         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2994         { .irq = -1 }
2995 };
2996
2997 static struct omap_hwmod omap44xx_timer5_hwmod = {
2998         .name           = "timer5",
2999         .class          = &omap44xx_timer_hwmod_class,
3000         .clkdm_name     = "abe_clkdm",
3001         .mpu_irqs       = omap44xx_timer5_irqs,
3002         .main_clk       = "timer5_fck",
3003         .prcm = {
3004                 .omap4 = {
3005                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3006                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3007                         .modulemode   = MODULEMODE_SWCTRL,
3008                 },
3009         },
3010 };
3011
3012 /* timer6 */
3013 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3014         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3015         { .irq = -1 }
3016 };
3017
3018 static struct omap_hwmod omap44xx_timer6_hwmod = {
3019         .name           = "timer6",
3020         .class          = &omap44xx_timer_hwmod_class,
3021         .clkdm_name     = "abe_clkdm",
3022         .mpu_irqs       = omap44xx_timer6_irqs,
3023
3024         .main_clk       = "timer6_fck",
3025         .prcm = {
3026                 .omap4 = {
3027                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3028                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3029                         .modulemode   = MODULEMODE_SWCTRL,
3030                 },
3031         },
3032 };
3033
3034 /* timer7 */
3035 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3036         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3037         { .irq = -1 }
3038 };
3039
3040 static struct omap_hwmod omap44xx_timer7_hwmod = {
3041         .name           = "timer7",
3042         .class          = &omap44xx_timer_hwmod_class,
3043         .clkdm_name     = "abe_clkdm",
3044         .mpu_irqs       = omap44xx_timer7_irqs,
3045         .main_clk       = "timer7_fck",
3046         .prcm = {
3047                 .omap4 = {
3048                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3049                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3050                         .modulemode   = MODULEMODE_SWCTRL,
3051                 },
3052         },
3053 };
3054
3055 /* timer8 */
3056 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3057         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3058         { .irq = -1 }
3059 };
3060
3061 static struct omap_hwmod omap44xx_timer8_hwmod = {
3062         .name           = "timer8",
3063         .class          = &omap44xx_timer_hwmod_class,
3064         .clkdm_name     = "abe_clkdm",
3065         .mpu_irqs       = omap44xx_timer8_irqs,
3066         .main_clk       = "timer8_fck",
3067         .prcm = {
3068                 .omap4 = {
3069                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3070                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3071                         .modulemode   = MODULEMODE_SWCTRL,
3072                 },
3073         },
3074         .dev_attr       = &capability_pwm_dev_attr,
3075 };
3076
3077 /* timer9 */
3078 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3079         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3080         { .irq = -1 }
3081 };
3082
3083 static struct omap_hwmod omap44xx_timer9_hwmod = {
3084         .name           = "timer9",
3085         .class          = &omap44xx_timer_hwmod_class,
3086         .clkdm_name     = "l4_per_clkdm",
3087         .mpu_irqs       = omap44xx_timer9_irqs,
3088         .main_clk       = "timer9_fck",
3089         .prcm = {
3090                 .omap4 = {
3091                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3092                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3093                         .modulemode   = MODULEMODE_SWCTRL,
3094                 },
3095         },
3096         .dev_attr       = &capability_pwm_dev_attr,
3097 };
3098
3099 /* timer10 */
3100 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3101         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3102         { .irq = -1 }
3103 };
3104
3105 static struct omap_hwmod omap44xx_timer10_hwmod = {
3106         .name           = "timer10",
3107         .class          = &omap44xx_timer_1ms_hwmod_class,
3108         .clkdm_name     = "l4_per_clkdm",
3109         .mpu_irqs       = omap44xx_timer10_irqs,
3110         .main_clk       = "timer10_fck",
3111         .prcm = {
3112                 .omap4 = {
3113                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3114                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3115                         .modulemode   = MODULEMODE_SWCTRL,
3116                 },
3117         },
3118         .dev_attr       = &capability_pwm_dev_attr,
3119 };
3120
3121 /* timer11 */
3122 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3123         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3124         { .irq = -1 }
3125 };
3126
3127 static struct omap_hwmod omap44xx_timer11_hwmod = {
3128         .name           = "timer11",
3129         .class          = &omap44xx_timer_hwmod_class,
3130         .clkdm_name     = "l4_per_clkdm",
3131         .mpu_irqs       = omap44xx_timer11_irqs,
3132         .main_clk       = "timer11_fck",
3133         .prcm = {
3134                 .omap4 = {
3135                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3136                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3137                         .modulemode   = MODULEMODE_SWCTRL,
3138                 },
3139         },
3140         .dev_attr       = &capability_pwm_dev_attr,
3141 };
3142
3143 /*
3144  * 'uart' class
3145  * universal asynchronous receiver/transmitter (uart)
3146  */
3147
3148 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3149         .rev_offs       = 0x0050,
3150         .sysc_offs      = 0x0054,
3151         .syss_offs      = 0x0058,
3152         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3153                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3154                            SYSS_HAS_RESET_STATUS),
3155         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3156                            SIDLE_SMART_WKUP),
3157         .sysc_fields    = &omap_hwmod_sysc_type1,
3158 };
3159
3160 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3161         .name   = "uart",
3162         .sysc   = &omap44xx_uart_sysc,
3163 };
3164
3165 /* uart1 */
3166 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3167         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3168         { .irq = -1 }
3169 };
3170
3171 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3172         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3173         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3174         { .dma_req = -1 }
3175 };
3176
3177 static struct omap_hwmod omap44xx_uart1_hwmod = {
3178         .name           = "uart1",
3179         .class          = &omap44xx_uart_hwmod_class,
3180         .clkdm_name     = "l4_per_clkdm",
3181         .mpu_irqs       = omap44xx_uart1_irqs,
3182         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3183         .main_clk       = "uart1_fck",
3184         .prcm = {
3185                 .omap4 = {
3186                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3187                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3188                         .modulemode   = MODULEMODE_SWCTRL,
3189                 },
3190         },
3191 };
3192
3193 /* uart2 */
3194 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3195         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3196         { .irq = -1 }
3197 };
3198
3199 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3200         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3201         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3202         { .dma_req = -1 }
3203 };
3204
3205 static struct omap_hwmod omap44xx_uart2_hwmod = {
3206         .name           = "uart2",
3207         .class          = &omap44xx_uart_hwmod_class,
3208         .clkdm_name     = "l4_per_clkdm",
3209         .mpu_irqs       = omap44xx_uart2_irqs,
3210         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3211         .main_clk       = "uart2_fck",
3212         .prcm = {
3213                 .omap4 = {
3214                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3215                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3216                         .modulemode   = MODULEMODE_SWCTRL,
3217                 },
3218         },
3219 };
3220
3221 /* uart3 */
3222 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3223         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3224         { .irq = -1 }
3225 };
3226
3227 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3228         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3229         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3230         { .dma_req = -1 }
3231 };
3232
3233 static struct omap_hwmod omap44xx_uart3_hwmod = {
3234         .name           = "uart3",
3235         .class          = &omap44xx_uart_hwmod_class,
3236         .clkdm_name     = "l4_per_clkdm",
3237         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3238         .mpu_irqs       = omap44xx_uart3_irqs,
3239         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3240         .main_clk       = "uart3_fck",
3241         .prcm = {
3242                 .omap4 = {
3243                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3244                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3245                         .modulemode   = MODULEMODE_SWCTRL,
3246                 },
3247         },
3248 };
3249
3250 /* uart4 */
3251 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3252         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3253         { .irq = -1 }
3254 };
3255
3256 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3257         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3258         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3259         { .dma_req = -1 }
3260 };
3261
3262 static struct omap_hwmod omap44xx_uart4_hwmod = {
3263         .name           = "uart4",
3264         .class          = &omap44xx_uart_hwmod_class,
3265         .clkdm_name     = "l4_per_clkdm",
3266         .mpu_irqs       = omap44xx_uart4_irqs,
3267         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3268         .main_clk       = "uart4_fck",
3269         .prcm = {
3270                 .omap4 = {
3271                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3272                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3273                         .modulemode   = MODULEMODE_SWCTRL,
3274                 },
3275         },
3276 };
3277
3278 /*
3279  * 'usb_host_fs' class
3280  * full-speed usb host controller
3281  */
3282
3283 /* The IP is not compliant to type1 / type2 scheme */
3284 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3285         .midle_shift    = 4,
3286         .sidle_shift    = 2,
3287         .srst_shift     = 1,
3288 };
3289
3290 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3291         .rev_offs       = 0x0000,
3292         .sysc_offs      = 0x0210,
3293         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3294                            SYSC_HAS_SOFTRESET),
3295         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3296                            SIDLE_SMART_WKUP),
3297         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3298 };
3299
3300 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3301         .name   = "usb_host_fs",
3302         .sysc   = &omap44xx_usb_host_fs_sysc,
3303 };
3304
3305 /* usb_host_fs */
3306 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3307         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3308         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3309         { .irq = -1 }
3310 };
3311
3312 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3313         .name           = "usb_host_fs",
3314         .class          = &omap44xx_usb_host_fs_hwmod_class,
3315         .clkdm_name     = "l3_init_clkdm",
3316         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3317         .main_clk       = "usb_host_fs_fck",
3318         .prcm = {
3319                 .omap4 = {
3320                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3321                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3322                         .modulemode   = MODULEMODE_SWCTRL,
3323                 },
3324         },
3325 };
3326
3327 /*
3328  * 'usb_host_hs' class
3329  * high-speed multi-port usb host controller
3330  */
3331
3332 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3333         .rev_offs       = 0x0000,
3334         .sysc_offs      = 0x0010,
3335         .syss_offs      = 0x0014,
3336         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3337                            SYSC_HAS_SOFTRESET),
3338         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3339                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3340                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3341         .sysc_fields    = &omap_hwmod_sysc_type2,
3342 };
3343
3344 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3345         .name   = "usb_host_hs",
3346         .sysc   = &omap44xx_usb_host_hs_sysc,
3347 };
3348
3349 /* usb_host_hs */
3350 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3351         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3352         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3353         { .irq = -1 }
3354 };
3355
3356 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3357         .name           = "usb_host_hs",
3358         .class          = &omap44xx_usb_host_hs_hwmod_class,
3359         .clkdm_name     = "l3_init_clkdm",
3360         .main_clk       = "usb_host_hs_fck",
3361         .prcm = {
3362                 .omap4 = {
3363                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3364                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3365                         .modulemode   = MODULEMODE_SWCTRL,
3366                 },
3367         },
3368         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3369
3370         /*
3371          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3372          * id: i660
3373          *
3374          * Description:
3375          * In the following configuration :
3376          * - USBHOST module is set to smart-idle mode
3377          * - PRCM asserts idle_req to the USBHOST module ( This typically
3378          *   happens when the system is going to a low power mode : all ports
3379          *   have been suspended, the master part of the USBHOST module has
3380          *   entered the standby state, and SW has cut the functional clocks)
3381          * - an USBHOST interrupt occurs before the module is able to answer
3382          *   idle_ack, typically a remote wakeup IRQ.
3383          * Then the USB HOST module will enter a deadlock situation where it
3384          * is no more accessible nor functional.
3385          *
3386          * Workaround:
3387          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3388          */
3389
3390         /*
3391          * Errata: USB host EHCI may stall when entering smart-standby mode
3392          * Id: i571
3393          *
3394          * Description:
3395          * When the USBHOST module is set to smart-standby mode, and when it is
3396          * ready to enter the standby state (i.e. all ports are suspended and
3397          * all attached devices are in suspend mode), then it can wrongly assert
3398          * the Mstandby signal too early while there are still some residual OCP
3399          * transactions ongoing. If this condition occurs, the internal state
3400          * machine may go to an undefined state and the USB link may be stuck
3401          * upon the next resume.
3402          *
3403          * Workaround:
3404          * Don't use smart standby; use only force standby,
3405          * hence HWMOD_SWSUP_MSTANDBY
3406          */
3407
3408         /*
3409          * During system boot; If the hwmod framework resets the module
3410          * the module will have smart idle settings; which can lead to deadlock
3411          * (above Errata Id:i660); so, dont reset the module during boot;
3412          * Use HWMOD_INIT_NO_RESET.
3413          */
3414
3415         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3416                           HWMOD_INIT_NO_RESET,
3417 };
3418
3419 /*
3420  * 'usb_otg_hs' class
3421  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3422  */
3423
3424 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3425         .rev_offs       = 0x0400,
3426         .sysc_offs      = 0x0404,
3427         .syss_offs      = 0x0408,
3428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3429                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3430                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3432                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3433                            MSTANDBY_SMART),
3434         .sysc_fields    = &omap_hwmod_sysc_type1,
3435 };
3436
3437 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3438         .name   = "usb_otg_hs",
3439         .sysc   = &omap44xx_usb_otg_hs_sysc,
3440 };
3441
3442 /* usb_otg_hs */
3443 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3444         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3445         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3446         { .irq = -1 }
3447 };
3448
3449 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3450         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3451 };
3452
3453 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3454         .name           = "usb_otg_hs",
3455         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3456         .clkdm_name     = "l3_init_clkdm",
3457         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3458         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3459         .main_clk       = "usb_otg_hs_ick",
3460         .prcm = {
3461                 .omap4 = {
3462                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3463                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3464                         .modulemode   = MODULEMODE_HWCTRL,
3465                 },
3466         },
3467         .opt_clks       = usb_otg_hs_opt_clks,
3468         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3469 };
3470
3471 /*
3472  * 'usb_tll_hs' class
3473  * usb_tll_hs module is the adapter on the usb_host_hs ports
3474  */
3475
3476 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3477         .rev_offs       = 0x0000,
3478         .sysc_offs      = 0x0010,
3479         .syss_offs      = 0x0014,
3480         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3481                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3482                            SYSC_HAS_AUTOIDLE),
3483         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3484         .sysc_fields    = &omap_hwmod_sysc_type1,
3485 };
3486
3487 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3488         .name   = "usb_tll_hs",
3489         .sysc   = &omap44xx_usb_tll_hs_sysc,
3490 };
3491
3492 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3493         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3494         { .irq = -1 }
3495 };
3496
3497 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3498         .name           = "usb_tll_hs",
3499         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3500         .clkdm_name     = "l3_init_clkdm",
3501         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3502         .main_clk       = "usb_tll_hs_ick",
3503         .prcm = {
3504                 .omap4 = {
3505                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3506                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3507                         .modulemode   = MODULEMODE_HWCTRL,
3508                 },
3509         },
3510 };
3511
3512 /*
3513  * 'wd_timer' class
3514  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3515  * overflow condition
3516  */
3517
3518 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3519         .rev_offs       = 0x0000,
3520         .sysc_offs      = 0x0010,
3521         .syss_offs      = 0x0014,
3522         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3523                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3524         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3525                            SIDLE_SMART_WKUP),
3526         .sysc_fields    = &omap_hwmod_sysc_type1,
3527 };
3528
3529 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3530         .name           = "wd_timer",
3531         .sysc           = &omap44xx_wd_timer_sysc,
3532         .pre_shutdown   = &omap2_wd_timer_disable,
3533         .reset          = &omap2_wd_timer_reset,
3534 };
3535
3536 /* wd_timer2 */
3537 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3538         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3539         { .irq = -1 }
3540 };
3541
3542 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3543         .name           = "wd_timer2",
3544         .class          = &omap44xx_wd_timer_hwmod_class,
3545         .clkdm_name     = "l4_wkup_clkdm",
3546         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3547         .main_clk       = "wd_timer2_fck",
3548         .prcm = {
3549                 .omap4 = {
3550                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3551                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3552                         .modulemode   = MODULEMODE_SWCTRL,
3553                 },
3554         },
3555 };
3556
3557 /* wd_timer3 */
3558 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3559         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3560         { .irq = -1 }
3561 };
3562
3563 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3564         .name           = "wd_timer3",
3565         .class          = &omap44xx_wd_timer_hwmod_class,
3566         .clkdm_name     = "abe_clkdm",
3567         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3568         .main_clk       = "wd_timer3_fck",
3569         .prcm = {
3570                 .omap4 = {
3571                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3572                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3573                         .modulemode   = MODULEMODE_SWCTRL,
3574                 },
3575         },
3576 };
3577
3578
3579 /*
3580  * interfaces
3581  */
3582
3583 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3584         {
3585                 .pa_start       = 0x4a204000,
3586                 .pa_end         = 0x4a2040ff,
3587                 .flags          = ADDR_TYPE_RT
3588         },
3589         { }
3590 };
3591
3592 /* c2c -> c2c_target_fw */
3593 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3594         .master         = &omap44xx_c2c_hwmod,
3595         .slave          = &omap44xx_c2c_target_fw_hwmod,
3596         .clk            = "div_core_ck",
3597         .addr           = omap44xx_c2c_target_fw_addrs,
3598         .user           = OCP_USER_MPU,
3599 };
3600
3601 /* l4_cfg -> c2c_target_fw */
3602 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3603         .master         = &omap44xx_l4_cfg_hwmod,
3604         .slave          = &omap44xx_c2c_target_fw_hwmod,
3605         .clk            = "l4_div_ck",
3606         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3607 };
3608
3609 /* l3_main_1 -> dmm */
3610 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3611         .master         = &omap44xx_l3_main_1_hwmod,
3612         .slave          = &omap44xx_dmm_hwmod,
3613         .clk            = "l3_div_ck",
3614         .user           = OCP_USER_SDMA,
3615 };
3616
3617 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3618         {
3619                 .pa_start       = 0x4e000000,
3620                 .pa_end         = 0x4e0007ff,
3621                 .flags          = ADDR_TYPE_RT
3622         },
3623         { }
3624 };
3625
3626 /* mpu -> dmm */
3627 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3628         .master         = &omap44xx_mpu_hwmod,
3629         .slave          = &omap44xx_dmm_hwmod,
3630         .clk            = "l3_div_ck",
3631         .addr           = omap44xx_dmm_addrs,
3632         .user           = OCP_USER_MPU,
3633 };
3634
3635 /* c2c -> emif_fw */
3636 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3637         .master         = &omap44xx_c2c_hwmod,
3638         .slave          = &omap44xx_emif_fw_hwmod,
3639         .clk            = "div_core_ck",
3640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3641 };
3642
3643 /* dmm -> emif_fw */
3644 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3645         .master         = &omap44xx_dmm_hwmod,
3646         .slave          = &omap44xx_emif_fw_hwmod,
3647         .clk            = "l3_div_ck",
3648         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3649 };
3650
3651 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3652         {
3653                 .pa_start       = 0x4a20c000,
3654                 .pa_end         = 0x4a20c0ff,
3655                 .flags          = ADDR_TYPE_RT
3656         },
3657         { }
3658 };
3659
3660 /* l4_cfg -> emif_fw */
3661 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3662         .master         = &omap44xx_l4_cfg_hwmod,
3663         .slave          = &omap44xx_emif_fw_hwmod,
3664         .clk            = "l4_div_ck",
3665         .addr           = omap44xx_emif_fw_addrs,
3666         .user           = OCP_USER_MPU,
3667 };
3668
3669 /* iva -> l3_instr */
3670 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3671         .master         = &omap44xx_iva_hwmod,
3672         .slave          = &omap44xx_l3_instr_hwmod,
3673         .clk            = "l3_div_ck",
3674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3675 };
3676
3677 /* l3_main_3 -> l3_instr */
3678 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3679         .master         = &omap44xx_l3_main_3_hwmod,
3680         .slave          = &omap44xx_l3_instr_hwmod,
3681         .clk            = "l3_div_ck",
3682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3683 };
3684
3685 /* ocp_wp_noc -> l3_instr */
3686 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3687         .master         = &omap44xx_ocp_wp_noc_hwmod,
3688         .slave          = &omap44xx_l3_instr_hwmod,
3689         .clk            = "l3_div_ck",
3690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3691 };
3692
3693 /* dsp -> l3_main_1 */
3694 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3695         .master         = &omap44xx_dsp_hwmod,
3696         .slave          = &omap44xx_l3_main_1_hwmod,
3697         .clk            = "l3_div_ck",
3698         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3699 };
3700
3701 /* dss -> l3_main_1 */
3702 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3703         .master         = &omap44xx_dss_hwmod,
3704         .slave          = &omap44xx_l3_main_1_hwmod,
3705         .clk            = "l3_div_ck",
3706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3707 };
3708
3709 /* l3_main_2 -> l3_main_1 */
3710 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3711         .master         = &omap44xx_l3_main_2_hwmod,
3712         .slave          = &omap44xx_l3_main_1_hwmod,
3713         .clk            = "l3_div_ck",
3714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3715 };
3716
3717 /* l4_cfg -> l3_main_1 */
3718 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3719         .master         = &omap44xx_l4_cfg_hwmod,
3720         .slave          = &omap44xx_l3_main_1_hwmod,
3721         .clk            = "l4_div_ck",
3722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3723 };
3724
3725 /* mmc1 -> l3_main_1 */
3726 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3727         .master         = &omap44xx_mmc1_hwmod,
3728         .slave          = &omap44xx_l3_main_1_hwmod,
3729         .clk            = "l3_div_ck",
3730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3731 };
3732
3733 /* mmc2 -> l3_main_1 */
3734 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3735         .master         = &omap44xx_mmc2_hwmod,
3736         .slave          = &omap44xx_l3_main_1_hwmod,
3737         .clk            = "l3_div_ck",
3738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3739 };
3740
3741 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3742         {
3743                 .pa_start       = 0x44000000,
3744                 .pa_end         = 0x44000fff,
3745                 .flags          = ADDR_TYPE_RT
3746         },
3747         { }
3748 };
3749
3750 /* mpu -> l3_main_1 */
3751 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3752         .master         = &omap44xx_mpu_hwmod,
3753         .slave          = &omap44xx_l3_main_1_hwmod,
3754         .clk            = "l3_div_ck",
3755         .addr           = omap44xx_l3_main_1_addrs,
3756         .user           = OCP_USER_MPU,
3757 };
3758
3759 /* c2c_target_fw -> l3_main_2 */
3760 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3761         .master         = &omap44xx_c2c_target_fw_hwmod,
3762         .slave          = &omap44xx_l3_main_2_hwmod,
3763         .clk            = "l3_div_ck",
3764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3765 };
3766
3767 /* debugss -> l3_main_2 */
3768 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3769         .master         = &omap44xx_debugss_hwmod,
3770         .slave          = &omap44xx_l3_main_2_hwmod,
3771         .clk            = "dbgclk_mux_ck",
3772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3773 };
3774
3775 /* dma_system -> l3_main_2 */
3776 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3777         .master         = &omap44xx_dma_system_hwmod,
3778         .slave          = &omap44xx_l3_main_2_hwmod,
3779         .clk            = "l3_div_ck",
3780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3781 };
3782
3783 /* fdif -> l3_main_2 */
3784 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3785         .master         = &omap44xx_fdif_hwmod,
3786         .slave          = &omap44xx_l3_main_2_hwmod,
3787         .clk            = "l3_div_ck",
3788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3789 };
3790
3791 /* gpu -> l3_main_2 */
3792 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3793         .master         = &omap44xx_gpu_hwmod,
3794         .slave          = &omap44xx_l3_main_2_hwmod,
3795         .clk            = "l3_div_ck",
3796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3797 };
3798
3799 /* hsi -> l3_main_2 */
3800 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3801         .master         = &omap44xx_hsi_hwmod,
3802         .slave          = &omap44xx_l3_main_2_hwmod,
3803         .clk            = "l3_div_ck",
3804         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3805 };
3806
3807 /* ipu -> l3_main_2 */
3808 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3809         .master         = &omap44xx_ipu_hwmod,
3810         .slave          = &omap44xx_l3_main_2_hwmod,
3811         .clk            = "l3_div_ck",
3812         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3813 };
3814
3815 /* iss -> l3_main_2 */
3816 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3817         .master         = &omap44xx_iss_hwmod,
3818         .slave          = &omap44xx_l3_main_2_hwmod,
3819         .clk            = "l3_div_ck",
3820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3821 };
3822
3823 /* iva -> l3_main_2 */
3824 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3825         .master         = &omap44xx_iva_hwmod,
3826         .slave          = &omap44xx_l3_main_2_hwmod,
3827         .clk            = "l3_div_ck",
3828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3829 };
3830
3831 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3832         {
3833                 .pa_start       = 0x44800000,
3834                 .pa_end         = 0x44801fff,
3835                 .flags          = ADDR_TYPE_RT
3836         },
3837         { }
3838 };
3839
3840 /* l3_main_1 -> l3_main_2 */
3841 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3842         .master         = &omap44xx_l3_main_1_hwmod,
3843         .slave          = &omap44xx_l3_main_2_hwmod,
3844         .clk            = "l3_div_ck",
3845         .addr           = omap44xx_l3_main_2_addrs,
3846         .user           = OCP_USER_MPU,
3847 };
3848
3849 /* l4_cfg -> l3_main_2 */
3850 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3851         .master         = &omap44xx_l4_cfg_hwmod,
3852         .slave          = &omap44xx_l3_main_2_hwmod,
3853         .clk            = "l4_div_ck",
3854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3855 };
3856
3857 /* usb_host_fs -> l3_main_2 */
3858 static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
3859         .master         = &omap44xx_usb_host_fs_hwmod,
3860         .slave          = &omap44xx_l3_main_2_hwmod,
3861         .clk            = "l3_div_ck",
3862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3863 };
3864
3865 /* usb_host_hs -> l3_main_2 */
3866 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3867         .master         = &omap44xx_usb_host_hs_hwmod,
3868         .slave          = &omap44xx_l3_main_2_hwmod,
3869         .clk            = "l3_div_ck",
3870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3871 };
3872
3873 /* usb_otg_hs -> l3_main_2 */
3874 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3875         .master         = &omap44xx_usb_otg_hs_hwmod,
3876         .slave          = &omap44xx_l3_main_2_hwmod,
3877         .clk            = "l3_div_ck",
3878         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3879 };
3880
3881 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3882         {
3883                 .pa_start       = 0x45000000,
3884                 .pa_end         = 0x45000fff,
3885                 .flags          = ADDR_TYPE_RT
3886         },
3887         { }
3888 };
3889
3890 /* l3_main_1 -> l3_main_3 */
3891 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3892         .master         = &omap44xx_l3_main_1_hwmod,
3893         .slave          = &omap44xx_l3_main_3_hwmod,
3894         .clk            = "l3_div_ck",
3895         .addr           = omap44xx_l3_main_3_addrs,
3896         .user           = OCP_USER_MPU,
3897 };
3898
3899 /* l3_main_2 -> l3_main_3 */
3900 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3901         .master         = &omap44xx_l3_main_2_hwmod,
3902         .slave          = &omap44xx_l3_main_3_hwmod,
3903         .clk            = "l3_div_ck",
3904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3905 };
3906
3907 /* l4_cfg -> l3_main_3 */
3908 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3909         .master         = &omap44xx_l4_cfg_hwmod,
3910         .slave          = &omap44xx_l3_main_3_hwmod,
3911         .clk            = "l4_div_ck",
3912         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3913 };
3914
3915 /* aess -> l4_abe */
3916 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
3917         .master         = &omap44xx_aess_hwmod,
3918         .slave          = &omap44xx_l4_abe_hwmod,
3919         .clk            = "ocp_abe_iclk",
3920         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3921 };
3922
3923 /* dsp -> l4_abe */
3924 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3925         .master         = &omap44xx_dsp_hwmod,
3926         .slave          = &omap44xx_l4_abe_hwmod,
3927         .clk            = "ocp_abe_iclk",
3928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3929 };
3930
3931 /* l3_main_1 -> l4_abe */
3932 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3933         .master         = &omap44xx_l3_main_1_hwmod,
3934         .slave          = &omap44xx_l4_abe_hwmod,
3935         .clk            = "l3_div_ck",
3936         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3937 };
3938
3939 /* mpu -> l4_abe */
3940 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3941         .master         = &omap44xx_mpu_hwmod,
3942         .slave          = &omap44xx_l4_abe_hwmod,
3943         .clk            = "ocp_abe_iclk",
3944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3945 };
3946
3947 /* l3_main_1 -> l4_cfg */
3948 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3949         .master         = &omap44xx_l3_main_1_hwmod,
3950         .slave          = &omap44xx_l4_cfg_hwmod,
3951         .clk            = "l3_div_ck",
3952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3953 };
3954
3955 /* l3_main_2 -> l4_per */
3956 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3957         .master         = &omap44xx_l3_main_2_hwmod,
3958         .slave          = &omap44xx_l4_per_hwmod,
3959         .clk            = "l3_div_ck",
3960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3961 };
3962
3963 /* l4_cfg -> l4_wkup */
3964 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3965         .master         = &omap44xx_l4_cfg_hwmod,
3966         .slave          = &omap44xx_l4_wkup_hwmod,
3967         .clk            = "l4_div_ck",
3968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3969 };
3970
3971 /* mpu -> mpu_private */
3972 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3973         .master         = &omap44xx_mpu_hwmod,
3974         .slave          = &omap44xx_mpu_private_hwmod,
3975         .clk            = "l3_div_ck",
3976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3977 };
3978
3979 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3980         {
3981                 .pa_start       = 0x4a102000,
3982                 .pa_end         = 0x4a10207f,
3983                 .flags          = ADDR_TYPE_RT
3984         },
3985         { }
3986 };
3987
3988 /* l4_cfg -> ocp_wp_noc */
3989 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3990         .master         = &omap44xx_l4_cfg_hwmod,
3991         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3992         .clk            = "l4_div_ck",
3993         .addr           = omap44xx_ocp_wp_noc_addrs,
3994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3995 };
3996
3997 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3998         {
3999                 .pa_start       = 0x401f1000,
4000                 .pa_end         = 0x401f13ff,
4001                 .flags          = ADDR_TYPE_RT
4002         },
4003         { }
4004 };
4005
4006 /* l4_abe -> aess */
4007 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
4008         .master         = &omap44xx_l4_abe_hwmod,
4009         .slave          = &omap44xx_aess_hwmod,
4010         .clk            = "ocp_abe_iclk",
4011         .addr           = omap44xx_aess_addrs,
4012         .user           = OCP_USER_MPU,
4013 };
4014
4015 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4016         {
4017                 .pa_start       = 0x490f1000,
4018                 .pa_end         = 0x490f13ff,
4019                 .flags          = ADDR_TYPE_RT
4020         },
4021         { }
4022 };
4023
4024 /* l4_abe -> aess (dma) */
4025 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
4026         .master         = &omap44xx_l4_abe_hwmod,
4027         .slave          = &omap44xx_aess_hwmod,
4028         .clk            = "ocp_abe_iclk",
4029         .addr           = omap44xx_aess_dma_addrs,
4030         .user           = OCP_USER_SDMA,
4031 };
4032
4033 /* l3_main_2 -> c2c */
4034 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4035         .master         = &omap44xx_l3_main_2_hwmod,
4036         .slave          = &omap44xx_c2c_hwmod,
4037         .clk            = "l3_div_ck",
4038         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4039 };
4040
4041 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4042         {
4043                 .pa_start       = 0x4a304000,
4044                 .pa_end         = 0x4a30401f,
4045                 .flags          = ADDR_TYPE_RT
4046         },
4047         { }
4048 };
4049
4050 /* l4_wkup -> counter_32k */
4051 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4052         .master         = &omap44xx_l4_wkup_hwmod,
4053         .slave          = &omap44xx_counter_32k_hwmod,
4054         .clk            = "l4_wkup_clk_mux_ck",
4055         .addr           = omap44xx_counter_32k_addrs,
4056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4057 };
4058
4059 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4060         {
4061                 .pa_start       = 0x4a002000,
4062                 .pa_end         = 0x4a0027ff,
4063                 .flags          = ADDR_TYPE_RT
4064         },
4065         { }
4066 };
4067
4068 /* l4_cfg -> ctrl_module_core */
4069 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4070         .master         = &omap44xx_l4_cfg_hwmod,
4071         .slave          = &omap44xx_ctrl_module_core_hwmod,
4072         .clk            = "l4_div_ck",
4073         .addr           = omap44xx_ctrl_module_core_addrs,
4074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4075 };
4076
4077 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4078         {
4079                 .pa_start       = 0x4a100000,
4080                 .pa_end         = 0x4a1007ff,
4081                 .flags          = ADDR_TYPE_RT
4082         },
4083         { }
4084 };
4085
4086 /* l4_cfg -> ctrl_module_pad_core */
4087 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4088         .master         = &omap44xx_l4_cfg_hwmod,
4089         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4090         .clk            = "l4_div_ck",
4091         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4093 };
4094
4095 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4096         {
4097                 .pa_start       = 0x4a30c000,
4098                 .pa_end         = 0x4a30c7ff,
4099                 .flags          = ADDR_TYPE_RT
4100         },
4101         { }
4102 };
4103
4104 /* l4_wkup -> ctrl_module_wkup */
4105 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4106         .master         = &omap44xx_l4_wkup_hwmod,
4107         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4108         .clk            = "l4_wkup_clk_mux_ck",
4109         .addr           = omap44xx_ctrl_module_wkup_addrs,
4110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4111 };
4112
4113 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4114         {
4115                 .pa_start       = 0x4a31e000,
4116                 .pa_end         = 0x4a31e7ff,
4117                 .flags          = ADDR_TYPE_RT
4118         },
4119         { }
4120 };
4121
4122 /* l4_wkup -> ctrl_module_pad_wkup */
4123 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4124         .master         = &omap44xx_l4_wkup_hwmod,
4125         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4126         .clk            = "l4_wkup_clk_mux_ck",
4127         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4129 };
4130
4131 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4132         {
4133                 .pa_start       = 0x54160000,
4134                 .pa_end         = 0x54167fff,
4135                 .flags          = ADDR_TYPE_RT
4136         },
4137         { }
4138 };
4139
4140 /* l3_instr -> debugss */
4141 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4142         .master         = &omap44xx_l3_instr_hwmod,
4143         .slave          = &omap44xx_debugss_hwmod,
4144         .clk            = "l3_div_ck",
4145         .addr           = omap44xx_debugss_addrs,
4146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4147 };
4148
4149 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4150         {
4151                 .pa_start       = 0x4a056000,
4152                 .pa_end         = 0x4a056fff,
4153                 .flags          = ADDR_TYPE_RT
4154         },
4155         { }
4156 };
4157
4158 /* l4_cfg -> dma_system */
4159 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4160         .master         = &omap44xx_l4_cfg_hwmod,
4161         .slave          = &omap44xx_dma_system_hwmod,
4162         .clk            = "l4_div_ck",
4163         .addr           = omap44xx_dma_system_addrs,
4164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4165 };
4166
4167 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4168         {
4169                 .name           = "mpu",
4170                 .pa_start       = 0x4012e000,
4171                 .pa_end         = 0x4012e07f,
4172                 .flags          = ADDR_TYPE_RT
4173         },
4174         { }
4175 };
4176
4177 /* l4_abe -> dmic */
4178 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4179         .master         = &omap44xx_l4_abe_hwmod,
4180         .slave          = &omap44xx_dmic_hwmod,
4181         .clk            = "ocp_abe_iclk",
4182         .addr           = omap44xx_dmic_addrs,
4183         .user           = OCP_USER_MPU,
4184 };
4185
4186 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4187         {
4188                 .name           = "dma",
4189                 .pa_start       = 0x4902e000,
4190                 .pa_end         = 0x4902e07f,
4191                 .flags          = ADDR_TYPE_RT
4192         },
4193         { }
4194 };
4195
4196 /* l4_abe -> dmic (dma) */
4197 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4198         .master         = &omap44xx_l4_abe_hwmod,
4199         .slave          = &omap44xx_dmic_hwmod,
4200         .clk            = "ocp_abe_iclk",
4201         .addr           = omap44xx_dmic_dma_addrs,
4202         .user           = OCP_USER_SDMA,
4203 };
4204
4205 /* dsp -> iva */
4206 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4207         .master         = &omap44xx_dsp_hwmod,
4208         .slave          = &omap44xx_iva_hwmod,
4209         .clk            = "dpll_iva_m5x2_ck",
4210         .user           = OCP_USER_DSP,
4211 };
4212
4213 /* dsp -> sl2if */
4214 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4215         .master         = &omap44xx_dsp_hwmod,
4216         .slave          = &omap44xx_sl2if_hwmod,
4217         .clk            = "dpll_iva_m5x2_ck",
4218         .user           = OCP_USER_DSP,
4219 };
4220
4221 /* l4_cfg -> dsp */
4222 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4223         .master         = &omap44xx_l4_cfg_hwmod,
4224         .slave          = &omap44xx_dsp_hwmod,
4225         .clk            = "l4_div_ck",
4226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4227 };
4228
4229 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4230         {
4231                 .pa_start       = 0x58000000,
4232                 .pa_end         = 0x5800007f,
4233                 .flags          = ADDR_TYPE_RT
4234         },
4235         { }
4236 };
4237
4238 /* l3_main_2 -> dss */
4239 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4240         .master         = &omap44xx_l3_main_2_hwmod,
4241         .slave          = &omap44xx_dss_hwmod,
4242         .clk            = "dss_fck",
4243         .addr           = omap44xx_dss_dma_addrs,
4244         .user           = OCP_USER_SDMA,
4245 };
4246
4247 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4248         {
4249                 .pa_start       = 0x48040000,
4250                 .pa_end         = 0x4804007f,
4251                 .flags          = ADDR_TYPE_RT
4252         },
4253         { }
4254 };
4255
4256 /* l4_per -> dss */
4257 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4258         .master         = &omap44xx_l4_per_hwmod,
4259         .slave          = &omap44xx_dss_hwmod,
4260         .clk            = "l4_div_ck",
4261         .addr           = omap44xx_dss_addrs,
4262         .user           = OCP_USER_MPU,
4263 };
4264
4265 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4266         {
4267                 .pa_start       = 0x58001000,
4268                 .pa_end         = 0x58001fff,
4269                 .flags          = ADDR_TYPE_RT
4270         },
4271         { }
4272 };
4273
4274 /* l3_main_2 -> dss_dispc */
4275 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4276         .master         = &omap44xx_l3_main_2_hwmod,
4277         .slave          = &omap44xx_dss_dispc_hwmod,
4278         .clk            = "dss_fck",
4279         .addr           = omap44xx_dss_dispc_dma_addrs,
4280         .user           = OCP_USER_SDMA,
4281 };
4282
4283 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4284         {
4285                 .pa_start       = 0x48041000,
4286                 .pa_end         = 0x48041fff,
4287                 .flags          = ADDR_TYPE_RT
4288         },
4289         { }
4290 };
4291
4292 /* l4_per -> dss_dispc */
4293 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4294         .master         = &omap44xx_l4_per_hwmod,
4295         .slave          = &omap44xx_dss_dispc_hwmod,
4296         .clk            = "l4_div_ck",
4297         .addr           = omap44xx_dss_dispc_addrs,
4298         .user           = OCP_USER_MPU,
4299 };
4300
4301 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4302         {
4303                 .pa_start       = 0x58004000,
4304                 .pa_end         = 0x580041ff,
4305                 .flags          = ADDR_TYPE_RT
4306         },
4307         { }
4308 };
4309
4310 /* l3_main_2 -> dss_dsi1 */
4311 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4312         .master         = &omap44xx_l3_main_2_hwmod,
4313         .slave          = &omap44xx_dss_dsi1_hwmod,
4314         .clk            = "dss_fck",
4315         .addr           = omap44xx_dss_dsi1_dma_addrs,
4316         .user           = OCP_USER_SDMA,
4317 };
4318
4319 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4320         {
4321                 .pa_start       = 0x48044000,
4322                 .pa_end         = 0x480441ff,
4323                 .flags          = ADDR_TYPE_RT
4324         },
4325         { }
4326 };
4327
4328 /* l4_per -> dss_dsi1 */
4329 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4330         .master         = &omap44xx_l4_per_hwmod,
4331         .slave          = &omap44xx_dss_dsi1_hwmod,
4332         .clk            = "l4_div_ck",
4333         .addr           = omap44xx_dss_dsi1_addrs,
4334         .user           = OCP_USER_MPU,
4335 };
4336
4337 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4338         {
4339                 .pa_start       = 0x58005000,
4340                 .pa_end         = 0x580051ff,
4341                 .flags          = ADDR_TYPE_RT
4342         },
4343         { }
4344 };
4345
4346 /* l3_main_2 -> dss_dsi2 */
4347 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4348         .master         = &omap44xx_l3_main_2_hwmod,
4349         .slave          = &omap44xx_dss_dsi2_hwmod,
4350         .clk            = "dss_fck",
4351         .addr           = omap44xx_dss_dsi2_dma_addrs,
4352         .user           = OCP_USER_SDMA,
4353 };
4354
4355 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4356         {
4357                 .pa_start       = 0x48045000,
4358                 .pa_end         = 0x480451ff,
4359                 .flags          = ADDR_TYPE_RT
4360         },
4361         { }
4362 };
4363
4364 /* l4_per -> dss_dsi2 */
4365 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4366         .master         = &omap44xx_l4_per_hwmod,
4367         .slave          = &omap44xx_dss_dsi2_hwmod,
4368         .clk            = "l4_div_ck",
4369         .addr           = omap44xx_dss_dsi2_addrs,
4370         .user           = OCP_USER_MPU,
4371 };
4372
4373 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4374         {
4375                 .pa_start       = 0x58006000,
4376                 .pa_end         = 0x58006fff,
4377                 .flags          = ADDR_TYPE_RT
4378         },
4379         { }
4380 };
4381
4382 /* l3_main_2 -> dss_hdmi */
4383 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4384         .master         = &omap44xx_l3_main_2_hwmod,
4385         .slave          = &omap44xx_dss_hdmi_hwmod,
4386         .clk            = "dss_fck",
4387         .addr           = omap44xx_dss_hdmi_dma_addrs,
4388         .user           = OCP_USER_SDMA,
4389 };
4390
4391 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4392         {
4393                 .pa_start       = 0x48046000,
4394                 .pa_end         = 0x48046fff,
4395                 .flags          = ADDR_TYPE_RT
4396         },
4397         { }
4398 };
4399
4400 /* l4_per -> dss_hdmi */
4401 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4402         .master         = &omap44xx_l4_per_hwmod,
4403         .slave          = &omap44xx_dss_hdmi_hwmod,
4404         .clk            = "l4_div_ck",
4405         .addr           = omap44xx_dss_hdmi_addrs,
4406         .user           = OCP_USER_MPU,
4407 };
4408
4409 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4410         {
4411                 .pa_start       = 0x58002000,
4412                 .pa_end         = 0x580020ff,
4413                 .flags          = ADDR_TYPE_RT
4414         },
4415         { }
4416 };
4417
4418 /* l3_main_2 -> dss_rfbi */
4419 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4420         .master         = &omap44xx_l3_main_2_hwmod,
4421         .slave          = &omap44xx_dss_rfbi_hwmod,
4422         .clk            = "dss_fck",
4423         .addr           = omap44xx_dss_rfbi_dma_addrs,
4424         .user           = OCP_USER_SDMA,
4425 };
4426
4427 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4428         {
4429                 .pa_start       = 0x48042000,
4430                 .pa_end         = 0x480420ff,
4431                 .flags          = ADDR_TYPE_RT
4432         },
4433         { }
4434 };
4435
4436 /* l4_per -> dss_rfbi */
4437 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4438         .master         = &omap44xx_l4_per_hwmod,
4439         .slave          = &omap44xx_dss_rfbi_hwmod,
4440         .clk            = "l4_div_ck",
4441         .addr           = omap44xx_dss_rfbi_addrs,
4442         .user           = OCP_USER_MPU,
4443 };
4444
4445 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4446         {
4447                 .pa_start       = 0x58003000,
4448                 .pa_end         = 0x580030ff,
4449                 .flags          = ADDR_TYPE_RT
4450         },
4451         { }
4452 };
4453
4454 /* l3_main_2 -> dss_venc */
4455 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4456         .master         = &omap44xx_l3_main_2_hwmod,
4457         .slave          = &omap44xx_dss_venc_hwmod,
4458         .clk            = "dss_fck",
4459         .addr           = omap44xx_dss_venc_dma_addrs,
4460         .user           = OCP_USER_SDMA,
4461 };
4462
4463 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4464         {
4465                 .pa_start       = 0x48043000,
4466                 .pa_end         = 0x480430ff,
4467                 .flags          = ADDR_TYPE_RT
4468         },
4469         { }
4470 };
4471
4472 /* l4_per -> dss_venc */
4473 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4474         .master         = &omap44xx_l4_per_hwmod,
4475         .slave          = &omap44xx_dss_venc_hwmod,
4476         .clk            = "l4_div_ck",
4477         .addr           = omap44xx_dss_venc_addrs,
4478         .user           = OCP_USER_MPU,
4479 };
4480
4481 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4482         {
4483                 .pa_start       = 0x48078000,
4484                 .pa_end         = 0x48078fff,
4485                 .flags          = ADDR_TYPE_RT
4486         },
4487         { }
4488 };
4489
4490 /* l4_per -> elm */
4491 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4492         .master         = &omap44xx_l4_per_hwmod,
4493         .slave          = &omap44xx_elm_hwmod,
4494         .clk            = "l4_div_ck",
4495         .addr           = omap44xx_elm_addrs,
4496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4497 };
4498
4499 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4500         {
4501                 .pa_start       = 0x4c000000,
4502                 .pa_end         = 0x4c0000ff,
4503                 .flags          = ADDR_TYPE_RT
4504         },
4505         { }
4506 };
4507
4508 /* emif_fw -> emif1 */
4509 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4510         .master         = &omap44xx_emif_fw_hwmod,
4511         .slave          = &omap44xx_emif1_hwmod,
4512         .clk            = "l3_div_ck",
4513         .addr           = omap44xx_emif1_addrs,
4514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4515 };
4516
4517 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4518         {
4519                 .pa_start       = 0x4d000000,
4520                 .pa_end         = 0x4d0000ff,
4521                 .flags          = ADDR_TYPE_RT
4522         },
4523         { }
4524 };
4525
4526 /* emif_fw -> emif2 */
4527 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4528         .master         = &omap44xx_emif_fw_hwmod,
4529         .slave          = &omap44xx_emif2_hwmod,
4530         .clk            = "l3_div_ck",
4531         .addr           = omap44xx_emif2_addrs,
4532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4533 };
4534
4535 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4536         {
4537                 .pa_start       = 0x4a10a000,
4538                 .pa_end         = 0x4a10a1ff,
4539                 .flags          = ADDR_TYPE_RT
4540         },
4541         { }
4542 };
4543
4544 /* l4_cfg -> fdif */
4545 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4546         .master         = &omap44xx_l4_cfg_hwmod,
4547         .slave          = &omap44xx_fdif_hwmod,
4548         .clk            = "l4_div_ck",
4549         .addr           = omap44xx_fdif_addrs,
4550         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4551 };
4552
4553 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4554         {
4555                 .pa_start       = 0x4a310000,
4556                 .pa_end         = 0x4a3101ff,
4557                 .flags          = ADDR_TYPE_RT
4558         },
4559         { }
4560 };
4561
4562 /* l4_wkup -> gpio1 */
4563 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4564         .master         = &omap44xx_l4_wkup_hwmod,
4565         .slave          = &omap44xx_gpio1_hwmod,
4566         .clk            = "l4_wkup_clk_mux_ck",
4567         .addr           = omap44xx_gpio1_addrs,
4568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4569 };
4570
4571 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4572         {
4573                 .pa_start       = 0x48055000,
4574                 .pa_end         = 0x480551ff,
4575                 .flags          = ADDR_TYPE_RT
4576         },
4577         { }
4578 };
4579
4580 /* l4_per -> gpio2 */
4581 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4582         .master         = &omap44xx_l4_per_hwmod,
4583         .slave          = &omap44xx_gpio2_hwmod,
4584         .clk            = "l4_div_ck",
4585         .addr           = omap44xx_gpio2_addrs,
4586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4587 };
4588
4589 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4590         {
4591                 .pa_start       = 0x48057000,
4592                 .pa_end         = 0x480571ff,
4593                 .flags          = ADDR_TYPE_RT
4594         },
4595         { }
4596 };
4597
4598 /* l4_per -> gpio3 */
4599 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4600         .master         = &omap44xx_l4_per_hwmod,
4601         .slave          = &omap44xx_gpio3_hwmod,
4602         .clk            = "l4_div_ck",
4603         .addr           = omap44xx_gpio3_addrs,
4604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4605 };
4606
4607 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4608         {
4609                 .pa_start       = 0x48059000,
4610                 .pa_end         = 0x480591ff,
4611                 .flags          = ADDR_TYPE_RT
4612         },
4613         { }
4614 };
4615
4616 /* l4_per -> gpio4 */
4617 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4618         .master         = &omap44xx_l4_per_hwmod,
4619         .slave          = &omap44xx_gpio4_hwmod,
4620         .clk            = "l4_div_ck",
4621         .addr           = omap44xx_gpio4_addrs,
4622         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4623 };
4624
4625 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4626         {
4627                 .pa_start       = 0x4805b000,
4628                 .pa_end         = 0x4805b1ff,
4629                 .flags          = ADDR_TYPE_RT
4630         },
4631         { }
4632 };
4633
4634 /* l4_per -> gpio5 */
4635 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4636         .master         = &omap44xx_l4_per_hwmod,
4637         .slave          = &omap44xx_gpio5_hwmod,
4638         .clk            = "l4_div_ck",
4639         .addr           = omap44xx_gpio5_addrs,
4640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4641 };
4642
4643 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4644         {
4645                 .pa_start       = 0x4805d000,
4646                 .pa_end         = 0x4805d1ff,
4647                 .flags          = ADDR_TYPE_RT
4648         },
4649         { }
4650 };
4651
4652 /* l4_per -> gpio6 */
4653 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4654         .master         = &omap44xx_l4_per_hwmod,
4655         .slave          = &omap44xx_gpio6_hwmod,
4656         .clk            = "l4_div_ck",
4657         .addr           = omap44xx_gpio6_addrs,
4658         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4659 };
4660
4661 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4662         {
4663                 .pa_start       = 0x50000000,
4664                 .pa_end         = 0x500003ff,
4665                 .flags          = ADDR_TYPE_RT
4666         },
4667         { }
4668 };
4669
4670 /* l3_main_2 -> gpmc */
4671 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4672         .master         = &omap44xx_l3_main_2_hwmod,
4673         .slave          = &omap44xx_gpmc_hwmod,
4674         .clk            = "l3_div_ck",
4675         .addr           = omap44xx_gpmc_addrs,
4676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4677 };
4678
4679 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4680         {
4681                 .pa_start       = 0x56000000,
4682                 .pa_end         = 0x5600ffff,
4683                 .flags          = ADDR_TYPE_RT
4684         },
4685         { }
4686 };
4687
4688 /* l3_main_2 -> gpu */
4689 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4690         .master         = &omap44xx_l3_main_2_hwmod,
4691         .slave          = &omap44xx_gpu_hwmod,
4692         .clk            = "l3_div_ck",
4693         .addr           = omap44xx_gpu_addrs,
4694         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4695 };
4696
4697 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4698         {
4699                 .pa_start       = 0x480b2000,
4700                 .pa_end         = 0x480b201f,
4701                 .flags          = ADDR_TYPE_RT
4702         },
4703         { }
4704 };
4705
4706 /* l4_per -> hdq1w */
4707 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4708         .master         = &omap44xx_l4_per_hwmod,
4709         .slave          = &omap44xx_hdq1w_hwmod,
4710         .clk            = "l4_div_ck",
4711         .addr           = omap44xx_hdq1w_addrs,
4712         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4713 };
4714
4715 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4716         {
4717                 .pa_start       = 0x4a058000,
4718                 .pa_end         = 0x4a05bfff,
4719                 .flags          = ADDR_TYPE_RT
4720         },
4721         { }
4722 };
4723
4724 /* l4_cfg -> hsi */
4725 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4726         .master         = &omap44xx_l4_cfg_hwmod,
4727         .slave          = &omap44xx_hsi_hwmod,
4728         .clk            = "l4_div_ck",
4729         .addr           = omap44xx_hsi_addrs,
4730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4731 };
4732
4733 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4734         {
4735                 .pa_start       = 0x48070000,
4736                 .pa_end         = 0x480700ff,
4737                 .flags          = ADDR_TYPE_RT
4738         },
4739         { }
4740 };
4741
4742 /* l4_per -> i2c1 */
4743 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4744         .master         = &omap44xx_l4_per_hwmod,
4745         .slave          = &omap44xx_i2c1_hwmod,
4746         .clk            = "l4_div_ck",
4747         .addr           = omap44xx_i2c1_addrs,
4748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4749 };
4750
4751 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4752         {
4753                 .pa_start       = 0x48072000,
4754                 .pa_end         = 0x480720ff,
4755                 .flags          = ADDR_TYPE_RT
4756         },
4757         { }
4758 };
4759
4760 /* l4_per -> i2c2 */
4761 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4762         .master         = &omap44xx_l4_per_hwmod,
4763         .slave          = &omap44xx_i2c2_hwmod,
4764         .clk            = "l4_div_ck",
4765         .addr           = omap44xx_i2c2_addrs,
4766         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4767 };
4768
4769 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4770         {
4771                 .pa_start       = 0x48060000,
4772                 .pa_end         = 0x480600ff,
4773                 .flags          = ADDR_TYPE_RT
4774         },
4775         { }
4776 };
4777
4778 /* l4_per -> i2c3 */
4779 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4780         .master         = &omap44xx_l4_per_hwmod,
4781         .slave          = &omap44xx_i2c3_hwmod,
4782         .clk            = "l4_div_ck",
4783         .addr           = omap44xx_i2c3_addrs,
4784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4785 };
4786
4787 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4788         {
4789                 .pa_start       = 0x48350000,
4790                 .pa_end         = 0x483500ff,
4791                 .flags          = ADDR_TYPE_RT
4792         },
4793         { }
4794 };
4795
4796 /* l4_per -> i2c4 */
4797 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4798         .master         = &omap44xx_l4_per_hwmod,
4799         .slave          = &omap44xx_i2c4_hwmod,
4800         .clk            = "l4_div_ck",
4801         .addr           = omap44xx_i2c4_addrs,
4802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4803 };
4804
4805 /* l3_main_2 -> ipu */
4806 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4807         .master         = &omap44xx_l3_main_2_hwmod,
4808         .slave          = &omap44xx_ipu_hwmod,
4809         .clk            = "l3_div_ck",
4810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4811 };
4812
4813 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4814         {
4815                 .pa_start       = 0x52000000,
4816                 .pa_end         = 0x520000ff,
4817                 .flags          = ADDR_TYPE_RT
4818         },
4819         { }
4820 };
4821
4822 /* l3_main_2 -> iss */
4823 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4824         .master         = &omap44xx_l3_main_2_hwmod,
4825         .slave          = &omap44xx_iss_hwmod,
4826         .clk            = "l3_div_ck",
4827         .addr           = omap44xx_iss_addrs,
4828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4829 };
4830
4831 /* iva -> sl2if */
4832 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4833         .master         = &omap44xx_iva_hwmod,
4834         .slave          = &omap44xx_sl2if_hwmod,
4835         .clk            = "dpll_iva_m5x2_ck",
4836         .user           = OCP_USER_IVA,
4837 };
4838
4839 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4840         {
4841                 .pa_start       = 0x5a000000,
4842                 .pa_end         = 0x5a07ffff,
4843                 .flags          = ADDR_TYPE_RT
4844         },
4845         { }
4846 };
4847
4848 /* l3_main_2 -> iva */
4849 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4850         .master         = &omap44xx_l3_main_2_hwmod,
4851         .slave          = &omap44xx_iva_hwmod,
4852         .clk            = "l3_div_ck",
4853         .addr           = omap44xx_iva_addrs,
4854         .user           = OCP_USER_MPU,
4855 };
4856
4857 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4858         {
4859                 .pa_start       = 0x4a31c000,
4860                 .pa_end         = 0x4a31c07f,
4861                 .flags          = ADDR_TYPE_RT
4862         },
4863         { }
4864 };
4865
4866 /* l4_wkup -> kbd */
4867 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4868         .master         = &omap44xx_l4_wkup_hwmod,
4869         .slave          = &omap44xx_kbd_hwmod,
4870         .clk            = "l4_wkup_clk_mux_ck",
4871         .addr           = omap44xx_kbd_addrs,
4872         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4873 };
4874
4875 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4876         {
4877                 .pa_start       = 0x4a0f4000,
4878                 .pa_end         = 0x4a0f41ff,
4879                 .flags          = ADDR_TYPE_RT
4880         },
4881         { }
4882 };
4883
4884 /* l4_cfg -> mailbox */
4885 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4886         .master         = &omap44xx_l4_cfg_hwmod,
4887         .slave          = &omap44xx_mailbox_hwmod,
4888         .clk            = "l4_div_ck",
4889         .addr           = omap44xx_mailbox_addrs,
4890         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4891 };
4892
4893 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4894         {
4895                 .pa_start       = 0x40128000,
4896                 .pa_end         = 0x401283ff,
4897                 .flags          = ADDR_TYPE_RT
4898         },
4899         { }
4900 };
4901
4902 /* l4_abe -> mcasp */
4903 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4904         .master         = &omap44xx_l4_abe_hwmod,
4905         .slave          = &omap44xx_mcasp_hwmod,
4906         .clk            = "ocp_abe_iclk",
4907         .addr           = omap44xx_mcasp_addrs,
4908         .user           = OCP_USER_MPU,
4909 };
4910
4911 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4912         {
4913                 .pa_start       = 0x49028000,
4914                 .pa_end         = 0x490283ff,
4915                 .flags          = ADDR_TYPE_RT
4916         },
4917         { }
4918 };
4919
4920 /* l4_abe -> mcasp (dma) */
4921 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4922         .master         = &omap44xx_l4_abe_hwmod,
4923         .slave          = &omap44xx_mcasp_hwmod,
4924         .clk            = "ocp_abe_iclk",
4925         .addr           = omap44xx_mcasp_dma_addrs,
4926         .user           = OCP_USER_SDMA,
4927 };
4928
4929 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4930         {
4931                 .name           = "mpu",
4932                 .pa_start       = 0x40122000,
4933                 .pa_end         = 0x401220ff,
4934                 .flags          = ADDR_TYPE_RT
4935         },
4936         { }
4937 };
4938
4939 /* l4_abe -> mcbsp1 */
4940 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4941         .master         = &omap44xx_l4_abe_hwmod,
4942         .slave          = &omap44xx_mcbsp1_hwmod,
4943         .clk            = "ocp_abe_iclk",
4944         .addr           = omap44xx_mcbsp1_addrs,
4945         .user           = OCP_USER_MPU,
4946 };
4947
4948 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4949         {
4950                 .name           = "dma",
4951                 .pa_start       = 0x49022000,
4952                 .pa_end         = 0x490220ff,
4953                 .flags          = ADDR_TYPE_RT
4954         },
4955         { }
4956 };
4957
4958 /* l4_abe -> mcbsp1 (dma) */
4959 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4960         .master         = &omap44xx_l4_abe_hwmod,
4961         .slave          = &omap44xx_mcbsp1_hwmod,
4962         .clk            = "ocp_abe_iclk",
4963         .addr           = omap44xx_mcbsp1_dma_addrs,
4964         .user           = OCP_USER_SDMA,
4965 };
4966
4967 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4968         {
4969                 .name           = "mpu",
4970                 .pa_start       = 0x40124000,
4971                 .pa_end         = 0x401240ff,
4972                 .flags          = ADDR_TYPE_RT
4973         },
4974         { }
4975 };
4976
4977 /* l4_abe -> mcbsp2 */
4978 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4979         .master         = &omap44xx_l4_abe_hwmod,
4980         .slave          = &omap44xx_mcbsp2_hwmod,
4981         .clk            = "ocp_abe_iclk",
4982         .addr           = omap44xx_mcbsp2_addrs,
4983         .user           = OCP_USER_MPU,
4984 };
4985
4986 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4987         {
4988                 .name           = "dma",
4989                 .pa_start       = 0x49024000,
4990                 .pa_end         = 0x490240ff,
4991                 .flags          = ADDR_TYPE_RT
4992         },
4993         { }
4994 };
4995
4996 /* l4_abe -> mcbsp2 (dma) */
4997 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4998         .master         = &omap44xx_l4_abe_hwmod,
4999         .slave          = &omap44xx_mcbsp2_hwmod,
5000         .clk            = "ocp_abe_iclk",
5001         .addr           = omap44xx_mcbsp2_dma_addrs,
5002         .user           = OCP_USER_SDMA,
5003 };
5004
5005 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5006         {
5007                 .name           = "mpu",
5008                 .pa_start       = 0x40126000,
5009                 .pa_end         = 0x401260ff,
5010                 .flags          = ADDR_TYPE_RT
5011         },
5012         { }
5013 };
5014
5015 /* l4_abe -> mcbsp3 */
5016 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5017         .master         = &omap44xx_l4_abe_hwmod,
5018         .slave          = &omap44xx_mcbsp3_hwmod,
5019         .clk            = "ocp_abe_iclk",
5020         .addr           = omap44xx_mcbsp3_addrs,
5021         .user           = OCP_USER_MPU,
5022 };
5023
5024 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5025         {
5026                 .name           = "dma",
5027                 .pa_start       = 0x49026000,
5028                 .pa_end         = 0x490260ff,
5029                 .flags          = ADDR_TYPE_RT
5030         },
5031         { }
5032 };
5033
5034 /* l4_abe -> mcbsp3 (dma) */
5035 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5036         .master         = &omap44xx_l4_abe_hwmod,
5037         .slave          = &omap44xx_mcbsp3_hwmod,
5038         .clk            = "ocp_abe_iclk",
5039         .addr           = omap44xx_mcbsp3_dma_addrs,
5040         .user           = OCP_USER_SDMA,
5041 };
5042
5043 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5044         {
5045                 .pa_start       = 0x48096000,
5046                 .pa_end         = 0x480960ff,
5047                 .flags          = ADDR_TYPE_RT
5048         },
5049         { }
5050 };
5051
5052 /* l4_per -> mcbsp4 */
5053 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5054         .master         = &omap44xx_l4_per_hwmod,
5055         .slave          = &omap44xx_mcbsp4_hwmod,
5056         .clk            = "l4_div_ck",
5057         .addr           = omap44xx_mcbsp4_addrs,
5058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5059 };
5060
5061 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5062         {
5063                 .pa_start       = 0x40132000,
5064                 .pa_end         = 0x4013207f,
5065                 .flags          = ADDR_TYPE_RT
5066         },
5067         { }
5068 };
5069
5070 /* l4_abe -> mcpdm */
5071 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5072         .master         = &omap44xx_l4_abe_hwmod,
5073         .slave          = &omap44xx_mcpdm_hwmod,
5074         .clk            = "ocp_abe_iclk",
5075         .addr           = omap44xx_mcpdm_addrs,
5076         .user           = OCP_USER_MPU,
5077 };
5078
5079 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5080         {
5081                 .pa_start       = 0x49032000,
5082                 .pa_end         = 0x4903207f,
5083                 .flags          = ADDR_TYPE_RT
5084         },
5085         { }
5086 };
5087
5088 /* l4_abe -> mcpdm (dma) */
5089 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5090         .master         = &omap44xx_l4_abe_hwmod,
5091         .slave          = &omap44xx_mcpdm_hwmod,
5092         .clk            = "ocp_abe_iclk",
5093         .addr           = omap44xx_mcpdm_dma_addrs,
5094         .user           = OCP_USER_SDMA,
5095 };
5096
5097 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5098         {
5099                 .pa_start       = 0x48098000,
5100                 .pa_end         = 0x480981ff,
5101                 .flags          = ADDR_TYPE_RT
5102         },
5103         { }
5104 };
5105
5106 /* l4_per -> mcspi1 */
5107 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5108         .master         = &omap44xx_l4_per_hwmod,
5109         .slave          = &omap44xx_mcspi1_hwmod,
5110         .clk            = "l4_div_ck",
5111         .addr           = omap44xx_mcspi1_addrs,
5112         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5113 };
5114
5115 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5116         {
5117                 .pa_start       = 0x4809a000,
5118                 .pa_end         = 0x4809a1ff,
5119                 .flags          = ADDR_TYPE_RT
5120         },
5121         { }
5122 };
5123
5124 /* l4_per -> mcspi2 */
5125 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5126         .master         = &omap44xx_l4_per_hwmod,
5127         .slave          = &omap44xx_mcspi2_hwmod,
5128         .clk            = "l4_div_ck",
5129         .addr           = omap44xx_mcspi2_addrs,
5130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5131 };
5132
5133 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5134         {
5135                 .pa_start       = 0x480b8000,
5136                 .pa_end         = 0x480b81ff,
5137                 .flags          = ADDR_TYPE_RT
5138         },
5139         { }
5140 };
5141
5142 /* l4_per -> mcspi3 */
5143 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5144         .master         = &omap44xx_l4_per_hwmod,
5145         .slave          = &omap44xx_mcspi3_hwmod,
5146         .clk            = "l4_div_ck",
5147         .addr           = omap44xx_mcspi3_addrs,
5148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5149 };
5150
5151 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5152         {
5153                 .pa_start       = 0x480ba000,
5154                 .pa_end         = 0x480ba1ff,
5155                 .flags          = ADDR_TYPE_RT
5156         },
5157         { }
5158 };
5159
5160 /* l4_per -> mcspi4 */
5161 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5162         .master         = &omap44xx_l4_per_hwmod,
5163         .slave          = &omap44xx_mcspi4_hwmod,
5164         .clk            = "l4_div_ck",
5165         .addr           = omap44xx_mcspi4_addrs,
5166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5167 };
5168
5169 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5170         {
5171                 .pa_start       = 0x4809c000,
5172                 .pa_end         = 0x4809c3ff,
5173                 .flags          = ADDR_TYPE_RT
5174         },
5175         { }
5176 };
5177
5178 /* l4_per -> mmc1 */
5179 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5180         .master         = &omap44xx_l4_per_hwmod,
5181         .slave          = &omap44xx_mmc1_hwmod,
5182         .clk            = "l4_div_ck",
5183         .addr           = omap44xx_mmc1_addrs,
5184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5185 };
5186
5187 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5188         {
5189                 .pa_start       = 0x480b4000,
5190                 .pa_end         = 0x480b43ff,
5191                 .flags          = ADDR_TYPE_RT
5192         },
5193         { }
5194 };
5195
5196 /* l4_per -> mmc2 */
5197 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5198         .master         = &omap44xx_l4_per_hwmod,
5199         .slave          = &omap44xx_mmc2_hwmod,
5200         .clk            = "l4_div_ck",
5201         .addr           = omap44xx_mmc2_addrs,
5202         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5203 };
5204
5205 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5206         {
5207                 .pa_start       = 0x480ad000,
5208                 .pa_end         = 0x480ad3ff,
5209                 .flags          = ADDR_TYPE_RT
5210         },
5211         { }
5212 };
5213
5214 /* l4_per -> mmc3 */
5215 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5216         .master         = &omap44xx_l4_per_hwmod,
5217         .slave          = &omap44xx_mmc3_hwmod,
5218         .clk            = "l4_div_ck",
5219         .addr           = omap44xx_mmc3_addrs,
5220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5221 };
5222
5223 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5224         {
5225                 .pa_start       = 0x480d1000,
5226                 .pa_end         = 0x480d13ff,
5227                 .flags          = ADDR_TYPE_RT
5228         },
5229         { }
5230 };
5231
5232 /* l4_per -> mmc4 */
5233 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5234         .master         = &omap44xx_l4_per_hwmod,
5235         .slave          = &omap44xx_mmc4_hwmod,
5236         .clk            = "l4_div_ck",
5237         .addr           = omap44xx_mmc4_addrs,
5238         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5239 };
5240
5241 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5242         {
5243                 .pa_start       = 0x480d5000,
5244                 .pa_end         = 0x480d53ff,
5245                 .flags          = ADDR_TYPE_RT
5246         },
5247         { }
5248 };
5249
5250 /* l4_per -> mmc5 */
5251 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5252         .master         = &omap44xx_l4_per_hwmod,
5253         .slave          = &omap44xx_mmc5_hwmod,
5254         .clk            = "l4_div_ck",
5255         .addr           = omap44xx_mmc5_addrs,
5256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5257 };
5258
5259 /* l3_main_2 -> ocmc_ram */
5260 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5261         .master         = &omap44xx_l3_main_2_hwmod,
5262         .slave          = &omap44xx_ocmc_ram_hwmod,
5263         .clk            = "l3_div_ck",
5264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5265 };
5266
5267 /* l4_cfg -> ocp2scp_usb_phy */
5268 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5269         .master         = &omap44xx_l4_cfg_hwmod,
5270         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5271         .clk            = "l4_div_ck",
5272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5273 };
5274
5275 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5276         {
5277                 .pa_start       = 0x48243000,
5278                 .pa_end         = 0x48243fff,
5279                 .flags          = ADDR_TYPE_RT
5280         },
5281         { }
5282 };
5283
5284 /* mpu_private -> prcm_mpu */
5285 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5286         .master         = &omap44xx_mpu_private_hwmod,
5287         .slave          = &omap44xx_prcm_mpu_hwmod,
5288         .clk            = "l3_div_ck",
5289         .addr           = omap44xx_prcm_mpu_addrs,
5290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5291 };
5292
5293 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5294         {
5295                 .pa_start       = 0x4a004000,
5296                 .pa_end         = 0x4a004fff,
5297                 .flags          = ADDR_TYPE_RT
5298         },
5299         { }
5300 };
5301
5302 /* l4_wkup -> cm_core_aon */
5303 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5304         .master         = &omap44xx_l4_wkup_hwmod,
5305         .slave          = &omap44xx_cm_core_aon_hwmod,
5306         .clk            = "l4_wkup_clk_mux_ck",
5307         .addr           = omap44xx_cm_core_aon_addrs,
5308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5309 };
5310
5311 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5312         {
5313                 .pa_start       = 0x4a008000,
5314                 .pa_end         = 0x4a009fff,
5315                 .flags          = ADDR_TYPE_RT
5316         },
5317         { }
5318 };
5319
5320 /* l4_cfg -> cm_core */
5321 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5322         .master         = &omap44xx_l4_cfg_hwmod,
5323         .slave          = &omap44xx_cm_core_hwmod,
5324         .clk            = "l4_div_ck",
5325         .addr           = omap44xx_cm_core_addrs,
5326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5327 };
5328
5329 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5330         {
5331                 .pa_start       = 0x4a306000,
5332                 .pa_end         = 0x4a307fff,
5333                 .flags          = ADDR_TYPE_RT
5334         },
5335         { }
5336 };
5337
5338 /* l4_wkup -> prm */
5339 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5340         .master         = &omap44xx_l4_wkup_hwmod,
5341         .slave          = &omap44xx_prm_hwmod,
5342         .clk            = "l4_wkup_clk_mux_ck",
5343         .addr           = omap44xx_prm_addrs,
5344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5345 };
5346
5347 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5348         {
5349                 .pa_start       = 0x4a30a000,
5350                 .pa_end         = 0x4a30a7ff,
5351                 .flags          = ADDR_TYPE_RT
5352         },
5353         { }
5354 };
5355
5356 /* l4_wkup -> scrm */
5357 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5358         .master         = &omap44xx_l4_wkup_hwmod,
5359         .slave          = &omap44xx_scrm_hwmod,
5360         .clk            = "l4_wkup_clk_mux_ck",
5361         .addr           = omap44xx_scrm_addrs,
5362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5363 };
5364
5365 /* l3_main_2 -> sl2if */
5366 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5367         .master         = &omap44xx_l3_main_2_hwmod,
5368         .slave          = &omap44xx_sl2if_hwmod,
5369         .clk            = "l3_div_ck",
5370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5371 };
5372
5373 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5374         {
5375                 .pa_start       = 0x4012c000,
5376                 .pa_end         = 0x4012c3ff,
5377                 .flags          = ADDR_TYPE_RT
5378         },
5379         { }
5380 };
5381
5382 /* l4_abe -> slimbus1 */
5383 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5384         .master         = &omap44xx_l4_abe_hwmod,
5385         .slave          = &omap44xx_slimbus1_hwmod,
5386         .clk            = "ocp_abe_iclk",
5387         .addr           = omap44xx_slimbus1_addrs,
5388         .user           = OCP_USER_MPU,
5389 };
5390
5391 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5392         {
5393                 .pa_start       = 0x4902c000,
5394                 .pa_end         = 0x4902c3ff,
5395                 .flags          = ADDR_TYPE_RT
5396         },
5397         { }
5398 };
5399
5400 /* l4_abe -> slimbus1 (dma) */
5401 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5402         .master         = &omap44xx_l4_abe_hwmod,
5403         .slave          = &omap44xx_slimbus1_hwmod,
5404         .clk            = "ocp_abe_iclk",
5405         .addr           = omap44xx_slimbus1_dma_addrs,
5406         .user           = OCP_USER_SDMA,
5407 };
5408
5409 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5410         {
5411                 .pa_start       = 0x48076000,
5412                 .pa_end         = 0x480763ff,
5413                 .flags          = ADDR_TYPE_RT
5414         },
5415         { }
5416 };
5417
5418 /* l4_per -> slimbus2 */
5419 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5420         .master         = &omap44xx_l4_per_hwmod,
5421         .slave          = &omap44xx_slimbus2_hwmod,
5422         .clk            = "l4_div_ck",
5423         .addr           = omap44xx_slimbus2_addrs,
5424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5425 };
5426
5427 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5428         {
5429                 .pa_start       = 0x4a0dd000,
5430                 .pa_end         = 0x4a0dd03f,
5431                 .flags          = ADDR_TYPE_RT
5432         },
5433         { }
5434 };
5435
5436 /* l4_cfg -> smartreflex_core */
5437 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5438         .master         = &omap44xx_l4_cfg_hwmod,
5439         .slave          = &omap44xx_smartreflex_core_hwmod,
5440         .clk            = "l4_div_ck",
5441         .addr           = omap44xx_smartreflex_core_addrs,
5442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5443 };
5444
5445 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5446         {
5447                 .pa_start       = 0x4a0db000,
5448                 .pa_end         = 0x4a0db03f,
5449                 .flags          = ADDR_TYPE_RT
5450         },
5451         { }
5452 };
5453
5454 /* l4_cfg -> smartreflex_iva */
5455 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5456         .master         = &omap44xx_l4_cfg_hwmod,
5457         .slave          = &omap44xx_smartreflex_iva_hwmod,
5458         .clk            = "l4_div_ck",
5459         .addr           = omap44xx_smartreflex_iva_addrs,
5460         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5461 };
5462
5463 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5464         {
5465                 .pa_start       = 0x4a0d9000,
5466                 .pa_end         = 0x4a0d903f,
5467                 .flags          = ADDR_TYPE_RT
5468         },
5469         { }
5470 };
5471
5472 /* l4_cfg -> smartreflex_mpu */
5473 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5474         .master         = &omap44xx_l4_cfg_hwmod,
5475         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5476         .clk            = "l4_div_ck",
5477         .addr           = omap44xx_smartreflex_mpu_addrs,
5478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5479 };
5480
5481 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5482         {
5483                 .pa_start       = 0x4a0f6000,
5484                 .pa_end         = 0x4a0f6fff,
5485                 .flags          = ADDR_TYPE_RT
5486         },
5487         { }
5488 };
5489
5490 /* l4_cfg -> spinlock */
5491 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5492         .master         = &omap44xx_l4_cfg_hwmod,
5493         .slave          = &omap44xx_spinlock_hwmod,
5494         .clk            = "l4_div_ck",
5495         .addr           = omap44xx_spinlock_addrs,
5496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5497 };
5498
5499 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5500         {
5501                 .pa_start       = 0x4a318000,
5502                 .pa_end         = 0x4a31807f,
5503                 .flags          = ADDR_TYPE_RT
5504         },
5505         { }
5506 };
5507
5508 /* l4_wkup -> timer1 */
5509 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5510         .master         = &omap44xx_l4_wkup_hwmod,
5511         .slave          = &omap44xx_timer1_hwmod,
5512         .clk            = "l4_wkup_clk_mux_ck",
5513         .addr           = omap44xx_timer1_addrs,
5514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5515 };
5516
5517 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5518         {
5519                 .pa_start       = 0x48032000,
5520                 .pa_end         = 0x4803207f,
5521                 .flags          = ADDR_TYPE_RT
5522         },
5523         { }
5524 };
5525
5526 /* l4_per -> timer2 */
5527 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5528         .master         = &omap44xx_l4_per_hwmod,
5529         .slave          = &omap44xx_timer2_hwmod,
5530         .clk            = "l4_div_ck",
5531         .addr           = omap44xx_timer2_addrs,
5532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5533 };
5534
5535 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5536         {
5537                 .pa_start       = 0x48034000,
5538                 .pa_end         = 0x4803407f,
5539                 .flags          = ADDR_TYPE_RT
5540         },
5541         { }
5542 };
5543
5544 /* l4_per -> timer3 */
5545 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5546         .master         = &omap44xx_l4_per_hwmod,
5547         .slave          = &omap44xx_timer3_hwmod,
5548         .clk            = "l4_div_ck",
5549         .addr           = omap44xx_timer3_addrs,
5550         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5551 };
5552
5553 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5554         {
5555                 .pa_start       = 0x48036000,
5556                 .pa_end         = 0x4803607f,
5557                 .flags          = ADDR_TYPE_RT
5558         },
5559         { }
5560 };
5561
5562 /* l4_per -> timer4 */
5563 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5564         .master         = &omap44xx_l4_per_hwmod,
5565         .slave          = &omap44xx_timer4_hwmod,
5566         .clk            = "l4_div_ck",
5567         .addr           = omap44xx_timer4_addrs,
5568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5569 };
5570
5571 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5572         {
5573                 .pa_start       = 0x40138000,
5574                 .pa_end         = 0x4013807f,
5575                 .flags          = ADDR_TYPE_RT
5576         },
5577         { }
5578 };
5579
5580 /* l4_abe -> timer5 */
5581 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5582         .master         = &omap44xx_l4_abe_hwmod,
5583         .slave          = &omap44xx_timer5_hwmod,
5584         .clk            = "ocp_abe_iclk",
5585         .addr           = omap44xx_timer5_addrs,
5586         .user           = OCP_USER_MPU,
5587 };
5588
5589 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5590         {
5591                 .pa_start       = 0x49038000,
5592                 .pa_end         = 0x4903807f,
5593                 .flags          = ADDR_TYPE_RT
5594         },
5595         { }
5596 };
5597
5598 /* l4_abe -> timer5 (dma) */
5599 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5600         .master         = &omap44xx_l4_abe_hwmod,
5601         .slave          = &omap44xx_timer5_hwmod,
5602         .clk            = "ocp_abe_iclk",
5603         .addr           = omap44xx_timer5_dma_addrs,
5604         .user           = OCP_USER_SDMA,
5605 };
5606
5607 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5608         {
5609                 .pa_start       = 0x4013a000,
5610                 .pa_end         = 0x4013a07f,
5611                 .flags          = ADDR_TYPE_RT
5612         },
5613         { }
5614 };
5615
5616 /* l4_abe -> timer6 */
5617 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5618         .master         = &omap44xx_l4_abe_hwmod,
5619         .slave          = &omap44xx_timer6_hwmod,
5620         .clk            = "ocp_abe_iclk",
5621         .addr           = omap44xx_timer6_addrs,
5622         .user           = OCP_USER_MPU,
5623 };
5624
5625 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5626         {
5627                 .pa_start       = 0x4903a000,
5628                 .pa_end         = 0x4903a07f,
5629                 .flags          = ADDR_TYPE_RT
5630         },
5631         { }
5632 };
5633
5634 /* l4_abe -> timer6 (dma) */
5635 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5636         .master         = &omap44xx_l4_abe_hwmod,
5637         .slave          = &omap44xx_timer6_hwmod,
5638         .clk            = "ocp_abe_iclk",
5639         .addr           = omap44xx_timer6_dma_addrs,
5640         .user           = OCP_USER_SDMA,
5641 };
5642
5643 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5644         {
5645                 .pa_start       = 0x4013c000,
5646                 .pa_end         = 0x4013c07f,
5647                 .flags          = ADDR_TYPE_RT
5648         },
5649         { }
5650 };
5651
5652 /* l4_abe -> timer7 */
5653 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5654         .master         = &omap44xx_l4_abe_hwmod,
5655         .slave          = &omap44xx_timer7_hwmod,
5656         .clk            = "ocp_abe_iclk",
5657         .addr           = omap44xx_timer7_addrs,
5658         .user           = OCP_USER_MPU,
5659 };
5660
5661 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5662         {
5663                 .pa_start       = 0x4903c000,
5664                 .pa_end         = 0x4903c07f,
5665                 .flags          = ADDR_TYPE_RT
5666         },
5667         { }
5668 };
5669
5670 /* l4_abe -> timer7 (dma) */
5671 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5672         .master         = &omap44xx_l4_abe_hwmod,
5673         .slave          = &omap44xx_timer7_hwmod,
5674         .clk            = "ocp_abe_iclk",
5675         .addr           = omap44xx_timer7_dma_addrs,
5676         .user           = OCP_USER_SDMA,
5677 };
5678
5679 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5680         {
5681                 .pa_start       = 0x4013e000,
5682                 .pa_end         = 0x4013e07f,
5683                 .flags          = ADDR_TYPE_RT
5684         },
5685         { }
5686 };
5687
5688 /* l4_abe -> timer8 */
5689 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5690         .master         = &omap44xx_l4_abe_hwmod,
5691         .slave          = &omap44xx_timer8_hwmod,
5692         .clk            = "ocp_abe_iclk",
5693         .addr           = omap44xx_timer8_addrs,
5694         .user           = OCP_USER_MPU,
5695 };
5696
5697 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5698         {
5699                 .pa_start       = 0x4903e000,
5700                 .pa_end         = 0x4903e07f,
5701                 .flags          = ADDR_TYPE_RT
5702         },
5703         { }
5704 };
5705
5706 /* l4_abe -> timer8 (dma) */
5707 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5708         .master         = &omap44xx_l4_abe_hwmod,
5709         .slave          = &omap44xx_timer8_hwmod,
5710         .clk            = "ocp_abe_iclk",
5711         .addr           = omap44xx_timer8_dma_addrs,
5712         .user           = OCP_USER_SDMA,
5713 };
5714
5715 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5716         {
5717                 .pa_start       = 0x4803e000,
5718                 .pa_end         = 0x4803e07f,
5719                 .flags          = ADDR_TYPE_RT
5720         },
5721         { }
5722 };
5723
5724 /* l4_per -> timer9 */
5725 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5726         .master         = &omap44xx_l4_per_hwmod,
5727         .slave          = &omap44xx_timer9_hwmod,
5728         .clk            = "l4_div_ck",
5729         .addr           = omap44xx_timer9_addrs,
5730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5731 };
5732
5733 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5734         {
5735                 .pa_start       = 0x48086000,
5736                 .pa_end         = 0x4808607f,
5737                 .flags          = ADDR_TYPE_RT
5738         },
5739         { }
5740 };
5741
5742 /* l4_per -> timer10 */
5743 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5744         .master         = &omap44xx_l4_per_hwmod,
5745         .slave          = &omap44xx_timer10_hwmod,
5746         .clk            = "l4_div_ck",
5747         .addr           = omap44xx_timer10_addrs,
5748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5749 };
5750
5751 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5752         {
5753                 .pa_start       = 0x48088000,
5754                 .pa_end         = 0x4808807f,
5755                 .flags          = ADDR_TYPE_RT
5756         },
5757         { }
5758 };
5759
5760 /* l4_per -> timer11 */
5761 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5762         .master         = &omap44xx_l4_per_hwmod,
5763         .slave          = &omap44xx_timer11_hwmod,
5764         .clk            = "l4_div_ck",
5765         .addr           = omap44xx_timer11_addrs,
5766         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5767 };
5768
5769 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5770         {
5771                 .pa_start       = 0x4806a000,
5772                 .pa_end         = 0x4806a0ff,
5773                 .flags          = ADDR_TYPE_RT
5774         },
5775         { }
5776 };
5777
5778 /* l4_per -> uart1 */
5779 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5780         .master         = &omap44xx_l4_per_hwmod,
5781         .slave          = &omap44xx_uart1_hwmod,
5782         .clk            = "l4_div_ck",
5783         .addr           = omap44xx_uart1_addrs,
5784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5785 };
5786
5787 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5788         {
5789                 .pa_start       = 0x4806c000,
5790                 .pa_end         = 0x4806c0ff,
5791                 .flags          = ADDR_TYPE_RT
5792         },
5793         { }
5794 };
5795
5796 /* l4_per -> uart2 */
5797 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5798         .master         = &omap44xx_l4_per_hwmod,
5799         .slave          = &omap44xx_uart2_hwmod,
5800         .clk            = "l4_div_ck",
5801         .addr           = omap44xx_uart2_addrs,
5802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5803 };
5804
5805 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5806         {
5807                 .pa_start       = 0x48020000,
5808                 .pa_end         = 0x480200ff,
5809                 .flags          = ADDR_TYPE_RT
5810         },
5811         { }
5812 };
5813
5814 /* l4_per -> uart3 */
5815 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5816         .master         = &omap44xx_l4_per_hwmod,
5817         .slave          = &omap44xx_uart3_hwmod,
5818         .clk            = "l4_div_ck",
5819         .addr           = omap44xx_uart3_addrs,
5820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5821 };
5822
5823 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5824         {
5825                 .pa_start       = 0x4806e000,
5826                 .pa_end         = 0x4806e0ff,
5827                 .flags          = ADDR_TYPE_RT
5828         },
5829         { }
5830 };
5831
5832 /* l4_per -> uart4 */
5833 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5834         .master         = &omap44xx_l4_per_hwmod,
5835         .slave          = &omap44xx_uart4_hwmod,
5836         .clk            = "l4_div_ck",
5837         .addr           = omap44xx_uart4_addrs,
5838         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5839 };
5840
5841 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5842         {
5843                 .pa_start       = 0x4a0a9000,
5844                 .pa_end         = 0x4a0a93ff,
5845                 .flags          = ADDR_TYPE_RT
5846         },
5847         { }
5848 };
5849
5850 /* l4_cfg -> usb_host_fs */
5851 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
5852         .master         = &omap44xx_l4_cfg_hwmod,
5853         .slave          = &omap44xx_usb_host_fs_hwmod,
5854         .clk            = "l4_div_ck",
5855         .addr           = omap44xx_usb_host_fs_addrs,
5856         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5857 };
5858
5859 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5860         {
5861                 .name           = "uhh",
5862                 .pa_start       = 0x4a064000,
5863                 .pa_end         = 0x4a0647ff,
5864                 .flags          = ADDR_TYPE_RT
5865         },
5866         {
5867                 .name           = "ohci",
5868                 .pa_start       = 0x4a064800,
5869                 .pa_end         = 0x4a064bff,
5870         },
5871         {
5872                 .name           = "ehci",
5873                 .pa_start       = 0x4a064c00,
5874                 .pa_end         = 0x4a064fff,
5875         },
5876         {}
5877 };
5878
5879 /* l4_cfg -> usb_host_hs */
5880 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5881         .master         = &omap44xx_l4_cfg_hwmod,
5882         .slave          = &omap44xx_usb_host_hs_hwmod,
5883         .clk            = "l4_div_ck",
5884         .addr           = omap44xx_usb_host_hs_addrs,
5885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5886 };
5887
5888 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5889         {
5890                 .pa_start       = 0x4a0ab000,
5891                 .pa_end         = 0x4a0ab003,
5892                 .flags          = ADDR_TYPE_RT
5893         },
5894         { }
5895 };
5896
5897 /* l4_cfg -> usb_otg_hs */
5898 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5899         .master         = &omap44xx_l4_cfg_hwmod,
5900         .slave          = &omap44xx_usb_otg_hs_hwmod,
5901         .clk            = "l4_div_ck",
5902         .addr           = omap44xx_usb_otg_hs_addrs,
5903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5904 };
5905
5906 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5907         {
5908                 .name           = "tll",
5909                 .pa_start       = 0x4a062000,
5910                 .pa_end         = 0x4a063fff,
5911                 .flags          = ADDR_TYPE_RT
5912         },
5913         {}
5914 };
5915
5916 /* l4_cfg -> usb_tll_hs */
5917 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5918         .master         = &omap44xx_l4_cfg_hwmod,
5919         .slave          = &omap44xx_usb_tll_hs_hwmod,
5920         .clk            = "l4_div_ck",
5921         .addr           = omap44xx_usb_tll_hs_addrs,
5922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5923 };
5924
5925 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5926         {
5927                 .pa_start       = 0x4a314000,
5928                 .pa_end         = 0x4a31407f,
5929                 .flags          = ADDR_TYPE_RT
5930         },
5931         { }
5932 };
5933
5934 /* l4_wkup -> wd_timer2 */
5935 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5936         .master         = &omap44xx_l4_wkup_hwmod,
5937         .slave          = &omap44xx_wd_timer2_hwmod,
5938         .clk            = "l4_wkup_clk_mux_ck",
5939         .addr           = omap44xx_wd_timer2_addrs,
5940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5941 };
5942
5943 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5944         {
5945                 .pa_start       = 0x40130000,
5946                 .pa_end         = 0x4013007f,
5947                 .flags          = ADDR_TYPE_RT
5948         },
5949         { }
5950 };
5951
5952 /* l4_abe -> wd_timer3 */
5953 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5954         .master         = &omap44xx_l4_abe_hwmod,
5955         .slave          = &omap44xx_wd_timer3_hwmod,
5956         .clk            = "ocp_abe_iclk",
5957         .addr           = omap44xx_wd_timer3_addrs,
5958         .user           = OCP_USER_MPU,
5959 };
5960
5961 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5962         {
5963                 .pa_start       = 0x49030000,
5964                 .pa_end         = 0x4903007f,
5965                 .flags          = ADDR_TYPE_RT
5966         },
5967         { }
5968 };
5969
5970 /* l4_abe -> wd_timer3 (dma) */
5971 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5972         .master         = &omap44xx_l4_abe_hwmod,
5973         .slave          = &omap44xx_wd_timer3_hwmod,
5974         .clk            = "ocp_abe_iclk",
5975         .addr           = omap44xx_wd_timer3_dma_addrs,
5976         .user           = OCP_USER_SDMA,
5977 };
5978
5979 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5980         &omap44xx_c2c__c2c_target_fw,
5981         &omap44xx_l4_cfg__c2c_target_fw,
5982         &omap44xx_l3_main_1__dmm,
5983         &omap44xx_mpu__dmm,
5984         &omap44xx_c2c__emif_fw,
5985         &omap44xx_dmm__emif_fw,
5986         &omap44xx_l4_cfg__emif_fw,
5987         &omap44xx_iva__l3_instr,
5988         &omap44xx_l3_main_3__l3_instr,
5989         &omap44xx_ocp_wp_noc__l3_instr,
5990         &omap44xx_dsp__l3_main_1,
5991         &omap44xx_dss__l3_main_1,
5992         &omap44xx_l3_main_2__l3_main_1,
5993         &omap44xx_l4_cfg__l3_main_1,
5994         &omap44xx_mmc1__l3_main_1,
5995         &omap44xx_mmc2__l3_main_1,
5996         &omap44xx_mpu__l3_main_1,
5997         &omap44xx_c2c_target_fw__l3_main_2,
5998         &omap44xx_debugss__l3_main_2,
5999         &omap44xx_dma_system__l3_main_2,
6000         &omap44xx_fdif__l3_main_2,
6001         &omap44xx_gpu__l3_main_2,
6002         &omap44xx_hsi__l3_main_2,
6003         &omap44xx_ipu__l3_main_2,
6004         &omap44xx_iss__l3_main_2,
6005         &omap44xx_iva__l3_main_2,
6006         &omap44xx_l3_main_1__l3_main_2,
6007         &omap44xx_l4_cfg__l3_main_2,
6008         &omap44xx_usb_host_fs__l3_main_2,
6009         &omap44xx_usb_host_hs__l3_main_2,
6010         &omap44xx_usb_otg_hs__l3_main_2,
6011         &omap44xx_l3_main_1__l3_main_3,
6012         &omap44xx_l3_main_2__l3_main_3,
6013         &omap44xx_l4_cfg__l3_main_3,
6014         &omap44xx_aess__l4_abe,
6015         &omap44xx_dsp__l4_abe,
6016         &omap44xx_l3_main_1__l4_abe,
6017         &omap44xx_mpu__l4_abe,
6018         &omap44xx_l3_main_1__l4_cfg,
6019         &omap44xx_l3_main_2__l4_per,
6020         &omap44xx_l4_cfg__l4_wkup,
6021         &omap44xx_mpu__mpu_private,
6022         &omap44xx_l4_cfg__ocp_wp_noc,
6023         &omap44xx_l4_abe__aess,
6024         &omap44xx_l4_abe__aess_dma,
6025         &omap44xx_l3_main_2__c2c,
6026         &omap44xx_l4_wkup__counter_32k,
6027         &omap44xx_l4_cfg__ctrl_module_core,
6028         &omap44xx_l4_cfg__ctrl_module_pad_core,
6029         &omap44xx_l4_wkup__ctrl_module_wkup,
6030         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6031         &omap44xx_l3_instr__debugss,
6032         &omap44xx_l4_cfg__dma_system,
6033         &omap44xx_l4_abe__dmic,
6034         &omap44xx_l4_abe__dmic_dma,
6035         &omap44xx_dsp__iva,
6036         &omap44xx_dsp__sl2if,
6037         &omap44xx_l4_cfg__dsp,
6038         &omap44xx_l3_main_2__dss,
6039         &omap44xx_l4_per__dss,
6040         &omap44xx_l3_main_2__dss_dispc,
6041         &omap44xx_l4_per__dss_dispc,
6042         &omap44xx_l3_main_2__dss_dsi1,
6043         &omap44xx_l4_per__dss_dsi1,
6044         &omap44xx_l3_main_2__dss_dsi2,
6045         &omap44xx_l4_per__dss_dsi2,
6046         &omap44xx_l3_main_2__dss_hdmi,
6047         &omap44xx_l4_per__dss_hdmi,
6048         &omap44xx_l3_main_2__dss_rfbi,
6049         &omap44xx_l4_per__dss_rfbi,
6050         &omap44xx_l3_main_2__dss_venc,
6051         &omap44xx_l4_per__dss_venc,
6052         &omap44xx_l4_per__elm,
6053         &omap44xx_emif_fw__emif1,
6054         &omap44xx_emif_fw__emif2,
6055         &omap44xx_l4_cfg__fdif,
6056         &omap44xx_l4_wkup__gpio1,
6057         &omap44xx_l4_per__gpio2,
6058         &omap44xx_l4_per__gpio3,
6059         &omap44xx_l4_per__gpio4,
6060         &omap44xx_l4_per__gpio5,
6061         &omap44xx_l4_per__gpio6,
6062         &omap44xx_l3_main_2__gpmc,
6063         &omap44xx_l3_main_2__gpu,
6064         &omap44xx_l4_per__hdq1w,
6065         &omap44xx_l4_cfg__hsi,
6066         &omap44xx_l4_per__i2c1,
6067         &omap44xx_l4_per__i2c2,
6068         &omap44xx_l4_per__i2c3,
6069         &omap44xx_l4_per__i2c4,
6070         &omap44xx_l3_main_2__ipu,
6071         &omap44xx_l3_main_2__iss,
6072         &omap44xx_iva__sl2if,
6073         &omap44xx_l3_main_2__iva,
6074         &omap44xx_l4_wkup__kbd,
6075         &omap44xx_l4_cfg__mailbox,
6076         &omap44xx_l4_abe__mcasp,
6077         &omap44xx_l4_abe__mcasp_dma,
6078         &omap44xx_l4_abe__mcbsp1,
6079         &omap44xx_l4_abe__mcbsp1_dma,
6080         &omap44xx_l4_abe__mcbsp2,
6081         &omap44xx_l4_abe__mcbsp2_dma,
6082         &omap44xx_l4_abe__mcbsp3,
6083         &omap44xx_l4_abe__mcbsp3_dma,
6084         &omap44xx_l4_per__mcbsp4,
6085         &omap44xx_l4_abe__mcpdm,
6086         &omap44xx_l4_abe__mcpdm_dma,
6087         &omap44xx_l4_per__mcspi1,
6088         &omap44xx_l4_per__mcspi2,
6089         &omap44xx_l4_per__mcspi3,
6090         &omap44xx_l4_per__mcspi4,
6091         &omap44xx_l4_per__mmc1,
6092         &omap44xx_l4_per__mmc2,
6093         &omap44xx_l4_per__mmc3,
6094         &omap44xx_l4_per__mmc4,
6095         &omap44xx_l4_per__mmc5,
6096         &omap44xx_l3_main_2__ocmc_ram,
6097         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6098         &omap44xx_mpu_private__prcm_mpu,
6099         &omap44xx_l4_wkup__cm_core_aon,
6100         &omap44xx_l4_cfg__cm_core,
6101         &omap44xx_l4_wkup__prm,
6102         &omap44xx_l4_wkup__scrm,
6103         &omap44xx_l3_main_2__sl2if,
6104         &omap44xx_l4_abe__slimbus1,
6105         &omap44xx_l4_abe__slimbus1_dma,
6106         &omap44xx_l4_per__slimbus2,
6107         &omap44xx_l4_cfg__smartreflex_core,
6108         &omap44xx_l4_cfg__smartreflex_iva,
6109         &omap44xx_l4_cfg__smartreflex_mpu,
6110         &omap44xx_l4_cfg__spinlock,
6111         &omap44xx_l4_wkup__timer1,
6112         &omap44xx_l4_per__timer2,
6113         &omap44xx_l4_per__timer3,
6114         &omap44xx_l4_per__timer4,
6115         &omap44xx_l4_abe__timer5,
6116         &omap44xx_l4_abe__timer5_dma,
6117         &omap44xx_l4_abe__timer6,
6118         &omap44xx_l4_abe__timer6_dma,
6119         &omap44xx_l4_abe__timer7,
6120         &omap44xx_l4_abe__timer7_dma,
6121         &omap44xx_l4_abe__timer8,
6122         &omap44xx_l4_abe__timer8_dma,
6123         &omap44xx_l4_per__timer9,
6124         &omap44xx_l4_per__timer10,
6125         &omap44xx_l4_per__timer11,
6126         &omap44xx_l4_per__uart1,
6127         &omap44xx_l4_per__uart2,
6128         &omap44xx_l4_per__uart3,
6129         &omap44xx_l4_per__uart4,
6130         &omap44xx_l4_cfg__usb_host_fs,
6131         &omap44xx_l4_cfg__usb_host_hs,
6132         &omap44xx_l4_cfg__usb_otg_hs,
6133         &omap44xx_l4_cfg__usb_tll_hs,
6134         &omap44xx_l4_wkup__wd_timer2,
6135         &omap44xx_l4_abe__wd_timer3,
6136         &omap44xx_l4_abe__wd_timer3_dma,
6137         NULL,
6138 };
6139
6140 int __init omap44xx_hwmod_init(void)
6141 {
6142         omap_hwmod_init();
6143         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6144 }
6145