Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24
  25 #include <plat/omap_hwmod.h>
  26 #include <plat/i2c.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "wd_timer.h"
  40
  41 /* Base offset for all OMAP4 interrupts external to MPUSS */
  42 #define OMAP44XX_IRQ_GIC_START  32
  43
  44 /* Base offset for all OMAP4 dma requests */
  45 #define OMAP44XX_DMA_REQ_START  1
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'c2c_target_fw' class
  53  * instance(s): c2c_target_fw
  54  */
  55 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  56         .name   = "c2c_target_fw",
  57 };
  58
  59 /* c2c_target_fw */
  60 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  61         .name           = "c2c_target_fw",
  62         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  63         .clkdm_name     = "d2d_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  67                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'dmm' class
  74  * instance(s): dmm
  75  */
  76 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  77         .name   = "dmm",
  78 };
  79
  80 /* dmm */
  81 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  82         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  83         { .irq = -1 }
  84 };
  85
  86 static struct omap_hwmod omap44xx_dmm_hwmod = {
  87         .name           = "dmm",
  88         .class          = &omap44xx_dmm_hwmod_class,
  89         .clkdm_name     = "l3_emif_clkdm",
  90         .mpu_irqs       = omap44xx_dmm_irqs,
  91         .prcm = {
  92                 .omap4 = {
  93                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  94                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  95                 },
  96         },
  97 };
  98
  99 /*
 100  * 'emif_fw' class
 101  * instance(s): emif_fw
 102  */
 103 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 104         .name   = "emif_fw",
 105 };
 106
 107 /* emif_fw */
 108 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 109         .name           = "emif_fw",
 110         .class          = &omap44xx_emif_fw_hwmod_class,
 111         .clkdm_name     = "l3_emif_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 115                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 116                 },
 117         },
 118 };
 119
 120 /*
 121  * 'l3' class
 122  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 123  */
 124 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 125         .name   = "l3",
 126 };
 127
 128 /* l3_instr */
 129 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 130         .name           = "l3_instr",
 131         .class          = &omap44xx_l3_hwmod_class,
 132         .clkdm_name     = "l3_instr_clkdm",
 133         .prcm = {
 134                 .omap4 = {
 135                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 136                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 137                         .modulemode   = MODULEMODE_HWCTRL,
 138                 },
 139         },
 140 };
 141
 142 /* l3_main_1 */
 143 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 144         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 145         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 146         { .irq = -1 }
 147 };
 148
 149 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 150         .name           = "l3_main_1",
 151         .class          = &omap44xx_l3_hwmod_class,
 152         .clkdm_name     = "l3_1_clkdm",
 153         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 154         .prcm = {
 155                 .omap4 = {
 156                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 157                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 158                 },
 159         },
 160 };
 161
 162 /* l3_main_2 */
 163 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 164         .name           = "l3_main_2",
 165         .class          = &omap44xx_l3_hwmod_class,
 166         .clkdm_name     = "l3_2_clkdm",
 167         .prcm = {
 168                 .omap4 = {
 169                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 170                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 171                 },
 172         },
 173 };
 174
 175 /* l3_main_3 */
 176 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 177         .name           = "l3_main_3",
 178         .class          = &omap44xx_l3_hwmod_class,
 179         .clkdm_name     = "l3_instr_clkdm",
 180         .prcm = {
 181                 .omap4 = {
 182                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 183                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 184                         .modulemode   = MODULEMODE_HWCTRL,
 185                 },
 186         },
 187 };
 188
 189 /*
 190  * 'l4' class
 191  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 192  */
 193 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 194         .name   = "l4",
 195 };
 196
 197 /* l4_abe */
 198 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 199         .name           = "l4_abe",
 200         .class          = &omap44xx_l4_hwmod_class,
 201         .clkdm_name     = "abe_clkdm",
 202         .prcm = {
 203                 .omap4 = {
 204                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 205                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 206                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 207                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 208                 },
 209         },
 210 };
 211
 212 /* l4_cfg */
 213 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 214         .name           = "l4_cfg",
 215         .class          = &omap44xx_l4_hwmod_class,
 216         .clkdm_name     = "l4_cfg_clkdm",
 217         .prcm = {
 218                 .omap4 = {
 219                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 220                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 221                 },
 222         },
 223 };
 224
 225 /* l4_per */
 226 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 227         .name           = "l4_per",
 228         .class          = &omap44xx_l4_hwmod_class,
 229         .clkdm_name     = "l4_per_clkdm",
 230         .prcm = {
 231                 .omap4 = {
 232                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 233                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 234                 },
 235         },
 236 };
 237
 238 /* l4_wkup */
 239 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 240         .name           = "l4_wkup",
 241         .class          = &omap44xx_l4_hwmod_class,
 242         .clkdm_name     = "l4_wkup_clkdm",
 243         .prcm = {
 244                 .omap4 = {
 245                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 246                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 247                 },
 248         },
 249 };
 250
 251 /*
 252  * 'mpu_bus' class
 253  * instance(s): mpu_private
 254  */
 255 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 256         .name   = "mpu_bus",
 257 };
 258
 259 /* mpu_private */
 260 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 261         .name           = "mpu_private",
 262         .class          = &omap44xx_mpu_bus_hwmod_class,
 263         .clkdm_name     = "mpuss_clkdm",
 264         .prcm = {
 265                 .omap4 = {
 266                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 267                 },
 268         },
 269 };
 270
 271 /*
 272  * 'ocp_wp_noc' class
 273  * instance(s): ocp_wp_noc
 274  */
 275 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 276         .name   = "ocp_wp_noc",
 277 };
 278
 279 /* ocp_wp_noc */
 280 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 281         .name           = "ocp_wp_noc",
 282         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 283         .clkdm_name     = "l3_instr_clkdm",
 284         .prcm = {
 285                 .omap4 = {
 286                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 287                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 288                         .modulemode   = MODULEMODE_HWCTRL,
 289                 },
 290         },
 291 };
 292
 293 /*
 294  * Modules omap_hwmod structures
 295  *
 296  * The following IPs are excluded for the moment because:
 297  * - They do not need an explicit SW control using omap_hwmod API.
 298  * - They still need to be validated with the driver
 299  *   properly adapted to omap_hwmod / omap_device
 300  *
 301  * usim
 302  */
 303
 304 /*
 305  * 'aess' class
 306  * audio engine sub system
 307  */
 308
 309 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 310         .rev_offs       = 0x0000,
 311         .sysc_offs      = 0x0010,
 312         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 313         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 314                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 315                            MSTANDBY_SMART_WKUP),
 316         .sysc_fields    = &omap_hwmod_sysc_type2,
 317 };
 318
 319 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 320         .name   = "aess",
 321         .sysc   = &omap44xx_aess_sysc,
 322 };
 323
 324 /* aess */
 325 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 326         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 327         { .irq = -1 }
 328 };
 329
 330 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 331         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 332         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 333         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 334         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 339         { .dma_req = -1 }
 340 };
 341
 342 static struct omap_hwmod omap44xx_aess_hwmod = {
 343         .name           = "aess",
 344         .class          = &omap44xx_aess_hwmod_class,
 345         .clkdm_name     = "abe_clkdm",
 346         .mpu_irqs       = omap44xx_aess_irqs,
 347         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 348         .main_clk       = "aess_fck",
 349         .prcm = {
 350                 .omap4 = {
 351                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 352                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 353                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 354                         .modulemode   = MODULEMODE_SWCTRL,
 355                 },
 356         },
 357 };
 358
 359 /*
 360  * 'c2c' class
 361  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 362  * soc
 363  */
 364
 365 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 366         .name   = "c2c",
 367 };
 368
 369 /* c2c */
 370 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 371         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 372         { .irq = -1 }
 373 };
 374
 375 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 376         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 377         { .dma_req = -1 }
 378 };
 379
 380 static struct omap_hwmod omap44xx_c2c_hwmod = {
 381         .name           = "c2c",
 382         .class          = &omap44xx_c2c_hwmod_class,
 383         .clkdm_name     = "d2d_clkdm",
 384         .mpu_irqs       = omap44xx_c2c_irqs,
 385         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 386         .prcm = {
 387                 .omap4 = {
 388                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 389                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 390                 },
 391         },
 392 };
 393
 394 /*
 395  * 'counter' class
 396  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 397  */
 398
 399 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 400         .rev_offs       = 0x0000,
 401         .sysc_offs      = 0x0004,
 402         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 403         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 404         .sysc_fields    = &omap_hwmod_sysc_type1,
 405 };
 406
 407 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 408         .name   = "counter",
 409         .sysc   = &omap44xx_counter_sysc,
 410 };
 411
 412 /* counter_32k */
 413 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 414         .name           = "counter_32k",
 415         .class          = &omap44xx_counter_hwmod_class,
 416         .clkdm_name     = "l4_wkup_clkdm",
 417         .flags          = HWMOD_SWSUP_SIDLE,
 418         .main_clk       = "sys_32k_ck",
 419         .prcm = {
 420                 .omap4 = {
 421                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 422                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 423                 },
 424         },
 425 };
 426
 427 /*
 428  * 'ctrl_module' class
 429  * attila core control module + core pad control module + wkup pad control
 430  * module + attila wkup control module
 431  */
 432
 433 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 434         .rev_offs       = 0x0000,
 435         .sysc_offs      = 0x0010,
 436         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 437         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 438                            SIDLE_SMART_WKUP),
 439         .sysc_fields    = &omap_hwmod_sysc_type2,
 440 };
 441
 442 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 443         .name   = "ctrl_module",
 444         .sysc   = &omap44xx_ctrl_module_sysc,
 445 };
 446
 447 /* ctrl_module_core */
 448 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 449         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 450         { .irq = -1 }
 451 };
 452
 453 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 454         .name           = "ctrl_module_core",
 455         .class          = &omap44xx_ctrl_module_hwmod_class,
 456         .clkdm_name     = "l4_cfg_clkdm",
 457         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 458         .prcm = {
 459                 .omap4 = {
 460                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 461                 },
 462         },
 463 };
 464
 465 /* ctrl_module_pad_core */
 466 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 467         .name           = "ctrl_module_pad_core",
 468         .class          = &omap44xx_ctrl_module_hwmod_class,
 469         .clkdm_name     = "l4_cfg_clkdm",
 470         .prcm = {
 471                 .omap4 = {
 472                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 473                 },
 474         },
 475 };
 476
 477 /* ctrl_module_wkup */
 478 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 479         .name           = "ctrl_module_wkup",
 480         .class          = &omap44xx_ctrl_module_hwmod_class,
 481         .clkdm_name     = "l4_wkup_clkdm",
 482         .prcm = {
 483                 .omap4 = {
 484                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 485                 },
 486         },
 487 };
 488
 489 /* ctrl_module_pad_wkup */
 490 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 491         .name           = "ctrl_module_pad_wkup",
 492         .class          = &omap44xx_ctrl_module_hwmod_class,
 493         .clkdm_name     = "l4_wkup_clkdm",
 494         .prcm = {
 495                 .omap4 = {
 496                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 497                 },
 498         },
 499 };
 500
 501 /*
 502  * 'debugss' class
 503  * debug and emulation sub system
 504  */
 505
 506 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 507         .name   = "debugss",
 508 };
 509
 510 /* debugss */
 511 static struct omap_hwmod omap44xx_debugss_hwmod = {
 512         .name           = "debugss",
 513         .class          = &omap44xx_debugss_hwmod_class,
 514         .clkdm_name     = "emu_sys_clkdm",
 515         .main_clk       = "trace_clk_div_ck",
 516         .prcm = {
 517                 .omap4 = {
 518                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 519                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 520                 },
 521         },
 522 };
 523
 524 /*
 525  * 'dma' class
 526  * dma controller for data exchange between memory to memory (i.e. internal or
 527  * external memory) and gp peripherals to memory or memory to gp peripherals
 528  */
 529
 530 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 531         .rev_offs       = 0x0000,
 532         .sysc_offs      = 0x002c,
 533         .syss_offs      = 0x0028,
 534         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 535                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 536                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 537                            SYSS_HAS_RESET_STATUS),
 538         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 539                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 540         .sysc_fields    = &omap_hwmod_sysc_type1,
 541 };
 542
 543 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 544         .name   = "dma",
 545         .sysc   = &omap44xx_dma_sysc,
 546 };
 547
 548 /* dma dev_attr */
 549 static struct omap_dma_dev_attr dma_dev_attr = {
 550         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 551                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 552         .lch_count      = 32,
 553 };
 554
 555 /* dma_system */
 556 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 557         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 558         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 559         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 560         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 561         { .irq = -1 }
 562 };
 563
 564 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 565         .name           = "dma_system",
 566         .class          = &omap44xx_dma_hwmod_class,
 567         .clkdm_name     = "l3_dma_clkdm",
 568         .mpu_irqs       = omap44xx_dma_system_irqs,
 569         .main_clk       = "l3_div_ck",
 570         .prcm = {
 571                 .omap4 = {
 572                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 573                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 574                 },
 575         },
 576         .dev_attr       = &dma_dev_attr,
 577 };
 578
 579 /*
 580  * 'dmic' class
 581  * digital microphone controller
 582  */
 583
 584 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 585         .rev_offs       = 0x0000,
 586         .sysc_offs      = 0x0010,
 587         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 588                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 589         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 590                            SIDLE_SMART_WKUP),
 591         .sysc_fields    = &omap_hwmod_sysc_type2,
 592 };
 593
 594 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 595         .name   = "dmic",
 596         .sysc   = &omap44xx_dmic_sysc,
 597 };
 598
 599 /* dmic */
 600 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 601         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 602         { .irq = -1 }
 603 };
 604
 605 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 606         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 607         { .dma_req = -1 }
 608 };
 609
 610 static struct omap_hwmod omap44xx_dmic_hwmod = {
 611         .name           = "dmic",
 612         .class          = &omap44xx_dmic_hwmod_class,
 613         .clkdm_name     = "abe_clkdm",
 614         .mpu_irqs       = omap44xx_dmic_irqs,
 615         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 616         .main_clk       = "dmic_fck",
 617         .prcm = {
 618                 .omap4 = {
 619                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 620                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 621                         .modulemode   = MODULEMODE_SWCTRL,
 622                 },
 623         },
 624 };
 625
 626 /*
 627  * 'dsp' class
 628  * dsp sub-system
 629  */
 630
 631 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 632         .name   = "dsp",
 633 };
 634
 635 /* dsp */
 636 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 637         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 638         { .irq = -1 }
 639 };
 640
 641 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 642         { .name = "dsp", .rst_shift = 0 },
 643         { .name = "mmu_cache", .rst_shift = 1 },
 644 };
 645
 646 static struct omap_hwmod omap44xx_dsp_hwmod = {
 647         .name           = "dsp",
 648         .class          = &omap44xx_dsp_hwmod_class,
 649         .clkdm_name     = "tesla_clkdm",
 650         .mpu_irqs       = omap44xx_dsp_irqs,
 651         .rst_lines      = omap44xx_dsp_resets,
 652         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 653         .main_clk       = "dsp_fck",
 654         .prcm = {
 655                 .omap4 = {
 656                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 657                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 658                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 659                         .modulemode   = MODULEMODE_HWCTRL,
 660                 },
 661         },
 662 };
 663
 664 /*
 665  * 'dss' class
 666  * display sub-system
 667  */
 668
 669 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 670         .rev_offs       = 0x0000,
 671         .syss_offs      = 0x0014,
 672         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 673 };
 674
 675 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 676         .name   = "dss",
 677         .sysc   = &omap44xx_dss_sysc,
 678         .reset  = omap_dss_reset,
 679 };
 680
 681 /* dss */
 682 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 683         { .role = "sys_clk", .clk = "dss_sys_clk" },
 684         { .role = "tv_clk", .clk = "dss_tv_clk" },
 685         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 686 };
 687
 688 static struct omap_hwmod omap44xx_dss_hwmod = {
 689         .name           = "dss_core",
 690         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 691         .class          = &omap44xx_dss_hwmod_class,
 692         .clkdm_name     = "l3_dss_clkdm",
 693         .main_clk       = "dss_dss_clk",
 694         .prcm = {
 695                 .omap4 = {
 696                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 697                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 698                 },
 699         },
 700         .opt_clks       = dss_opt_clks,
 701         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 702 };
 703
 704 /*
 705  * 'dispc' class
 706  * display controller
 707  */
 708
 709 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 710         .rev_offs       = 0x0000,
 711         .sysc_offs      = 0x0010,
 712         .syss_offs      = 0x0014,
 713         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 714                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 715                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 716                            SYSS_HAS_RESET_STATUS),
 717         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 718                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 719         .sysc_fields    = &omap_hwmod_sysc_type1,
 720 };
 721
 722 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 723         .name   = "dispc",
 724         .sysc   = &omap44xx_dispc_sysc,
 725 };
 726
 727 /* dss_dispc */
 728 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 729         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 730         { .irq = -1 }
 731 };
 732
 733 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 734         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 735         { .dma_req = -1 }
 736 };
 737
 738 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 739         .manager_count          = 3,
 740         .has_framedonetv_irq    = 1
 741 };
 742
 743 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 744         .name           = "dss_dispc",
 745         .class          = &omap44xx_dispc_hwmod_class,
 746         .clkdm_name     = "l3_dss_clkdm",
 747         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 748         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 749         .main_clk       = "dss_dss_clk",
 750         .prcm = {
 751                 .omap4 = {
 752                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 753                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 754                 },
 755         },
 756         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 757 };
 758
 759 /*
 760  * 'dsi' class
 761  * display serial interface controller
 762  */
 763
 764 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 765         .rev_offs       = 0x0000,
 766         .sysc_offs      = 0x0010,
 767         .syss_offs      = 0x0014,
 768         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 769                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 770                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 771         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 772         .sysc_fields    = &omap_hwmod_sysc_type1,
 773 };
 774
 775 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 776         .name   = "dsi",
 777         .sysc   = &omap44xx_dsi_sysc,
 778 };
 779
 780 /* dss_dsi1 */
 781 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 782         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 783         { .irq = -1 }
 784 };
 785
 786 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 787         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 788         { .dma_req = -1 }
 789 };
 790
 791 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 792         { .role = "sys_clk", .clk = "dss_sys_clk" },
 793 };
 794
 795 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 796         .name           = "dss_dsi1",
 797         .class          = &omap44xx_dsi_hwmod_class,
 798         .clkdm_name     = "l3_dss_clkdm",
 799         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 800         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 801         .main_clk       = "dss_dss_clk",
 802         .prcm = {
 803                 .omap4 = {
 804                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 805                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 806                 },
 807         },
 808         .opt_clks       = dss_dsi1_opt_clks,
 809         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 810 };
 811
 812 /* dss_dsi2 */
 813 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 814         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 815         { .irq = -1 }
 816 };
 817
 818 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 819         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 820         { .dma_req = -1 }
 821 };
 822
 823 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 824         { .role = "sys_clk", .clk = "dss_sys_clk" },
 825 };
 826
 827 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 828         .name           = "dss_dsi2",
 829         .class          = &omap44xx_dsi_hwmod_class,
 830         .clkdm_name     = "l3_dss_clkdm",
 831         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 832         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 833         .main_clk       = "dss_dss_clk",
 834         .prcm = {
 835                 .omap4 = {
 836                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 837                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 838                 },
 839         },
 840         .opt_clks       = dss_dsi2_opt_clks,
 841         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 842 };
 843
 844 /*
 845  * 'hdmi' class
 846  * hdmi controller
 847  */
 848
 849 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 850         .rev_offs       = 0x0000,
 851         .sysc_offs      = 0x0010,
 852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 853                            SYSC_HAS_SOFTRESET),
 854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 855                            SIDLE_SMART_WKUP),
 856         .sysc_fields    = &omap_hwmod_sysc_type2,
 857 };
 858
 859 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 860         .name   = "hdmi",
 861         .sysc   = &omap44xx_hdmi_sysc,
 862 };
 863
 864 /* dss_hdmi */
 865 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 866         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 867         { .irq = -1 }
 868 };
 869
 870 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 871         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 872         { .dma_req = -1 }
 873 };
 874
 875 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 876         { .role = "sys_clk", .clk = "dss_sys_clk" },
 877 };
 878
 879 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 880         .name           = "dss_hdmi",
 881         .class          = &omap44xx_hdmi_hwmod_class,
 882         .clkdm_name     = "l3_dss_clkdm",
 883         /*
 884          * HDMI audio requires to use no-idle mode. Hence,
 885          * set idle mode by software.
 886          */
 887         .flags          = HWMOD_SWSUP_SIDLE,
 888         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 889         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 890         .main_clk       = "dss_48mhz_clk",
 891         .prcm = {
 892                 .omap4 = {
 893                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 894                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 895                 },
 896         },
 897         .opt_clks       = dss_hdmi_opt_clks,
 898         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 899 };
 900
 901 /*
 902  * 'rfbi' class
 903  * remote frame buffer interface
 904  */
 905
 906 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 907         .rev_offs       = 0x0000,
 908         .sysc_offs      = 0x0010,
 909         .syss_offs      = 0x0014,
 910         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 911                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 912         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 913         .sysc_fields    = &omap_hwmod_sysc_type1,
 914 };
 915
 916 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 917         .name   = "rfbi",
 918         .sysc   = &omap44xx_rfbi_sysc,
 919 };
 920
 921 /* dss_rfbi */
 922 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 923         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 924         { .dma_req = -1 }
 925 };
 926
 927 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 928         { .role = "ick", .clk = "dss_fck" },
 929 };
 930
 931 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 932         .name           = "dss_rfbi",
 933         .class          = &omap44xx_rfbi_hwmod_class,
 934         .clkdm_name     = "l3_dss_clkdm",
 935         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 936         .main_clk       = "dss_dss_clk",
 937         .prcm = {
 938                 .omap4 = {
 939                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 940                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 941                 },
 942         },
 943         .opt_clks       = dss_rfbi_opt_clks,
 944         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 945 };
 946
 947 /*
 948  * 'venc' class
 949  * video encoder
 950  */
 951
 952 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 953         .name   = "venc",
 954 };
 955
 956 /* dss_venc */
 957 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 958         .name           = "dss_venc",
 959         .class          = &omap44xx_venc_hwmod_class,
 960         .clkdm_name     = "l3_dss_clkdm",
 961         .main_clk       = "dss_tv_clk",
 962         .prcm = {
 963                 .omap4 = {
 964                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 965                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 966                 },
 967         },
 968 };
 969
 970 /*
 971  * 'elm' class
 972  * bch error location module
 973  */
 974
 975 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 976         .rev_offs       = 0x0000,
 977         .sysc_offs      = 0x0010,
 978         .syss_offs      = 0x0014,
 979         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 980                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 981                            SYSS_HAS_RESET_STATUS),
 982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 983         .sysc_fields    = &omap_hwmod_sysc_type1,
 984 };
 985
 986 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 987         .name   = "elm",
 988         .sysc   = &omap44xx_elm_sysc,
 989 };
 990
 991 /* elm */
 992 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 993         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 994         { .irq = -1 }
 995 };
 996
 997 static struct omap_hwmod omap44xx_elm_hwmod = {
 998         .name           = "elm",
 999         .class          = &omap44xx_elm_hwmod_class,
1000         .clkdm_name     = "l4_per_clkdm",
1001         .mpu_irqs       = omap44xx_elm_irqs,
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1005                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1006                 },
1007         },
1008 };
1009
1010 /*
1011  * 'emif' class
1012  * external memory interface no1
1013  */
1014
1015 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1016         .rev_offs       = 0x0000,
1017 };
1018
1019 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1020         .name   = "emif",
1021         .sysc   = &omap44xx_emif_sysc,
1022 };
1023
1024 /* emif1 */
1025 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1026         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1027         { .irq = -1 }
1028 };
1029
1030 static struct omap_hwmod omap44xx_emif1_hwmod = {
1031         .name           = "emif1",
1032         .class          = &omap44xx_emif_hwmod_class,
1033         .clkdm_name     = "l3_emif_clkdm",
1034         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1035         .mpu_irqs       = omap44xx_emif1_irqs,
1036         .main_clk       = "ddrphy_ck",
1037         .prcm = {
1038                 .omap4 = {
1039                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1040                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1041                         .modulemode   = MODULEMODE_HWCTRL,
1042                 },
1043         },
1044 };
1045
1046 /* emif2 */
1047 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1048         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1049         { .irq = -1 }
1050 };
1051
1052 static struct omap_hwmod omap44xx_emif2_hwmod = {
1053         .name           = "emif2",
1054         .class          = &omap44xx_emif_hwmod_class,
1055         .clkdm_name     = "l3_emif_clkdm",
1056         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1057         .mpu_irqs       = omap44xx_emif2_irqs,
1058         .main_clk       = "ddrphy_ck",
1059         .prcm = {
1060                 .omap4 = {
1061                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1062                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1063                         .modulemode   = MODULEMODE_HWCTRL,
1064                 },
1065         },
1066 };
1067
1068 /*
1069  * 'fdif' class
1070  * face detection hw accelerator module
1071  */
1072
1073 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1074         .rev_offs       = 0x0000,
1075         .sysc_offs      = 0x0010,
1076         /*
1077          * FDIF needs 100 OCP clk cycles delay after a softreset before
1078          * accessing sysconfig again.
1079          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1080          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1081          *
1082          * TODO: Indicate errata when available.
1083          */
1084         .srst_udelay    = 2,
1085         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1086                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1087         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1088                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1089         .sysc_fields    = &omap_hwmod_sysc_type2,
1090 };
1091
1092 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1093         .name   = "fdif",
1094         .sysc   = &omap44xx_fdif_sysc,
1095 };
1096
1097 /* fdif */
1098 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1099         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1100         { .irq = -1 }
1101 };
1102
1103 static struct omap_hwmod omap44xx_fdif_hwmod = {
1104         .name           = "fdif",
1105         .class          = &omap44xx_fdif_hwmod_class,
1106         .clkdm_name     = "iss_clkdm",
1107         .mpu_irqs       = omap44xx_fdif_irqs,
1108         .main_clk       = "fdif_fck",
1109         .prcm = {
1110                 .omap4 = {
1111                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1112                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1113                         .modulemode   = MODULEMODE_SWCTRL,
1114                 },
1115         },
1116 };
1117
1118 /*
1119  * 'gpio' class
1120  * general purpose io module
1121  */
1122
1123 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1124         .rev_offs       = 0x0000,
1125         .sysc_offs      = 0x0010,
1126         .syss_offs      = 0x0114,
1127         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1128                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1129                            SYSS_HAS_RESET_STATUS),
1130         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1131                            SIDLE_SMART_WKUP),
1132         .sysc_fields    = &omap_hwmod_sysc_type1,
1133 };
1134
1135 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1136         .name   = "gpio",
1137         .sysc   = &omap44xx_gpio_sysc,
1138         .rev    = 2,
1139 };
1140
1141 /* gpio dev_attr */
1142 static struct omap_gpio_dev_attr gpio_dev_attr = {
1143         .bank_width     = 32,
1144         .dbck_flag      = true,
1145 };
1146
1147 /* gpio1 */
1148 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1149         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1150         { .irq = -1 }
1151 };
1152
1153 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1154         { .role = "dbclk", .clk = "gpio1_dbclk" },
1155 };
1156
1157 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1158         .name           = "gpio1",
1159         .class          = &omap44xx_gpio_hwmod_class,
1160         .clkdm_name     = "l4_wkup_clkdm",
1161         .mpu_irqs       = omap44xx_gpio1_irqs,
1162         .main_clk       = "gpio1_ick",
1163         .prcm = {
1164                 .omap4 = {
1165                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1166                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1167                         .modulemode   = MODULEMODE_HWCTRL,
1168                 },
1169         },
1170         .opt_clks       = gpio1_opt_clks,
1171         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1172         .dev_attr       = &gpio_dev_attr,
1173 };
1174
1175 /* gpio2 */
1176 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1177         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1178         { .irq = -1 }
1179 };
1180
1181 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1182         { .role = "dbclk", .clk = "gpio2_dbclk" },
1183 };
1184
1185 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1186         .name           = "gpio2",
1187         .class          = &omap44xx_gpio_hwmod_class,
1188         .clkdm_name     = "l4_per_clkdm",
1189         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1190         .mpu_irqs       = omap44xx_gpio2_irqs,
1191         .main_clk       = "gpio2_ick",
1192         .prcm = {
1193                 .omap4 = {
1194                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1195                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1196                         .modulemode   = MODULEMODE_HWCTRL,
1197                 },
1198         },
1199         .opt_clks       = gpio2_opt_clks,
1200         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1201         .dev_attr       = &gpio_dev_attr,
1202 };
1203
1204 /* gpio3 */
1205 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1206         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1207         { .irq = -1 }
1208 };
1209
1210 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1211         { .role = "dbclk", .clk = "gpio3_dbclk" },
1212 };
1213
1214 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1215         .name           = "gpio3",
1216         .class          = &omap44xx_gpio_hwmod_class,
1217         .clkdm_name     = "l4_per_clkdm",
1218         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1219         .mpu_irqs       = omap44xx_gpio3_irqs,
1220         .main_clk       = "gpio3_ick",
1221         .prcm = {
1222                 .omap4 = {
1223                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1224                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1225                         .modulemode   = MODULEMODE_HWCTRL,
1226                 },
1227         },
1228         .opt_clks       = gpio3_opt_clks,
1229         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1230         .dev_attr       = &gpio_dev_attr,
1231 };
1232
1233 /* gpio4 */
1234 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1235         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1236         { .irq = -1 }
1237 };
1238
1239 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1240         { .role = "dbclk", .clk = "gpio4_dbclk" },
1241 };
1242
1243 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1244         .name           = "gpio4",
1245         .class          = &omap44xx_gpio_hwmod_class,
1246         .clkdm_name     = "l4_per_clkdm",
1247         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1248         .mpu_irqs       = omap44xx_gpio4_irqs,
1249         .main_clk       = "gpio4_ick",
1250         .prcm = {
1251                 .omap4 = {
1252                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1253                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1254                         .modulemode   = MODULEMODE_HWCTRL,
1255                 },
1256         },
1257         .opt_clks       = gpio4_opt_clks,
1258         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1259         .dev_attr       = &gpio_dev_attr,
1260 };
1261
1262 /* gpio5 */
1263 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1264         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1265         { .irq = -1 }
1266 };
1267
1268 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1269         { .role = "dbclk", .clk = "gpio5_dbclk" },
1270 };
1271
1272 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1273         .name           = "gpio5",
1274         .class          = &omap44xx_gpio_hwmod_class,
1275         .clkdm_name     = "l4_per_clkdm",
1276         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1277         .mpu_irqs       = omap44xx_gpio5_irqs,
1278         .main_clk       = "gpio5_ick",
1279         .prcm = {
1280                 .omap4 = {
1281                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1282                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1283                         .modulemode   = MODULEMODE_HWCTRL,
1284                 },
1285         },
1286         .opt_clks       = gpio5_opt_clks,
1287         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1288         .dev_attr       = &gpio_dev_attr,
1289 };
1290
1291 /* gpio6 */
1292 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1293         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1294         { .irq = -1 }
1295 };
1296
1297 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1298         { .role = "dbclk", .clk = "gpio6_dbclk" },
1299 };
1300
1301 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1302         .name           = "gpio6",
1303         .class          = &omap44xx_gpio_hwmod_class,
1304         .clkdm_name     = "l4_per_clkdm",
1305         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1306         .mpu_irqs       = omap44xx_gpio6_irqs,
1307         .main_clk       = "gpio6_ick",
1308         .prcm = {
1309                 .omap4 = {
1310                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1311                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1312                         .modulemode   = MODULEMODE_HWCTRL,
1313                 },
1314         },
1315         .opt_clks       = gpio6_opt_clks,
1316         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1317         .dev_attr       = &gpio_dev_attr,
1318 };
1319
1320 /*
1321  * 'gpmc' class
1322  * general purpose memory controller
1323  */
1324
1325 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1326         .rev_offs       = 0x0000,
1327         .sysc_offs      = 0x0010,
1328         .syss_offs      = 0x0014,
1329         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1330                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1331         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1332         .sysc_fields    = &omap_hwmod_sysc_type1,
1333 };
1334
1335 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1336         .name   = "gpmc",
1337         .sysc   = &omap44xx_gpmc_sysc,
1338 };
1339
1340 /* gpmc */
1341 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1342         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1343         { .irq = -1 }
1344 };
1345
1346 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1347         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1348         { .dma_req = -1 }
1349 };
1350
1351 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1352         .name           = "gpmc",
1353         .class          = &omap44xx_gpmc_hwmod_class,
1354         .clkdm_name     = "l3_2_clkdm",
1355         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1356         .mpu_irqs       = omap44xx_gpmc_irqs,
1357         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1358         .prcm = {
1359                 .omap4 = {
1360                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1361                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1362                         .modulemode   = MODULEMODE_HWCTRL,
1363                 },
1364         },
1365 };
1366
1367 /*
1368  * 'gpu' class
1369  * 2d/3d graphics accelerator
1370  */
1371
1372 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1373         .rev_offs       = 0x1fc00,
1374         .sysc_offs      = 0x1fc10,
1375         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1376         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1377                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1378                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1379         .sysc_fields    = &omap_hwmod_sysc_type2,
1380 };
1381
1382 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1383         .name   = "gpu",
1384         .sysc   = &omap44xx_gpu_sysc,
1385 };
1386
1387 /* gpu */
1388 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1389         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1390         { .irq = -1 }
1391 };
1392
1393 static struct omap_hwmod omap44xx_gpu_hwmod = {
1394         .name           = "gpu",
1395         .class          = &omap44xx_gpu_hwmod_class,
1396         .clkdm_name     = "l3_gfx_clkdm",
1397         .mpu_irqs       = omap44xx_gpu_irqs,
1398         .main_clk       = "gpu_fck",
1399         .prcm = {
1400                 .omap4 = {
1401                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1402                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1403                         .modulemode   = MODULEMODE_SWCTRL,
1404                 },
1405         },
1406 };
1407
1408 /*
1409  * 'hdq1w' class
1410  * hdq / 1-wire serial interface controller
1411  */
1412
1413 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1414         .rev_offs       = 0x0000,
1415         .sysc_offs      = 0x0014,
1416         .syss_offs      = 0x0018,
1417         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1418                            SYSS_HAS_RESET_STATUS),
1419         .sysc_fields    = &omap_hwmod_sysc_type1,
1420 };
1421
1422 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1423         .name   = "hdq1w",
1424         .sysc   = &omap44xx_hdq1w_sysc,
1425 };
1426
1427 /* hdq1w */
1428 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1429         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1430         { .irq = -1 }
1431 };
1432
1433 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1434         .name           = "hdq1w",
1435         .class          = &omap44xx_hdq1w_hwmod_class,
1436         .clkdm_name     = "l4_per_clkdm",
1437         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1438         .mpu_irqs       = omap44xx_hdq1w_irqs,
1439         .main_clk       = "hdq1w_fck",
1440         .prcm = {
1441                 .omap4 = {
1442                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1443                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1444                         .modulemode   = MODULEMODE_SWCTRL,
1445                 },
1446         },
1447 };
1448
1449 /*
1450  * 'hsi' class
1451  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1452  * serial if)
1453  */
1454
1455 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1456         .rev_offs       = 0x0000,
1457         .sysc_offs      = 0x0010,
1458         .syss_offs      = 0x0014,
1459         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1460                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1461                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1462         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1463                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1464                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1465         .sysc_fields    = &omap_hwmod_sysc_type1,
1466 };
1467
1468 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1469         .name   = "hsi",
1470         .sysc   = &omap44xx_hsi_sysc,
1471 };
1472
1473 /* hsi */
1474 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1475         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1476         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1477         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1478         { .irq = -1 }
1479 };
1480
1481 static struct omap_hwmod omap44xx_hsi_hwmod = {
1482         .name           = "hsi",
1483         .class          = &omap44xx_hsi_hwmod_class,
1484         .clkdm_name     = "l3_init_clkdm",
1485         .mpu_irqs       = omap44xx_hsi_irqs,
1486         .main_clk       = "hsi_fck",
1487         .prcm = {
1488                 .omap4 = {
1489                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1490                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1491                         .modulemode   = MODULEMODE_HWCTRL,
1492                 },
1493         },
1494 };
1495
1496 /*
1497  * 'i2c' class
1498  * multimaster high-speed i2c controller
1499  */
1500
1501 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1502         .sysc_offs      = 0x0010,
1503         .syss_offs      = 0x0090,
1504         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1505                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1506                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1507         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1508                            SIDLE_SMART_WKUP),
1509         .clockact       = CLOCKACT_TEST_ICLK,
1510         .sysc_fields    = &omap_hwmod_sysc_type1,
1511 };
1512
1513 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1514         .name   = "i2c",
1515         .sysc   = &omap44xx_i2c_sysc,
1516         .rev    = OMAP_I2C_IP_VERSION_2,
1517         .reset  = &omap_i2c_reset,
1518 };
1519
1520 static struct omap_i2c_dev_attr i2c_dev_attr = {
1521         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1522                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1523 };
1524
1525 /* i2c1 */
1526 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1527         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1528         { .irq = -1 }
1529 };
1530
1531 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1532         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1533         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1534         { .dma_req = -1 }
1535 };
1536
1537 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1538         .name           = "i2c1",
1539         .class          = &omap44xx_i2c_hwmod_class,
1540         .clkdm_name     = "l4_per_clkdm",
1541         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1542         .mpu_irqs       = omap44xx_i2c1_irqs,
1543         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1544         .main_clk       = "i2c1_fck",
1545         .prcm = {
1546                 .omap4 = {
1547                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1548                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1549                         .modulemode   = MODULEMODE_SWCTRL,
1550                 },
1551         },
1552         .dev_attr       = &i2c_dev_attr,
1553 };
1554
1555 /* i2c2 */
1556 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1557         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1558         { .irq = -1 }
1559 };
1560
1561 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1562         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1563         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1564         { .dma_req = -1 }
1565 };
1566
1567 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1568         .name           = "i2c2",
1569         .class          = &omap44xx_i2c_hwmod_class,
1570         .clkdm_name     = "l4_per_clkdm",
1571         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1572         .mpu_irqs       = omap44xx_i2c2_irqs,
1573         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1574         .main_clk       = "i2c2_fck",
1575         .prcm = {
1576                 .omap4 = {
1577                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1578                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1579                         .modulemode   = MODULEMODE_SWCTRL,
1580                 },
1581         },
1582         .dev_attr       = &i2c_dev_attr,
1583 };
1584
1585 /* i2c3 */
1586 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1587         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1588         { .irq = -1 }
1589 };
1590
1591 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1592         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1593         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1594         { .dma_req = -1 }
1595 };
1596
1597 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1598         .name           = "i2c3",
1599         .class          = &omap44xx_i2c_hwmod_class,
1600         .clkdm_name     = "l4_per_clkdm",
1601         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1602         .mpu_irqs       = omap44xx_i2c3_irqs,
1603         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1604         .main_clk       = "i2c3_fck",
1605         .prcm = {
1606                 .omap4 = {
1607                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1608                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1609                         .modulemode   = MODULEMODE_SWCTRL,
1610                 },
1611         },
1612         .dev_attr       = &i2c_dev_attr,
1613 };
1614
1615 /* i2c4 */
1616 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1617         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1618         { .irq = -1 }
1619 };
1620
1621 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1622         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1623         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1624         { .dma_req = -1 }
1625 };
1626
1627 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1628         .name           = "i2c4",
1629         .class          = &omap44xx_i2c_hwmod_class,
1630         .clkdm_name     = "l4_per_clkdm",
1631         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1632         .mpu_irqs       = omap44xx_i2c4_irqs,
1633         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1634         .main_clk       = "i2c4_fck",
1635         .prcm = {
1636                 .omap4 = {
1637                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1638                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1639                         .modulemode   = MODULEMODE_SWCTRL,
1640                 },
1641         },
1642         .dev_attr       = &i2c_dev_attr,
1643 };
1644
1645 /*
1646  * 'ipu' class
1647  * imaging processor unit
1648  */
1649
1650 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1651         .name   = "ipu",
1652 };
1653
1654 /* ipu */
1655 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1656         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1657         { .irq = -1 }
1658 };
1659
1660 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1661         { .name = "cpu0", .rst_shift = 0 },
1662         { .name = "cpu1", .rst_shift = 1 },
1663         { .name = "mmu_cache", .rst_shift = 2 },
1664 };
1665
1666 static struct omap_hwmod omap44xx_ipu_hwmod = {
1667         .name           = "ipu",
1668         .class          = &omap44xx_ipu_hwmod_class,
1669         .clkdm_name     = "ducati_clkdm",
1670         .mpu_irqs       = omap44xx_ipu_irqs,
1671         .rst_lines      = omap44xx_ipu_resets,
1672         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1673         .main_clk       = "ipu_fck",
1674         .prcm = {
1675                 .omap4 = {
1676                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1677                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1678                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1679                         .modulemode   = MODULEMODE_HWCTRL,
1680                 },
1681         },
1682 };
1683
1684 /*
1685  * 'iss' class
1686  * external images sensor pixel data processor
1687  */
1688
1689 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1690         .rev_offs       = 0x0000,
1691         .sysc_offs      = 0x0010,
1692         /*
1693          * ISS needs 100 OCP clk cycles delay after a softreset before
1694          * accessing sysconfig again.
1695          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1696          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1697          *
1698          * TODO: Indicate errata when available.
1699          */
1700         .srst_udelay    = 2,
1701         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1702                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1703         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1704                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1705                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1706         .sysc_fields    = &omap_hwmod_sysc_type2,
1707 };
1708
1709 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1710         .name   = "iss",
1711         .sysc   = &omap44xx_iss_sysc,
1712 };
1713
1714 /* iss */
1715 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1716         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1717         { .irq = -1 }
1718 };
1719
1720 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1721         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1722         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1723         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1724         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1725         { .dma_req = -1 }
1726 };
1727
1728 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1729         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1730 };
1731
1732 static struct omap_hwmod omap44xx_iss_hwmod = {
1733         .name           = "iss",
1734         .class          = &omap44xx_iss_hwmod_class,
1735         .clkdm_name     = "iss_clkdm",
1736         .mpu_irqs       = omap44xx_iss_irqs,
1737         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1738         .main_clk       = "iss_fck",
1739         .prcm = {
1740                 .omap4 = {
1741                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1742                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1743                         .modulemode   = MODULEMODE_SWCTRL,
1744                 },
1745         },
1746         .opt_clks       = iss_opt_clks,
1747         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1748 };
1749
1750 /*
1751  * 'iva' class
1752  * multi-standard video encoder/decoder hardware accelerator
1753  */
1754
1755 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1756         .name   = "iva",
1757 };
1758
1759 /* iva */
1760 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1761         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1762         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1763         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1764         { .irq = -1 }
1765 };
1766
1767 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1768         { .name = "seq0", .rst_shift = 0 },
1769         { .name = "seq1", .rst_shift = 1 },
1770         { .name = "logic", .rst_shift = 2 },
1771 };
1772
1773 static struct omap_hwmod omap44xx_iva_hwmod = {
1774         .name           = "iva",
1775         .class          = &omap44xx_iva_hwmod_class,
1776         .clkdm_name     = "ivahd_clkdm",
1777         .mpu_irqs       = omap44xx_iva_irqs,
1778         .rst_lines      = omap44xx_iva_resets,
1779         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1780         .main_clk       = "iva_fck",
1781         .prcm = {
1782                 .omap4 = {
1783                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1784                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1785                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1786                         .modulemode   = MODULEMODE_HWCTRL,
1787                 },
1788         },
1789 };
1790
1791 /*
1792  * 'kbd' class
1793  * keyboard controller
1794  */
1795
1796 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1797         .rev_offs       = 0x0000,
1798         .sysc_offs      = 0x0010,
1799         .syss_offs      = 0x0014,
1800         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1801                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1802                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1803                            SYSS_HAS_RESET_STATUS),
1804         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1805         .sysc_fields    = &omap_hwmod_sysc_type1,
1806 };
1807
1808 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1809         .name   = "kbd",
1810         .sysc   = &omap44xx_kbd_sysc,
1811 };
1812
1813 /* kbd */
1814 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1815         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1816         { .irq = -1 }
1817 };
1818
1819 static struct omap_hwmod omap44xx_kbd_hwmod = {
1820         .name           = "kbd",
1821         .class          = &omap44xx_kbd_hwmod_class,
1822         .clkdm_name     = "l4_wkup_clkdm",
1823         .mpu_irqs       = omap44xx_kbd_irqs,
1824         .main_clk       = "kbd_fck",
1825         .prcm = {
1826                 .omap4 = {
1827                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1828                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1829                         .modulemode   = MODULEMODE_SWCTRL,
1830                 },
1831         },
1832 };
1833
1834 /*
1835  * 'mailbox' class
1836  * mailbox module allowing communication between the on-chip processors using a
1837  * queued mailbox-interrupt mechanism.
1838  */
1839
1840 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1841         .rev_offs       = 0x0000,
1842         .sysc_offs      = 0x0010,
1843         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1844                            SYSC_HAS_SOFTRESET),
1845         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1846         .sysc_fields    = &omap_hwmod_sysc_type2,
1847 };
1848
1849 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1850         .name   = "mailbox",
1851         .sysc   = &omap44xx_mailbox_sysc,
1852 };
1853
1854 /* mailbox */
1855 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1856         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1857         { .irq = -1 }
1858 };
1859
1860 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1861         .name           = "mailbox",
1862         .class          = &omap44xx_mailbox_hwmod_class,
1863         .clkdm_name     = "l4_cfg_clkdm",
1864         .mpu_irqs       = omap44xx_mailbox_irqs,
1865         .prcm = {
1866                 .omap4 = {
1867                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1868                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1869                 },
1870         },
1871 };
1872
1873 /*
1874  * 'mcasp' class
1875  * multi-channel audio serial port controller
1876  */
1877
1878 /* The IP is not compliant to type1 / type2 scheme */
1879 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1880         .sidle_shift    = 0,
1881 };
1882
1883 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1884         .sysc_offs      = 0x0004,
1885         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1886         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1887                            SIDLE_SMART_WKUP),
1888         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1889 };
1890
1891 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1892         .name   = "mcasp",
1893         .sysc   = &omap44xx_mcasp_sysc,
1894 };
1895
1896 /* mcasp */
1897 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1898         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1899         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1900         { .irq = -1 }
1901 };
1902
1903 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1904         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1905         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1906         { .dma_req = -1 }
1907 };
1908
1909 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1910         .name           = "mcasp",
1911         .class          = &omap44xx_mcasp_hwmod_class,
1912         .clkdm_name     = "abe_clkdm",
1913         .mpu_irqs       = omap44xx_mcasp_irqs,
1914         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1915         .main_clk       = "mcasp_fck",
1916         .prcm = {
1917                 .omap4 = {
1918                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1919                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1920                         .modulemode   = MODULEMODE_SWCTRL,
1921                 },
1922         },
1923 };
1924
1925 /*
1926  * 'mcbsp' class
1927  * multi channel buffered serial port controller
1928  */
1929
1930 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1931         .sysc_offs      = 0x008c,
1932         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1933                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1934         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1935         .sysc_fields    = &omap_hwmod_sysc_type1,
1936 };
1937
1938 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1939         .name   = "mcbsp",
1940         .sysc   = &omap44xx_mcbsp_sysc,
1941         .rev    = MCBSP_CONFIG_TYPE4,
1942 };
1943
1944 /* mcbsp1 */
1945 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1946         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1947         { .irq = -1 }
1948 };
1949
1950 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1951         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1952         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1953         { .dma_req = -1 }
1954 };
1955
1956 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1957         { .role = "pad_fck", .clk = "pad_clks_ck" },
1958         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1959 };
1960
1961 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1962         .name           = "mcbsp1",
1963         .class          = &omap44xx_mcbsp_hwmod_class,
1964         .clkdm_name     = "abe_clkdm",
1965         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1966         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1967         .main_clk       = "mcbsp1_fck",
1968         .prcm = {
1969                 .omap4 = {
1970                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1971                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1972                         .modulemode   = MODULEMODE_SWCTRL,
1973                 },
1974         },
1975         .opt_clks       = mcbsp1_opt_clks,
1976         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1977 };
1978
1979 /* mcbsp2 */
1980 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1981         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1982         { .irq = -1 }
1983 };
1984
1985 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1986         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1987         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1988         { .dma_req = -1 }
1989 };
1990
1991 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1992         { .role = "pad_fck", .clk = "pad_clks_ck" },
1993         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1994 };
1995
1996 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1997         .name           = "mcbsp2",
1998         .class          = &omap44xx_mcbsp_hwmod_class,
1999         .clkdm_name     = "abe_clkdm",
2000         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2001         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2002         .main_clk       = "mcbsp2_fck",
2003         .prcm = {
2004                 .omap4 = {
2005                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2006                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2007                         .modulemode   = MODULEMODE_SWCTRL,
2008                 },
2009         },
2010         .opt_clks       = mcbsp2_opt_clks,
2011         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2012 };
2013
2014 /* mcbsp3 */
2015 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2016         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2017         { .irq = -1 }
2018 };
2019
2020 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2021         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2022         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2023         { .dma_req = -1 }
2024 };
2025
2026 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2027         { .role = "pad_fck", .clk = "pad_clks_ck" },
2028         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2029 };
2030
2031 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2032         .name           = "mcbsp3",
2033         .class          = &omap44xx_mcbsp_hwmod_class,
2034         .clkdm_name     = "abe_clkdm",
2035         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2036         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2037         .main_clk       = "mcbsp3_fck",
2038         .prcm = {
2039                 .omap4 = {
2040                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2041                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2042                         .modulemode   = MODULEMODE_SWCTRL,
2043                 },
2044         },
2045         .opt_clks       = mcbsp3_opt_clks,
2046         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2047 };
2048
2049 /* mcbsp4 */
2050 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2051         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2052         { .irq = -1 }
2053 };
2054
2055 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2056         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2057         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2058         { .dma_req = -1 }
2059 };
2060
2061 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2062         { .role = "pad_fck", .clk = "pad_clks_ck" },
2063         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2064 };
2065
2066 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2067         .name           = "mcbsp4",
2068         .class          = &omap44xx_mcbsp_hwmod_class,
2069         .clkdm_name     = "l4_per_clkdm",
2070         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2071         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2072         .main_clk       = "mcbsp4_fck",
2073         .prcm = {
2074                 .omap4 = {
2075                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2076                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2077                         .modulemode   = MODULEMODE_SWCTRL,
2078                 },
2079         },
2080         .opt_clks       = mcbsp4_opt_clks,
2081         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2082 };
2083
2084 /*
2085  * 'mcpdm' class
2086  * multi channel pdm controller (proprietary interface with phoenix power
2087  * ic)
2088  */
2089
2090 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2091         .rev_offs       = 0x0000,
2092         .sysc_offs      = 0x0010,
2093         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2094                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2095         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2096                            SIDLE_SMART_WKUP),
2097         .sysc_fields    = &omap_hwmod_sysc_type2,
2098 };
2099
2100 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2101         .name   = "mcpdm",
2102         .sysc   = &omap44xx_mcpdm_sysc,
2103 };
2104
2105 /* mcpdm */
2106 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2107         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2108         { .irq = -1 }
2109 };
2110
2111 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2112         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2113         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2114         { .dma_req = -1 }
2115 };
2116
2117 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2118         .name           = "mcpdm",
2119         .class          = &omap44xx_mcpdm_hwmod_class,
2120         .clkdm_name     = "abe_clkdm",
2121         .mpu_irqs       = omap44xx_mcpdm_irqs,
2122         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2123         .main_clk       = "mcpdm_fck",
2124         .prcm = {
2125                 .omap4 = {
2126                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2127                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2128                         .modulemode   = MODULEMODE_SWCTRL,
2129                 },
2130         },
2131 };
2132
2133 /*
2134  * 'mcspi' class
2135  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2136  * bus
2137  */
2138
2139 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2140         .rev_offs       = 0x0000,
2141         .sysc_offs      = 0x0010,
2142         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2143                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2144         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2145                            SIDLE_SMART_WKUP),
2146         .sysc_fields    = &omap_hwmod_sysc_type2,
2147 };
2148
2149 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2150         .name   = "mcspi",
2151         .sysc   = &omap44xx_mcspi_sysc,
2152         .rev    = OMAP4_MCSPI_REV,
2153 };
2154
2155 /* mcspi1 */
2156 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2157         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2158         { .irq = -1 }
2159 };
2160
2161 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2162         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2163         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2164         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2165         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2166         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2167         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2168         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2169         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2170         { .dma_req = -1 }
2171 };
2172
2173 /* mcspi1 dev_attr */
2174 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2175         .num_chipselect = 4,
2176 };
2177
2178 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2179         .name           = "mcspi1",
2180         .class          = &omap44xx_mcspi_hwmod_class,
2181         .clkdm_name     = "l4_per_clkdm",
2182         .mpu_irqs       = omap44xx_mcspi1_irqs,
2183         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2184         .main_clk       = "mcspi1_fck",
2185         .prcm = {
2186                 .omap4 = {
2187                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2188                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2189                         .modulemode   = MODULEMODE_SWCTRL,
2190                 },
2191         },
2192         .dev_attr       = &mcspi1_dev_attr,
2193 };
2194
2195 /* mcspi2 */
2196 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2197         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2198         { .irq = -1 }
2199 };
2200
2201 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2202         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2203         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2204         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2205         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2206         { .dma_req = -1 }
2207 };
2208
2209 /* mcspi2 dev_attr */
2210 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2211         .num_chipselect = 2,
2212 };
2213
2214 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2215         .name           = "mcspi2",
2216         .class          = &omap44xx_mcspi_hwmod_class,
2217         .clkdm_name     = "l4_per_clkdm",
2218         .mpu_irqs       = omap44xx_mcspi2_irqs,
2219         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2220         .main_clk       = "mcspi2_fck",
2221         .prcm = {
2222                 .omap4 = {
2223                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2224                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2225                         .modulemode   = MODULEMODE_SWCTRL,
2226                 },
2227         },
2228         .dev_attr       = &mcspi2_dev_attr,
2229 };
2230
2231 /* mcspi3 */
2232 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2233         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2234         { .irq = -1 }
2235 };
2236
2237 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2238         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2239         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2240         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2241         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2242         { .dma_req = -1 }
2243 };
2244
2245 /* mcspi3 dev_attr */
2246 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2247         .num_chipselect = 2,
2248 };
2249
2250 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2251         .name           = "mcspi3",
2252         .class          = &omap44xx_mcspi_hwmod_class,
2253         .clkdm_name     = "l4_per_clkdm",
2254         .mpu_irqs       = omap44xx_mcspi3_irqs,
2255         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2256         .main_clk       = "mcspi3_fck",
2257         .prcm = {
2258                 .omap4 = {
2259                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2260                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2261                         .modulemode   = MODULEMODE_SWCTRL,
2262                 },
2263         },
2264         .dev_attr       = &mcspi3_dev_attr,
2265 };
2266
2267 /* mcspi4 */
2268 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2269         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2270         { .irq = -1 }
2271 };
2272
2273 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2274         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2275         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2276         { .dma_req = -1 }
2277 };
2278
2279 /* mcspi4 dev_attr */
2280 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2281         .num_chipselect = 1,
2282 };
2283
2284 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2285         .name           = "mcspi4",
2286         .class          = &omap44xx_mcspi_hwmod_class,
2287         .clkdm_name     = "l4_per_clkdm",
2288         .mpu_irqs       = omap44xx_mcspi4_irqs,
2289         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2290         .main_clk       = "mcspi4_fck",
2291         .prcm = {
2292                 .omap4 = {
2293                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2294                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2295                         .modulemode   = MODULEMODE_SWCTRL,
2296                 },
2297         },
2298         .dev_attr       = &mcspi4_dev_attr,
2299 };
2300
2301 /*
2302  * 'mmc' class
2303  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2304  */
2305
2306 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2307         .rev_offs       = 0x0000,
2308         .sysc_offs      = 0x0010,
2309         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2310                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2311                            SYSC_HAS_SOFTRESET),
2312         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2313                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2314                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2315         .sysc_fields    = &omap_hwmod_sysc_type2,
2316 };
2317
2318 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2319         .name   = "mmc",
2320         .sysc   = &omap44xx_mmc_sysc,
2321 };
2322
2323 /* mmc1 */
2324 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2325         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2326         { .irq = -1 }
2327 };
2328
2329 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2330         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2331         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2332         { .dma_req = -1 }
2333 };
2334
2335 /* mmc1 dev_attr */
2336 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2337         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2338 };
2339
2340 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2341         .name           = "mmc1",
2342         .class          = &omap44xx_mmc_hwmod_class,
2343         .clkdm_name     = "l3_init_clkdm",
2344         .mpu_irqs       = omap44xx_mmc1_irqs,
2345         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2346         .main_clk       = "mmc1_fck",
2347         .prcm = {
2348                 .omap4 = {
2349                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2350                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2351                         .modulemode   = MODULEMODE_SWCTRL,
2352                 },
2353         },
2354         .dev_attr       = &mmc1_dev_attr,
2355 };
2356
2357 /* mmc2 */
2358 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2359         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2360         { .irq = -1 }
2361 };
2362
2363 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2364         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2365         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2366         { .dma_req = -1 }
2367 };
2368
2369 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2370         .name           = "mmc2",
2371         .class          = &omap44xx_mmc_hwmod_class,
2372         .clkdm_name     = "l3_init_clkdm",
2373         .mpu_irqs       = omap44xx_mmc2_irqs,
2374         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2375         .main_clk       = "mmc2_fck",
2376         .prcm = {
2377                 .omap4 = {
2378                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2379                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2380                         .modulemode   = MODULEMODE_SWCTRL,
2381                 },
2382         },
2383 };
2384
2385 /* mmc3 */
2386 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2387         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2388         { .irq = -1 }
2389 };
2390
2391 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2392         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2393         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2394         { .dma_req = -1 }
2395 };
2396
2397 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2398         .name           = "mmc3",
2399         .class          = &omap44xx_mmc_hwmod_class,
2400         .clkdm_name     = "l4_per_clkdm",
2401         .mpu_irqs       = omap44xx_mmc3_irqs,
2402         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2403         .main_clk       = "mmc3_fck",
2404         .prcm = {
2405                 .omap4 = {
2406                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2407                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2408                         .modulemode   = MODULEMODE_SWCTRL,
2409                 },
2410         },
2411 };
2412
2413 /* mmc4 */
2414 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2415         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2416         { .irq = -1 }
2417 };
2418
2419 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2420         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2421         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2422         { .dma_req = -1 }
2423 };
2424
2425 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2426         .name           = "mmc4",
2427         .class          = &omap44xx_mmc_hwmod_class,
2428         .clkdm_name     = "l4_per_clkdm",
2429         .mpu_irqs       = omap44xx_mmc4_irqs,
2430         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2431         .main_clk       = "mmc4_fck",
2432         .prcm = {
2433                 .omap4 = {
2434                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2435                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2436                         .modulemode   = MODULEMODE_SWCTRL,
2437                 },
2438         },
2439 };
2440
2441 /* mmc5 */
2442 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2443         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2444         { .irq = -1 }
2445 };
2446
2447 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2448         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2449         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2450         { .dma_req = -1 }
2451 };
2452
2453 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2454         .name           = "mmc5",
2455         .class          = &omap44xx_mmc_hwmod_class,
2456         .clkdm_name     = "l4_per_clkdm",
2457         .mpu_irqs       = omap44xx_mmc5_irqs,
2458         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2459         .main_clk       = "mmc5_fck",
2460         .prcm = {
2461                 .omap4 = {
2462                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2463                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2464                         .modulemode   = MODULEMODE_SWCTRL,
2465                 },
2466         },
2467 };
2468
2469 /*
2470  * 'mpu' class
2471  * mpu sub-system
2472  */
2473
2474 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2475         .name   = "mpu",
2476 };
2477
2478 /* mpu */
2479 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2480         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2481         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2482         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2483         { .irq = -1 }
2484 };
2485
2486 static struct omap_hwmod omap44xx_mpu_hwmod = {
2487         .name           = "mpu",
2488         .class          = &omap44xx_mpu_hwmod_class,
2489         .clkdm_name     = "mpuss_clkdm",
2490         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2491         .mpu_irqs       = omap44xx_mpu_irqs,
2492         .main_clk       = "dpll_mpu_m2_ck",
2493         .prcm = {
2494                 .omap4 = {
2495                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2496                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2497                 },
2498         },
2499 };
2500
2501 /*
2502  * 'ocmc_ram' class
2503  * top-level core on-chip ram
2504  */
2505
2506 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2507         .name   = "ocmc_ram",
2508 };
2509
2510 /* ocmc_ram */
2511 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2512         .name           = "ocmc_ram",
2513         .class          = &omap44xx_ocmc_ram_hwmod_class,
2514         .clkdm_name     = "l3_2_clkdm",
2515         .prcm = {
2516                 .omap4 = {
2517                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2518                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2519                 },
2520         },
2521 };
2522
2523 /*
2524  * 'ocp2scp' class
2525  * bridge to transform ocp interface protocol to scp (serial control port)
2526  * protocol
2527  */
2528
2529 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2530         .rev_offs       = 0x0000,
2531         .sysc_offs      = 0x0010,
2532         .syss_offs      = 0x0014,
2533         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2534                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2535         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2536         .sysc_fields    = &omap_hwmod_sysc_type1,
2537 };
2538
2539 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2540         .name   = "ocp2scp",
2541         .sysc   = &omap44xx_ocp2scp_sysc,
2542 };
2543
2544 /* ocp2scp_usb_phy */
2545 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2546         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2547 };
2548
2549 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2550         .name           = "ocp2scp_usb_phy",
2551         .class          = &omap44xx_ocp2scp_hwmod_class,
2552         .clkdm_name     = "l3_init_clkdm",
2553         .prcm = {
2554                 .omap4 = {
2555                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2556                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2557                         .modulemode   = MODULEMODE_HWCTRL,
2558                 },
2559         },
2560         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2561         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2562 };
2563
2564 /*
2565  * 'prcm' class
2566  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2567  * + clock manager 1 (in always on power domain) + local prm in mpu
2568  */
2569
2570 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2571         .name   = "prcm",
2572 };
2573
2574 /* prcm_mpu */
2575 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2576         .name           = "prcm_mpu",
2577         .class          = &omap44xx_prcm_hwmod_class,
2578         .clkdm_name     = "l4_wkup_clkdm",
2579         .prcm = {
2580                 .omap4 = {
2581                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2582                 },
2583         },
2584 };
2585
2586 /* cm_core_aon */
2587 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2588         .name           = "cm_core_aon",
2589         .class          = &omap44xx_prcm_hwmod_class,
2590         .prcm = {
2591                 .omap4 = {
2592                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2593                 },
2594         },
2595 };
2596
2597 /* cm_core */
2598 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2599         .name           = "cm_core",
2600         .class          = &omap44xx_prcm_hwmod_class,
2601         .prcm = {
2602                 .omap4 = {
2603                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2604                 },
2605         },
2606 };
2607
2608 /* prm */
2609 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2610         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2611         { .irq = -1 }
2612 };
2613
2614 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2615         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2616         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2617 };
2618
2619 static struct omap_hwmod omap44xx_prm_hwmod = {
2620         .name           = "prm",
2621         .class          = &omap44xx_prcm_hwmod_class,
2622         .mpu_irqs       = omap44xx_prm_irqs,
2623         .rst_lines      = omap44xx_prm_resets,
2624         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2625 };
2626
2627 /*
2628  * 'scrm' class
2629  * system clock and reset manager
2630  */
2631
2632 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2633         .name   = "scrm",
2634 };
2635
2636 /* scrm */
2637 static struct omap_hwmod omap44xx_scrm_hwmod = {
2638         .name           = "scrm",
2639         .class          = &omap44xx_scrm_hwmod_class,
2640         .clkdm_name     = "l4_wkup_clkdm",
2641         .prcm = {
2642                 .omap4 = {
2643                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2644                 },
2645         },
2646 };
2647
2648 /*
2649  * 'sl2if' class
2650  * shared level 2 memory interface
2651  */
2652
2653 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2654         .name   = "sl2if",
2655 };
2656
2657 /* sl2if */
2658 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2659         .name           = "sl2if",
2660         .class          = &omap44xx_sl2if_hwmod_class,
2661         .clkdm_name     = "ivahd_clkdm",
2662         .prcm = {
2663                 .omap4 = {
2664                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2665                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2666                         .modulemode   = MODULEMODE_HWCTRL,
2667                 },
2668         },
2669 };
2670
2671 /*
2672  * 'slimbus' class
2673  * bidirectional, multi-drop, multi-channel two-line serial interface between
2674  * the device and external components
2675  */
2676
2677 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2678         .rev_offs       = 0x0000,
2679         .sysc_offs      = 0x0010,
2680         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2681                            SYSC_HAS_SOFTRESET),
2682         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2683                            SIDLE_SMART_WKUP),
2684         .sysc_fields    = &omap_hwmod_sysc_type2,
2685 };
2686
2687 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2688         .name   = "slimbus",
2689         .sysc   = &omap44xx_slimbus_sysc,
2690 };
2691
2692 /* slimbus1 */
2693 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2694         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2695         { .irq = -1 }
2696 };
2697
2698 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2699         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2700         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2701         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2702         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2703         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2704         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2705         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2706         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2707         { .dma_req = -1 }
2708 };
2709
2710 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2711         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2712         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2713         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2714         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2715 };
2716
2717 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2718         .name           = "slimbus1",
2719         .class          = &omap44xx_slimbus_hwmod_class,
2720         .clkdm_name     = "abe_clkdm",
2721         .mpu_irqs       = omap44xx_slimbus1_irqs,
2722         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2723         .prcm = {
2724                 .omap4 = {
2725                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2726                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2727                         .modulemode   = MODULEMODE_SWCTRL,
2728                 },
2729         },
2730         .opt_clks       = slimbus1_opt_clks,
2731         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2732 };
2733
2734 /* slimbus2 */
2735 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2736         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2737         { .irq = -1 }
2738 };
2739
2740 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2741         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2742         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2743         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2744         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2745         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2746         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2747         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2748         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2749         { .dma_req = -1 }
2750 };
2751
2752 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2753         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2754         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2755         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2756 };
2757
2758 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2759         .name           = "slimbus2",
2760         .class          = &omap44xx_slimbus_hwmod_class,
2761         .clkdm_name     = "l4_per_clkdm",
2762         .mpu_irqs       = omap44xx_slimbus2_irqs,
2763         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2764         .prcm = {
2765                 .omap4 = {
2766                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2767                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2768                         .modulemode   = MODULEMODE_SWCTRL,
2769                 },
2770         },
2771         .opt_clks       = slimbus2_opt_clks,
2772         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2773 };
2774
2775 /*
2776  * 'smartreflex' class
2777  * smartreflex module (monitor silicon performance and outputs a measure of
2778  * performance error)
2779  */
2780
2781 /* The IP is not compliant to type1 / type2 scheme */
2782 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2783         .sidle_shift    = 24,
2784         .enwkup_shift   = 26,
2785 };
2786
2787 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2788         .sysc_offs      = 0x0038,
2789         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2790         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2791                            SIDLE_SMART_WKUP),
2792         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2793 };
2794
2795 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2796         .name   = "smartreflex",
2797         .sysc   = &omap44xx_smartreflex_sysc,
2798         .rev    = 2,
2799 };
2800
2801 /* smartreflex_core */
2802 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2803         .sensor_voltdm_name   = "core",
2804 };
2805
2806 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2807         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2808         { .irq = -1 }
2809 };
2810
2811 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2812         .name           = "smartreflex_core",
2813         .class          = &omap44xx_smartreflex_hwmod_class,
2814         .clkdm_name     = "l4_ao_clkdm",
2815         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2816
2817         .main_clk       = "smartreflex_core_fck",
2818         .prcm = {
2819                 .omap4 = {
2820                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2821                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2822                         .modulemode   = MODULEMODE_SWCTRL,
2823                 },
2824         },
2825         .dev_attr       = &smartreflex_core_dev_attr,
2826 };
2827
2828 /* smartreflex_iva */
2829 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2830         .sensor_voltdm_name     = "iva",
2831 };
2832
2833 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2834         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2835         { .irq = -1 }
2836 };
2837
2838 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2839         .name           = "smartreflex_iva",
2840         .class          = &omap44xx_smartreflex_hwmod_class,
2841         .clkdm_name     = "l4_ao_clkdm",
2842         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2843         .main_clk       = "smartreflex_iva_fck",
2844         .prcm = {
2845                 .omap4 = {
2846                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2847                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2848                         .modulemode   = MODULEMODE_SWCTRL,
2849                 },
2850         },
2851         .dev_attr       = &smartreflex_iva_dev_attr,
2852 };
2853
2854 /* smartreflex_mpu */
2855 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2856         .sensor_voltdm_name     = "mpu",
2857 };
2858
2859 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2860         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2861         { .irq = -1 }
2862 };
2863
2864 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2865         .name           = "smartreflex_mpu",
2866         .class          = &omap44xx_smartreflex_hwmod_class,
2867         .clkdm_name     = "l4_ao_clkdm",
2868         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2869         .main_clk       = "smartreflex_mpu_fck",
2870         .prcm = {
2871                 .omap4 = {
2872                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2873                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2874                         .modulemode   = MODULEMODE_SWCTRL,
2875                 },
2876         },
2877         .dev_attr       = &smartreflex_mpu_dev_attr,
2878 };
2879
2880 /*
2881  * 'spinlock' class
2882  * spinlock provides hardware assistance for synchronizing the processes
2883  * running on multiple processors
2884  */
2885
2886 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2887         .rev_offs       = 0x0000,
2888         .sysc_offs      = 0x0010,
2889         .syss_offs      = 0x0014,
2890         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2891                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2892                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2893         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2894                            SIDLE_SMART_WKUP),
2895         .sysc_fields    = &omap_hwmod_sysc_type1,
2896 };
2897
2898 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2899         .name   = "spinlock",
2900         .sysc   = &omap44xx_spinlock_sysc,
2901 };
2902
2903 /* spinlock */
2904 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2905         .name           = "spinlock",
2906         .class          = &omap44xx_spinlock_hwmod_class,
2907         .clkdm_name     = "l4_cfg_clkdm",
2908         .prcm = {
2909                 .omap4 = {
2910                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2911                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2912                 },
2913         },
2914 };
2915
2916 /*
2917  * 'timer' class
2918  * general purpose timer module with accurate 1ms tick
2919  * This class contains several variants: ['timer_1ms', 'timer']
2920  */
2921
2922 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2923         .rev_offs       = 0x0000,
2924         .sysc_offs      = 0x0010,
2925         .syss_offs      = 0x0014,
2926         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2927                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2928                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2929                            SYSS_HAS_RESET_STATUS),
2930         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2931         .sysc_fields    = &omap_hwmod_sysc_type1,
2932 };
2933
2934 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2935         .name   = "timer",
2936         .sysc   = &omap44xx_timer_1ms_sysc,
2937 };
2938
2939 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2940         .rev_offs       = 0x0000,
2941         .sysc_offs      = 0x0010,
2942         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2943                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2944         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2945                            SIDLE_SMART_WKUP),
2946         .sysc_fields    = &omap_hwmod_sysc_type2,
2947 };
2948
2949 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2950         .name   = "timer",
2951         .sysc   = &omap44xx_timer_sysc,
2952 };
2953
2954 /* always-on timers dev attribute */
2955 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2956         .timer_capability       = OMAP_TIMER_ALWON,
2957 };
2958
2959 /* pwm timers dev attribute */
2960 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2961         .timer_capability       = OMAP_TIMER_HAS_PWM,
2962 };
2963
2964 /* timer1 */
2965 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2966         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2967         { .irq = -1 }
2968 };
2969
2970 static struct omap_hwmod omap44xx_timer1_hwmod = {
2971         .name           = "timer1",
2972         .class          = &omap44xx_timer_1ms_hwmod_class,
2973         .clkdm_name     = "l4_wkup_clkdm",
2974         .mpu_irqs       = omap44xx_timer1_irqs,
2975         .main_clk       = "timer1_fck",
2976         .prcm = {
2977                 .omap4 = {
2978                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2979                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2980                         .modulemode   = MODULEMODE_SWCTRL,
2981                 },
2982         },
2983         .dev_attr       = &capability_alwon_dev_attr,
2984 };
2985
2986 /* timer2 */
2987 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2988         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2989         { .irq = -1 }
2990 };
2991
2992 static struct omap_hwmod omap44xx_timer2_hwmod = {
2993         .name           = "timer2",
2994         .class          = &omap44xx_timer_1ms_hwmod_class,
2995         .clkdm_name     = "l4_per_clkdm",
2996         .mpu_irqs       = omap44xx_timer2_irqs,
2997         .main_clk       = "timer2_fck",
2998         .prcm = {
2999                 .omap4 = {
3000                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3001                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3002                         .modulemode   = MODULEMODE_SWCTRL,
3003                 },
3004         },
3005 };
3006
3007 /* timer3 */
3008 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3009         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3010         { .irq = -1 }
3011 };
3012
3013 static struct omap_hwmod omap44xx_timer3_hwmod = {
3014         .name           = "timer3",
3015         .class          = &omap44xx_timer_hwmod_class,
3016         .clkdm_name     = "l4_per_clkdm",
3017         .mpu_irqs       = omap44xx_timer3_irqs,
3018         .main_clk       = "timer3_fck",
3019         .prcm = {
3020                 .omap4 = {
3021                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3022                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3023                         .modulemode   = MODULEMODE_SWCTRL,
3024                 },
3025         },
3026 };
3027
3028 /* timer4 */
3029 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3030         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3031         { .irq = -1 }
3032 };
3033
3034 static struct omap_hwmod omap44xx_timer4_hwmod = {
3035         .name           = "timer4",
3036         .class          = &omap44xx_timer_hwmod_class,
3037         .clkdm_name     = "l4_per_clkdm",
3038         .mpu_irqs       = omap44xx_timer4_irqs,
3039         .main_clk       = "timer4_fck",
3040         .prcm = {
3041                 .omap4 = {
3042                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3043                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3044                         .modulemode   = MODULEMODE_SWCTRL,
3045                 },
3046         },
3047 };
3048
3049 /* timer5 */
3050 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3051         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3052         { .irq = -1 }
3053 };
3054
3055 static struct omap_hwmod omap44xx_timer5_hwmod = {
3056         .name           = "timer5",
3057         .class          = &omap44xx_timer_hwmod_class,
3058         .clkdm_name     = "abe_clkdm",
3059         .mpu_irqs       = omap44xx_timer5_irqs,
3060         .main_clk       = "timer5_fck",
3061         .prcm = {
3062                 .omap4 = {
3063                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3064                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3065                         .modulemode   = MODULEMODE_SWCTRL,
3066                 },
3067         },
3068 };
3069
3070 /* timer6 */
3071 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3072         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3073         { .irq = -1 }
3074 };
3075
3076 static struct omap_hwmod omap44xx_timer6_hwmod = {
3077         .name           = "timer6",
3078         .class          = &omap44xx_timer_hwmod_class,
3079         .clkdm_name     = "abe_clkdm",
3080         .mpu_irqs       = omap44xx_timer6_irqs,
3081
3082         .main_clk       = "timer6_fck",
3083         .prcm = {
3084                 .omap4 = {
3085                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3086                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3087                         .modulemode   = MODULEMODE_SWCTRL,
3088                 },
3089         },
3090 };
3091
3092 /* timer7 */
3093 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3094         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3095         { .irq = -1 }
3096 };
3097
3098 static struct omap_hwmod omap44xx_timer7_hwmod = {
3099         .name           = "timer7",
3100         .class          = &omap44xx_timer_hwmod_class,
3101         .clkdm_name     = "abe_clkdm",
3102         .mpu_irqs       = omap44xx_timer7_irqs,
3103         .main_clk       = "timer7_fck",
3104         .prcm = {
3105                 .omap4 = {
3106                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3107                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3108                         .modulemode   = MODULEMODE_SWCTRL,
3109                 },
3110         },
3111 };
3112
3113 /* timer8 */
3114 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3115         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3116         { .irq = -1 }
3117 };
3118
3119 static struct omap_hwmod omap44xx_timer8_hwmod = {
3120         .name           = "timer8",
3121         .class          = &omap44xx_timer_hwmod_class,
3122         .clkdm_name     = "abe_clkdm",
3123         .mpu_irqs       = omap44xx_timer8_irqs,
3124         .main_clk       = "timer8_fck",
3125         .prcm = {
3126                 .omap4 = {
3127                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3128                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3129                         .modulemode   = MODULEMODE_SWCTRL,
3130                 },
3131         },
3132         .dev_attr       = &capability_pwm_dev_attr,
3133 };
3134
3135 /* timer9 */
3136 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3137         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3138         { .irq = -1 }
3139 };
3140
3141 static struct omap_hwmod omap44xx_timer9_hwmod = {
3142         .name           = "timer9",
3143         .class          = &omap44xx_timer_hwmod_class,
3144         .clkdm_name     = "l4_per_clkdm",
3145         .mpu_irqs       = omap44xx_timer9_irqs,
3146         .main_clk       = "timer9_fck",
3147         .prcm = {
3148                 .omap4 = {
3149                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3150                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3151                         .modulemode   = MODULEMODE_SWCTRL,
3152                 },
3153         },
3154         .dev_attr       = &capability_pwm_dev_attr,
3155 };
3156
3157 /* timer10 */
3158 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3159         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3160         { .irq = -1 }
3161 };
3162
3163 static struct omap_hwmod omap44xx_timer10_hwmod = {
3164         .name           = "timer10",
3165         .class          = &omap44xx_timer_1ms_hwmod_class,
3166         .clkdm_name     = "l4_per_clkdm",
3167         .mpu_irqs       = omap44xx_timer10_irqs,
3168         .main_clk       = "timer10_fck",
3169         .prcm = {
3170                 .omap4 = {
3171                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3172                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3173                         .modulemode   = MODULEMODE_SWCTRL,
3174                 },
3175         },
3176         .dev_attr       = &capability_pwm_dev_attr,
3177 };
3178
3179 /* timer11 */
3180 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3181         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3182         { .irq = -1 }
3183 };
3184
3185 static struct omap_hwmod omap44xx_timer11_hwmod = {
3186         .name           = "timer11",
3187         .class          = &omap44xx_timer_hwmod_class,
3188         .clkdm_name     = "l4_per_clkdm",
3189         .mpu_irqs       = omap44xx_timer11_irqs,
3190         .main_clk       = "timer11_fck",
3191         .prcm = {
3192                 .omap4 = {
3193                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3194                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3195                         .modulemode   = MODULEMODE_SWCTRL,
3196                 },
3197         },
3198         .dev_attr       = &capability_pwm_dev_attr,
3199 };
3200
3201 /*
3202  * 'uart' class
3203  * universal asynchronous receiver/transmitter (uart)
3204  */
3205
3206 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3207         .rev_offs       = 0x0050,
3208         .sysc_offs      = 0x0054,
3209         .syss_offs      = 0x0058,
3210         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3211                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3212                            SYSS_HAS_RESET_STATUS),
3213         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3214                            SIDLE_SMART_WKUP),
3215         .sysc_fields    = &omap_hwmod_sysc_type1,
3216 };
3217
3218 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3219         .name   = "uart",
3220         .sysc   = &omap44xx_uart_sysc,
3221 };
3222
3223 /* uart1 */
3224 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3225         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3226         { .irq = -1 }
3227 };
3228
3229 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3230         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3231         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3232         { .dma_req = -1 }
3233 };
3234
3235 static struct omap_hwmod omap44xx_uart1_hwmod = {
3236         .name           = "uart1",
3237         .class          = &omap44xx_uart_hwmod_class,
3238         .clkdm_name     = "l4_per_clkdm",
3239         .mpu_irqs       = omap44xx_uart1_irqs,
3240         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3241         .main_clk       = "uart1_fck",
3242         .prcm = {
3243                 .omap4 = {
3244                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3245                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3246                         .modulemode   = MODULEMODE_SWCTRL,
3247                 },
3248         },
3249 };
3250
3251 /* uart2 */
3252 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3253         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3254         { .irq = -1 }
3255 };
3256
3257 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3258         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3259         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3260         { .dma_req = -1 }
3261 };
3262
3263 static struct omap_hwmod omap44xx_uart2_hwmod = {
3264         .name           = "uart2",
3265         .class          = &omap44xx_uart_hwmod_class,
3266         .clkdm_name     = "l4_per_clkdm",
3267         .mpu_irqs       = omap44xx_uart2_irqs,
3268         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3269         .main_clk       = "uart2_fck",
3270         .prcm = {
3271                 .omap4 = {
3272                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3273                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3274                         .modulemode   = MODULEMODE_SWCTRL,
3275                 },
3276         },
3277 };
3278
3279 /* uart3 */
3280 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3281         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3282         { .irq = -1 }
3283 };
3284
3285 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3286         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3287         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3288         { .dma_req = -1 }
3289 };
3290
3291 static struct omap_hwmod omap44xx_uart3_hwmod = {
3292         .name           = "uart3",
3293         .class          = &omap44xx_uart_hwmod_class,
3294         .clkdm_name     = "l4_per_clkdm",
3295         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3296         .mpu_irqs       = omap44xx_uart3_irqs,
3297         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3298         .main_clk       = "uart3_fck",
3299         .prcm = {
3300                 .omap4 = {
3301                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3302                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3303                         .modulemode   = MODULEMODE_SWCTRL,
3304                 },
3305         },
3306 };
3307
3308 /* uart4 */
3309 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3310         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3311         { .irq = -1 }
3312 };
3313
3314 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3315         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3316         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3317         { .dma_req = -1 }
3318 };
3319
3320 static struct omap_hwmod omap44xx_uart4_hwmod = {
3321         .name           = "uart4",
3322         .class          = &omap44xx_uart_hwmod_class,
3323         .clkdm_name     = "l4_per_clkdm",
3324         .mpu_irqs       = omap44xx_uart4_irqs,
3325         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3326         .main_clk       = "uart4_fck",
3327         .prcm = {
3328                 .omap4 = {
3329                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3330                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3331                         .modulemode   = MODULEMODE_SWCTRL,
3332                 },
3333         },
3334 };
3335
3336 /*
3337  * 'usb_host_fs' class
3338  * full-speed usb host controller
3339  */
3340
3341 /* The IP is not compliant to type1 / type2 scheme */
3342 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3343         .midle_shift    = 4,
3344         .sidle_shift    = 2,
3345         .srst_shift     = 1,
3346 };
3347
3348 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3349         .rev_offs       = 0x0000,
3350         .sysc_offs      = 0x0210,
3351         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3352                            SYSC_HAS_SOFTRESET),
3353         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3354                            SIDLE_SMART_WKUP),
3355         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3356 };
3357
3358 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3359         .name   = "usb_host_fs",
3360         .sysc   = &omap44xx_usb_host_fs_sysc,
3361 };
3362
3363 /* usb_host_fs */
3364 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3365         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3366         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3367         { .irq = -1 }
3368 };
3369
3370 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3371         .name           = "usb_host_fs",
3372         .class          = &omap44xx_usb_host_fs_hwmod_class,
3373         .clkdm_name     = "l3_init_clkdm",
3374         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3375         .main_clk       = "usb_host_fs_fck",
3376         .prcm = {
3377                 .omap4 = {
3378                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3379                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3380                         .modulemode   = MODULEMODE_SWCTRL,
3381                 },
3382         },
3383 };
3384
3385 /*
3386  * 'usb_host_hs' class
3387  * high-speed multi-port usb host controller
3388  */
3389
3390 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3391         .rev_offs       = 0x0000,
3392         .sysc_offs      = 0x0010,
3393         .syss_offs      = 0x0014,
3394         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3395                            SYSC_HAS_SOFTRESET),
3396         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3397                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3398                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3399         .sysc_fields    = &omap_hwmod_sysc_type2,
3400 };
3401
3402 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3403         .name   = "usb_host_hs",
3404         .sysc   = &omap44xx_usb_host_hs_sysc,
3405 };
3406
3407 /* usb_host_hs */
3408 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3409         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3410         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3411         { .irq = -1 }
3412 };
3413
3414 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3415         .name           = "usb_host_hs",
3416         .class          = &omap44xx_usb_host_hs_hwmod_class,
3417         .clkdm_name     = "l3_init_clkdm",
3418         .main_clk       = "usb_host_hs_fck",
3419         .prcm = {
3420                 .omap4 = {
3421                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3422                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3423                         .modulemode   = MODULEMODE_SWCTRL,
3424                 },
3425         },
3426         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3427
3428         /*
3429          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3430          * id: i660
3431          *
3432          * Description:
3433          * In the following configuration :
3434          * - USBHOST module is set to smart-idle mode
3435          * - PRCM asserts idle_req to the USBHOST module ( This typically
3436          *   happens when the system is going to a low power mode : all ports
3437          *   have been suspended, the master part of the USBHOST module has
3438          *   entered the standby state, and SW has cut the functional clocks)
3439          * - an USBHOST interrupt occurs before the module is able to answer
3440          *   idle_ack, typically a remote wakeup IRQ.
3441          * Then the USB HOST module will enter a deadlock situation where it
3442          * is no more accessible nor functional.
3443          *
3444          * Workaround:
3445          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3446          */
3447
3448         /*
3449          * Errata: USB host EHCI may stall when entering smart-standby mode
3450          * Id: i571
3451          *
3452          * Description:
3453          * When the USBHOST module is set to smart-standby mode, and when it is
3454          * ready to enter the standby state (i.e. all ports are suspended and
3455          * all attached devices are in suspend mode), then it can wrongly assert
3456          * the Mstandby signal too early while there are still some residual OCP
3457          * transactions ongoing. If this condition occurs, the internal state
3458          * machine may go to an undefined state and the USB link may be stuck
3459          * upon the next resume.
3460          *
3461          * Workaround:
3462          * Don't use smart standby; use only force standby,
3463          * hence HWMOD_SWSUP_MSTANDBY
3464          */
3465
3466         /*
3467          * During system boot; If the hwmod framework resets the module
3468          * the module will have smart idle settings; which can lead to deadlock
3469          * (above Errata Id:i660); so, dont reset the module during boot;
3470          * Use HWMOD_INIT_NO_RESET.
3471          */
3472
3473         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3474                           HWMOD_INIT_NO_RESET,
3475 };
3476
3477 /*
3478  * 'usb_otg_hs' class
3479  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3480  */
3481
3482 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3483         .rev_offs       = 0x0400,
3484         .sysc_offs      = 0x0404,
3485         .syss_offs      = 0x0408,
3486         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3487                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3488                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3489         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3490                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3491                            MSTANDBY_SMART),
3492         .sysc_fields    = &omap_hwmod_sysc_type1,
3493 };
3494
3495 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3496         .name   = "usb_otg_hs",
3497         .sysc   = &omap44xx_usb_otg_hs_sysc,
3498 };
3499
3500 /* usb_otg_hs */
3501 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3502         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3503         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3504         { .irq = -1 }
3505 };
3506
3507 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3508         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3509 };
3510
3511 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3512         .name           = "usb_otg_hs",
3513         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3514         .clkdm_name     = "l3_init_clkdm",
3515         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3516         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3517         .main_clk       = "usb_otg_hs_ick",
3518         .prcm = {
3519                 .omap4 = {
3520                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3521                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3522                         .modulemode   = MODULEMODE_HWCTRL,
3523                 },
3524         },
3525         .opt_clks       = usb_otg_hs_opt_clks,
3526         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3527 };
3528
3529 /*
3530  * 'usb_tll_hs' class
3531  * usb_tll_hs module is the adapter on the usb_host_hs ports
3532  */
3533
3534 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3535         .rev_offs       = 0x0000,
3536         .sysc_offs      = 0x0010,
3537         .syss_offs      = 0x0014,
3538         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3539                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3540                            SYSC_HAS_AUTOIDLE),
3541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3542         .sysc_fields    = &omap_hwmod_sysc_type1,
3543 };
3544
3545 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3546         .name   = "usb_tll_hs",
3547         .sysc   = &omap44xx_usb_tll_hs_sysc,
3548 };
3549
3550 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3551         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3552         { .irq = -1 }
3553 };
3554
3555 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3556         .name           = "usb_tll_hs",
3557         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3558         .clkdm_name     = "l3_init_clkdm",
3559         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3560         .main_clk       = "usb_tll_hs_ick",
3561         .prcm = {
3562                 .omap4 = {
3563                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3564                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3565                         .modulemode   = MODULEMODE_HWCTRL,
3566                 },
3567         },
3568 };
3569
3570 /*
3571  * 'wd_timer' class
3572  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3573  * overflow condition
3574  */
3575
3576 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3577         .rev_offs       = 0x0000,
3578         .sysc_offs      = 0x0010,
3579         .syss_offs      = 0x0014,
3580         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3581                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3582         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3583                            SIDLE_SMART_WKUP),
3584         .sysc_fields    = &omap_hwmod_sysc_type1,
3585 };
3586
3587 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3588         .name           = "wd_timer",
3589         .sysc           = &omap44xx_wd_timer_sysc,
3590         .pre_shutdown   = &omap2_wd_timer_disable,
3591         .reset          = &omap2_wd_timer_reset,
3592 };
3593
3594 /* wd_timer2 */
3595 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3596         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3597         { .irq = -1 }
3598 };
3599
3600 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3601         .name           = "wd_timer2",
3602         .class          = &omap44xx_wd_timer_hwmod_class,
3603         .clkdm_name     = "l4_wkup_clkdm",
3604         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3605         .main_clk       = "wd_timer2_fck",
3606         .prcm = {
3607                 .omap4 = {
3608                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3609                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3610                         .modulemode   = MODULEMODE_SWCTRL,
3611                 },
3612         },
3613 };
3614
3615 /* wd_timer3 */
3616 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3617         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3618         { .irq = -1 }
3619 };
3620
3621 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3622         .name           = "wd_timer3",
3623         .class          = &omap44xx_wd_timer_hwmod_class,
3624         .clkdm_name     = "abe_clkdm",
3625         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3626         .main_clk       = "wd_timer3_fck",
3627         .prcm = {
3628                 .omap4 = {
3629                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3630                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3631                         .modulemode   = MODULEMODE_SWCTRL,
3632                 },
3633         },
3634 };
3635
3636
3637 /*
3638  * interfaces
3639  */
3640
3641 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3642         {
3643                 .pa_start       = 0x4a204000,
3644                 .pa_end         = 0x4a2040ff,
3645                 .flags          = ADDR_TYPE_RT
3646         },
3647         { }
3648 };
3649
3650 /* c2c -> c2c_target_fw */
3651 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3652         .master         = &omap44xx_c2c_hwmod,
3653         .slave          = &omap44xx_c2c_target_fw_hwmod,
3654         .clk            = "div_core_ck",
3655         .addr           = omap44xx_c2c_target_fw_addrs,
3656         .user           = OCP_USER_MPU,
3657 };
3658
3659 /* l4_cfg -> c2c_target_fw */
3660 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3661         .master         = &omap44xx_l4_cfg_hwmod,
3662         .slave          = &omap44xx_c2c_target_fw_hwmod,
3663         .clk            = "l4_div_ck",
3664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3665 };
3666
3667 /* l3_main_1 -> dmm */
3668 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3669         .master         = &omap44xx_l3_main_1_hwmod,
3670         .slave          = &omap44xx_dmm_hwmod,
3671         .clk            = "l3_div_ck",
3672         .user           = OCP_USER_SDMA,
3673 };
3674
3675 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3676         {
3677                 .pa_start       = 0x4e000000,
3678                 .pa_end         = 0x4e0007ff,
3679                 .flags          = ADDR_TYPE_RT
3680         },
3681         { }
3682 };
3683
3684 /* mpu -> dmm */
3685 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3686         .master         = &omap44xx_mpu_hwmod,
3687         .slave          = &omap44xx_dmm_hwmod,
3688         .clk            = "l3_div_ck",
3689         .addr           = omap44xx_dmm_addrs,
3690         .user           = OCP_USER_MPU,
3691 };
3692
3693 /* c2c -> emif_fw */
3694 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3695         .master         = &omap44xx_c2c_hwmod,
3696         .slave          = &omap44xx_emif_fw_hwmod,
3697         .clk            = "div_core_ck",
3698         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3699 };
3700
3701 /* dmm -> emif_fw */
3702 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3703         .master         = &omap44xx_dmm_hwmod,
3704         .slave          = &omap44xx_emif_fw_hwmod,
3705         .clk            = "l3_div_ck",
3706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3707 };
3708
3709 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3710         {
3711                 .pa_start       = 0x4a20c000,
3712                 .pa_end         = 0x4a20c0ff,
3713                 .flags          = ADDR_TYPE_RT
3714         },
3715         { }
3716 };
3717
3718 /* l4_cfg -> emif_fw */
3719 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3720         .master         = &omap44xx_l4_cfg_hwmod,
3721         .slave          = &omap44xx_emif_fw_hwmod,
3722         .clk            = "l4_div_ck",
3723         .addr           = omap44xx_emif_fw_addrs,
3724         .user           = OCP_USER_MPU,
3725 };
3726
3727 /* iva -> l3_instr */
3728 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3729         .master         = &omap44xx_iva_hwmod,
3730         .slave          = &omap44xx_l3_instr_hwmod,
3731         .clk            = "l3_div_ck",
3732         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3733 };
3734
3735 /* l3_main_3 -> l3_instr */
3736 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3737         .master         = &omap44xx_l3_main_3_hwmod,
3738         .slave          = &omap44xx_l3_instr_hwmod,
3739         .clk            = "l3_div_ck",
3740         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3741 };
3742
3743 /* ocp_wp_noc -> l3_instr */
3744 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3745         .master         = &omap44xx_ocp_wp_noc_hwmod,
3746         .slave          = &omap44xx_l3_instr_hwmod,
3747         .clk            = "l3_div_ck",
3748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3749 };
3750
3751 /* dsp -> l3_main_1 */
3752 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3753         .master         = &omap44xx_dsp_hwmod,
3754         .slave          = &omap44xx_l3_main_1_hwmod,
3755         .clk            = "l3_div_ck",
3756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3757 };
3758
3759 /* dss -> l3_main_1 */
3760 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3761         .master         = &omap44xx_dss_hwmod,
3762         .slave          = &omap44xx_l3_main_1_hwmod,
3763         .clk            = "l3_div_ck",
3764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3765 };
3766
3767 /* l3_main_2 -> l3_main_1 */
3768 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3769         .master         = &omap44xx_l3_main_2_hwmod,
3770         .slave          = &omap44xx_l3_main_1_hwmod,
3771         .clk            = "l3_div_ck",
3772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3773 };
3774
3775 /* l4_cfg -> l3_main_1 */
3776 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3777         .master         = &omap44xx_l4_cfg_hwmod,
3778         .slave          = &omap44xx_l3_main_1_hwmod,
3779         .clk            = "l4_div_ck",
3780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3781 };
3782
3783 /* mmc1 -> l3_main_1 */
3784 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3785         .master         = &omap44xx_mmc1_hwmod,
3786         .slave          = &omap44xx_l3_main_1_hwmod,
3787         .clk            = "l3_div_ck",
3788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3789 };
3790
3791 /* mmc2 -> l3_main_1 */
3792 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3793         .master         = &omap44xx_mmc2_hwmod,
3794         .slave          = &omap44xx_l3_main_1_hwmod,
3795         .clk            = "l3_div_ck",
3796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3797 };
3798
3799 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3800         {
3801                 .pa_start       = 0x44000000,
3802                 .pa_end         = 0x44000fff,
3803                 .flags          = ADDR_TYPE_RT
3804         },
3805         { }
3806 };
3807
3808 /* mpu -> l3_main_1 */
3809 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3810         .master         = &omap44xx_mpu_hwmod,
3811         .slave          = &omap44xx_l3_main_1_hwmod,
3812         .clk            = "l3_div_ck",
3813         .addr           = omap44xx_l3_main_1_addrs,
3814         .user           = OCP_USER_MPU,
3815 };
3816
3817 /* c2c_target_fw -> l3_main_2 */
3818 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3819         .master         = &omap44xx_c2c_target_fw_hwmod,
3820         .slave          = &omap44xx_l3_main_2_hwmod,
3821         .clk            = "l3_div_ck",
3822         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3823 };
3824
3825 /* debugss -> l3_main_2 */
3826 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3827         .master         = &omap44xx_debugss_hwmod,
3828         .slave          = &omap44xx_l3_main_2_hwmod,
3829         .clk            = "dbgclk_mux_ck",
3830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3831 };
3832
3833 /* dma_system -> l3_main_2 */
3834 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3835         .master         = &omap44xx_dma_system_hwmod,
3836         .slave          = &omap44xx_l3_main_2_hwmod,
3837         .clk            = "l3_div_ck",
3838         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3839 };
3840
3841 /* fdif -> l3_main_2 */
3842 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3843         .master         = &omap44xx_fdif_hwmod,
3844         .slave          = &omap44xx_l3_main_2_hwmod,
3845         .clk            = "l3_div_ck",
3846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3847 };
3848
3849 /* gpu -> l3_main_2 */
3850 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3851         .master         = &omap44xx_gpu_hwmod,
3852         .slave          = &omap44xx_l3_main_2_hwmod,
3853         .clk            = "l3_div_ck",
3854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3855 };
3856
3857 /* hsi -> l3_main_2 */
3858 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3859         .master         = &omap44xx_hsi_hwmod,
3860         .slave          = &omap44xx_l3_main_2_hwmod,
3861         .clk            = "l3_div_ck",
3862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3863 };
3864
3865 /* ipu -> l3_main_2 */
3866 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3867         .master         = &omap44xx_ipu_hwmod,
3868         .slave          = &omap44xx_l3_main_2_hwmod,
3869         .clk            = "l3_div_ck",
3870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3871 };
3872
3873 /* iss -> l3_main_2 */
3874 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3875         .master         = &omap44xx_iss_hwmod,
3876         .slave          = &omap44xx_l3_main_2_hwmod,
3877         .clk            = "l3_div_ck",
3878         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3879 };
3880
3881 /* iva -> l3_main_2 */
3882 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3883         .master         = &omap44xx_iva_hwmod,
3884         .slave          = &omap44xx_l3_main_2_hwmod,
3885         .clk            = "l3_div_ck",
3886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3887 };
3888
3889 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3890         {
3891                 .pa_start       = 0x44800000,
3892                 .pa_end         = 0x44801fff,
3893                 .flags          = ADDR_TYPE_RT
3894         },
3895         { }
3896 };
3897
3898 /* l3_main_1 -> l3_main_2 */
3899 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3900         .master         = &omap44xx_l3_main_1_hwmod,
3901         .slave          = &omap44xx_l3_main_2_hwmod,
3902         .clk            = "l3_div_ck",
3903         .addr           = omap44xx_l3_main_2_addrs,
3904         .user           = OCP_USER_MPU,
3905 };
3906
3907 /* l4_cfg -> l3_main_2 */
3908 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3909         .master         = &omap44xx_l4_cfg_hwmod,
3910         .slave          = &omap44xx_l3_main_2_hwmod,
3911         .clk            = "l4_div_ck",
3912         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3913 };
3914
3915 /* usb_host_fs -> l3_main_2 */
3916 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3917         .master         = &omap44xx_usb_host_fs_hwmod,
3918         .slave          = &omap44xx_l3_main_2_hwmod,
3919         .clk            = "l3_div_ck",
3920         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3921 };
3922
3923 /* usb_host_hs -> l3_main_2 */
3924 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3925         .master         = &omap44xx_usb_host_hs_hwmod,
3926         .slave          = &omap44xx_l3_main_2_hwmod,
3927         .clk            = "l3_div_ck",
3928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3929 };
3930
3931 /* usb_otg_hs -> l3_main_2 */
3932 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3933         .master         = &omap44xx_usb_otg_hs_hwmod,
3934         .slave          = &omap44xx_l3_main_2_hwmod,
3935         .clk            = "l3_div_ck",
3936         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3937 };
3938
3939 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3940         {
3941                 .pa_start       = 0x45000000,
3942                 .pa_end         = 0x45000fff,
3943                 .flags          = ADDR_TYPE_RT
3944         },
3945         { }
3946 };
3947
3948 /* l3_main_1 -> l3_main_3 */
3949 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3950         .master         = &omap44xx_l3_main_1_hwmod,
3951         .slave          = &omap44xx_l3_main_3_hwmod,
3952         .clk            = "l3_div_ck",
3953         .addr           = omap44xx_l3_main_3_addrs,
3954         .user           = OCP_USER_MPU,
3955 };
3956
3957 /* l3_main_2 -> l3_main_3 */
3958 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3959         .master         = &omap44xx_l3_main_2_hwmod,
3960         .slave          = &omap44xx_l3_main_3_hwmod,
3961         .clk            = "l3_div_ck",
3962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3963 };
3964
3965 /* l4_cfg -> l3_main_3 */
3966 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3967         .master         = &omap44xx_l4_cfg_hwmod,
3968         .slave          = &omap44xx_l3_main_3_hwmod,
3969         .clk            = "l4_div_ck",
3970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3971 };
3972
3973 /* aess -> l4_abe */
3974 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3975         .master         = &omap44xx_aess_hwmod,
3976         .slave          = &omap44xx_l4_abe_hwmod,
3977         .clk            = "ocp_abe_iclk",
3978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3979 };
3980
3981 /* dsp -> l4_abe */
3982 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3983         .master         = &omap44xx_dsp_hwmod,
3984         .slave          = &omap44xx_l4_abe_hwmod,
3985         .clk            = "ocp_abe_iclk",
3986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3987 };
3988
3989 /* l3_main_1 -> l4_abe */
3990 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3991         .master         = &omap44xx_l3_main_1_hwmod,
3992         .slave          = &omap44xx_l4_abe_hwmod,
3993         .clk            = "l3_div_ck",
3994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3995 };
3996
3997 /* mpu -> l4_abe */
3998 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3999         .master         = &omap44xx_mpu_hwmod,
4000         .slave          = &omap44xx_l4_abe_hwmod,
4001         .clk            = "ocp_abe_iclk",
4002         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4003 };
4004
4005 /* l3_main_1 -> l4_cfg */
4006 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4007         .master         = &omap44xx_l3_main_1_hwmod,
4008         .slave          = &omap44xx_l4_cfg_hwmod,
4009         .clk            = "l3_div_ck",
4010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4011 };
4012
4013 /* l3_main_2 -> l4_per */
4014 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4015         .master         = &omap44xx_l3_main_2_hwmod,
4016         .slave          = &omap44xx_l4_per_hwmod,
4017         .clk            = "l3_div_ck",
4018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4019 };
4020
4021 /* l4_cfg -> l4_wkup */
4022 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4023         .master         = &omap44xx_l4_cfg_hwmod,
4024         .slave          = &omap44xx_l4_wkup_hwmod,
4025         .clk            = "l4_div_ck",
4026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4027 };
4028
4029 /* mpu -> mpu_private */
4030 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4031         .master         = &omap44xx_mpu_hwmod,
4032         .slave          = &omap44xx_mpu_private_hwmod,
4033         .clk            = "l3_div_ck",
4034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4035 };
4036
4037 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4038         {
4039                 .pa_start       = 0x4a102000,
4040                 .pa_end         = 0x4a10207f,
4041                 .flags          = ADDR_TYPE_RT
4042         },
4043         { }
4044 };
4045
4046 /* l4_cfg -> ocp_wp_noc */
4047 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4048         .master         = &omap44xx_l4_cfg_hwmod,
4049         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4050         .clk            = "l4_div_ck",
4051         .addr           = omap44xx_ocp_wp_noc_addrs,
4052         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4053 };
4054
4055 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4056         {
4057                 .pa_start       = 0x401f1000,
4058                 .pa_end         = 0x401f13ff,
4059                 .flags          = ADDR_TYPE_RT
4060         },
4061         { }
4062 };
4063
4064 /* l4_abe -> aess */
4065 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4066         .master         = &omap44xx_l4_abe_hwmod,
4067         .slave          = &omap44xx_aess_hwmod,
4068         .clk            = "ocp_abe_iclk",
4069         .addr           = omap44xx_aess_addrs,
4070         .user           = OCP_USER_MPU,
4071 };
4072
4073 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4074         {
4075                 .pa_start       = 0x490f1000,
4076                 .pa_end         = 0x490f13ff,
4077                 .flags          = ADDR_TYPE_RT
4078         },
4079         { }
4080 };
4081
4082 /* l4_abe -> aess (dma) */
4083 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4084         .master         = &omap44xx_l4_abe_hwmod,
4085         .slave          = &omap44xx_aess_hwmod,
4086         .clk            = "ocp_abe_iclk",
4087         .addr           = omap44xx_aess_dma_addrs,
4088         .user           = OCP_USER_SDMA,
4089 };
4090
4091 /* l3_main_2 -> c2c */
4092 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4093         .master         = &omap44xx_l3_main_2_hwmod,
4094         .slave          = &omap44xx_c2c_hwmod,
4095         .clk            = "l3_div_ck",
4096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4097 };
4098
4099 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4100         {
4101                 .pa_start       = 0x4a304000,
4102                 .pa_end         = 0x4a30401f,
4103                 .flags          = ADDR_TYPE_RT
4104         },
4105         { }
4106 };
4107
4108 /* l4_wkup -> counter_32k */
4109 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4110         .master         = &omap44xx_l4_wkup_hwmod,
4111         .slave          = &omap44xx_counter_32k_hwmod,
4112         .clk            = "l4_wkup_clk_mux_ck",
4113         .addr           = omap44xx_counter_32k_addrs,
4114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4115 };
4116
4117 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4118         {
4119                 .pa_start       = 0x4a002000,
4120                 .pa_end         = 0x4a0027ff,
4121                 .flags          = ADDR_TYPE_RT
4122         },
4123         { }
4124 };
4125
4126 /* l4_cfg -> ctrl_module_core */
4127 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4128         .master         = &omap44xx_l4_cfg_hwmod,
4129         .slave          = &omap44xx_ctrl_module_core_hwmod,
4130         .clk            = "l4_div_ck",
4131         .addr           = omap44xx_ctrl_module_core_addrs,
4132         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4133 };
4134
4135 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4136         {
4137                 .pa_start       = 0x4a100000,
4138                 .pa_end         = 0x4a1007ff,
4139                 .flags          = ADDR_TYPE_RT
4140         },
4141         { }
4142 };
4143
4144 /* l4_cfg -> ctrl_module_pad_core */
4145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4146         .master         = &omap44xx_l4_cfg_hwmod,
4147         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4148         .clk            = "l4_div_ck",
4149         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4150         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4151 };
4152
4153 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4154         {
4155                 .pa_start       = 0x4a30c000,
4156                 .pa_end         = 0x4a30c7ff,
4157                 .flags          = ADDR_TYPE_RT
4158         },
4159         { }
4160 };
4161
4162 /* l4_wkup -> ctrl_module_wkup */
4163 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4164         .master         = &omap44xx_l4_wkup_hwmod,
4165         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4166         .clk            = "l4_wkup_clk_mux_ck",
4167         .addr           = omap44xx_ctrl_module_wkup_addrs,
4168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4169 };
4170
4171 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4172         {
4173                 .pa_start       = 0x4a31e000,
4174                 .pa_end         = 0x4a31e7ff,
4175                 .flags          = ADDR_TYPE_RT
4176         },
4177         { }
4178 };
4179
4180 /* l4_wkup -> ctrl_module_pad_wkup */
4181 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4182         .master         = &omap44xx_l4_wkup_hwmod,
4183         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4184         .clk            = "l4_wkup_clk_mux_ck",
4185         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4187 };
4188
4189 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4190         {
4191                 .pa_start       = 0x54160000,
4192                 .pa_end         = 0x54167fff,
4193                 .flags          = ADDR_TYPE_RT
4194         },
4195         { }
4196 };
4197
4198 /* l3_instr -> debugss */
4199 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4200         .master         = &omap44xx_l3_instr_hwmod,
4201         .slave          = &omap44xx_debugss_hwmod,
4202         .clk            = "l3_div_ck",
4203         .addr           = omap44xx_debugss_addrs,
4204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4205 };
4206
4207 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4208         {
4209                 .pa_start       = 0x4a056000,
4210                 .pa_end         = 0x4a056fff,
4211                 .flags          = ADDR_TYPE_RT
4212         },
4213         { }
4214 };
4215
4216 /* l4_cfg -> dma_system */
4217 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4218         .master         = &omap44xx_l4_cfg_hwmod,
4219         .slave          = &omap44xx_dma_system_hwmod,
4220         .clk            = "l4_div_ck",
4221         .addr           = omap44xx_dma_system_addrs,
4222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4223 };
4224
4225 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4226         {
4227                 .name           = "mpu",
4228                 .pa_start       = 0x4012e000,
4229                 .pa_end         = 0x4012e07f,
4230                 .flags          = ADDR_TYPE_RT
4231         },
4232         { }
4233 };
4234
4235 /* l4_abe -> dmic */
4236 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4237         .master         = &omap44xx_l4_abe_hwmod,
4238         .slave          = &omap44xx_dmic_hwmod,
4239         .clk            = "ocp_abe_iclk",
4240         .addr           = omap44xx_dmic_addrs,
4241         .user           = OCP_USER_MPU,
4242 };
4243
4244 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4245         {
4246                 .name           = "dma",
4247                 .pa_start       = 0x4902e000,
4248                 .pa_end         = 0x4902e07f,
4249                 .flags          = ADDR_TYPE_RT
4250         },
4251         { }
4252 };
4253
4254 /* l4_abe -> dmic (dma) */
4255 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4256         .master         = &omap44xx_l4_abe_hwmod,
4257         .slave          = &omap44xx_dmic_hwmod,
4258         .clk            = "ocp_abe_iclk",
4259         .addr           = omap44xx_dmic_dma_addrs,
4260         .user           = OCP_USER_SDMA,
4261 };
4262
4263 /* dsp -> iva */
4264 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4265         .master         = &omap44xx_dsp_hwmod,
4266         .slave          = &omap44xx_iva_hwmod,
4267         .clk            = "dpll_iva_m5x2_ck",
4268         .user           = OCP_USER_DSP,
4269 };
4270
4271 /* dsp -> sl2if */
4272 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4273         .master         = &omap44xx_dsp_hwmod,
4274         .slave          = &omap44xx_sl2if_hwmod,
4275         .clk            = "dpll_iva_m5x2_ck",
4276         .user           = OCP_USER_DSP,
4277 };
4278
4279 /* l4_cfg -> dsp */
4280 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4281         .master         = &omap44xx_l4_cfg_hwmod,
4282         .slave          = &omap44xx_dsp_hwmod,
4283         .clk            = "l4_div_ck",
4284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4285 };
4286
4287 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4288         {
4289                 .pa_start       = 0x58000000,
4290                 .pa_end         = 0x5800007f,
4291                 .flags          = ADDR_TYPE_RT
4292         },
4293         { }
4294 };
4295
4296 /* l3_main_2 -> dss */
4297 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4298         .master         = &omap44xx_l3_main_2_hwmod,
4299         .slave          = &omap44xx_dss_hwmod,
4300         .clk            = "dss_fck",
4301         .addr           = omap44xx_dss_dma_addrs,
4302         .user           = OCP_USER_SDMA,
4303 };
4304
4305 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4306         {
4307                 .pa_start       = 0x48040000,
4308                 .pa_end         = 0x4804007f,
4309                 .flags          = ADDR_TYPE_RT
4310         },
4311         { }
4312 };
4313
4314 /* l4_per -> dss */
4315 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4316         .master         = &omap44xx_l4_per_hwmod,
4317         .slave          = &omap44xx_dss_hwmod,
4318         .clk            = "l4_div_ck",
4319         .addr           = omap44xx_dss_addrs,
4320         .user           = OCP_USER_MPU,
4321 };
4322
4323 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4324         {
4325                 .pa_start       = 0x58001000,
4326                 .pa_end         = 0x58001fff,
4327                 .flags          = ADDR_TYPE_RT
4328         },
4329         { }
4330 };
4331
4332 /* l3_main_2 -> dss_dispc */
4333 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4334         .master         = &omap44xx_l3_main_2_hwmod,
4335         .slave          = &omap44xx_dss_dispc_hwmod,
4336         .clk            = "dss_fck",
4337         .addr           = omap44xx_dss_dispc_dma_addrs,
4338         .user           = OCP_USER_SDMA,
4339 };
4340
4341 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4342         {
4343                 .pa_start       = 0x48041000,
4344                 .pa_end         = 0x48041fff,
4345                 .flags          = ADDR_TYPE_RT
4346         },
4347         { }
4348 };
4349
4350 /* l4_per -> dss_dispc */
4351 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4352         .master         = &omap44xx_l4_per_hwmod,
4353         .slave          = &omap44xx_dss_dispc_hwmod,
4354         .clk            = "l4_div_ck",
4355         .addr           = omap44xx_dss_dispc_addrs,
4356         .user           = OCP_USER_MPU,
4357 };
4358
4359 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4360         {
4361                 .pa_start       = 0x58004000,
4362                 .pa_end         = 0x580041ff,
4363                 .flags          = ADDR_TYPE_RT
4364         },
4365         { }
4366 };
4367
4368 /* l3_main_2 -> dss_dsi1 */
4369 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4370         .master         = &omap44xx_l3_main_2_hwmod,
4371         .slave          = &omap44xx_dss_dsi1_hwmod,
4372         .clk            = "dss_fck",
4373         .addr           = omap44xx_dss_dsi1_dma_addrs,
4374         .user           = OCP_USER_SDMA,
4375 };
4376
4377 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4378         {
4379                 .pa_start       = 0x48044000,
4380                 .pa_end         = 0x480441ff,
4381                 .flags          = ADDR_TYPE_RT
4382         },
4383         { }
4384 };
4385
4386 /* l4_per -> dss_dsi1 */
4387 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4388         .master         = &omap44xx_l4_per_hwmod,
4389         .slave          = &omap44xx_dss_dsi1_hwmod,
4390         .clk            = "l4_div_ck",
4391         .addr           = omap44xx_dss_dsi1_addrs,
4392         .user           = OCP_USER_MPU,
4393 };
4394
4395 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4396         {
4397                 .pa_start       = 0x58005000,
4398                 .pa_end         = 0x580051ff,
4399                 .flags          = ADDR_TYPE_RT
4400         },
4401         { }
4402 };
4403
4404 /* l3_main_2 -> dss_dsi2 */
4405 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4406         .master         = &omap44xx_l3_main_2_hwmod,
4407         .slave          = &omap44xx_dss_dsi2_hwmod,
4408         .clk            = "dss_fck",
4409         .addr           = omap44xx_dss_dsi2_dma_addrs,
4410         .user           = OCP_USER_SDMA,
4411 };
4412
4413 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4414         {
4415                 .pa_start       = 0x48045000,
4416                 .pa_end         = 0x480451ff,
4417                 .flags          = ADDR_TYPE_RT
4418         },
4419         { }
4420 };
4421
4422 /* l4_per -> dss_dsi2 */
4423 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4424         .master         = &omap44xx_l4_per_hwmod,
4425         .slave          = &omap44xx_dss_dsi2_hwmod,
4426         .clk            = "l4_div_ck",
4427         .addr           = omap44xx_dss_dsi2_addrs,
4428         .user           = OCP_USER_MPU,
4429 };
4430
4431 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4432         {
4433                 .pa_start       = 0x58006000,
4434                 .pa_end         = 0x58006fff,
4435                 .flags          = ADDR_TYPE_RT
4436         },
4437         { }
4438 };
4439
4440 /* l3_main_2 -> dss_hdmi */
4441 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4442         .master         = &omap44xx_l3_main_2_hwmod,
4443         .slave          = &omap44xx_dss_hdmi_hwmod,
4444         .clk            = "dss_fck",
4445         .addr           = omap44xx_dss_hdmi_dma_addrs,
4446         .user           = OCP_USER_SDMA,
4447 };
4448
4449 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4450         {
4451                 .pa_start       = 0x48046000,
4452                 .pa_end         = 0x48046fff,
4453                 .flags          = ADDR_TYPE_RT
4454         },
4455         { }
4456 };
4457
4458 /* l4_per -> dss_hdmi */
4459 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4460         .master         = &omap44xx_l4_per_hwmod,
4461         .slave          = &omap44xx_dss_hdmi_hwmod,
4462         .clk            = "l4_div_ck",
4463         .addr           = omap44xx_dss_hdmi_addrs,
4464         .user           = OCP_USER_MPU,
4465 };
4466
4467 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4468         {
4469                 .pa_start       = 0x58002000,
4470                 .pa_end         = 0x580020ff,
4471                 .flags          = ADDR_TYPE_RT
4472         },
4473         { }
4474 };
4475
4476 /* l3_main_2 -> dss_rfbi */
4477 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4478         .master         = &omap44xx_l3_main_2_hwmod,
4479         .slave          = &omap44xx_dss_rfbi_hwmod,
4480         .clk            = "dss_fck",
4481         .addr           = omap44xx_dss_rfbi_dma_addrs,
4482         .user           = OCP_USER_SDMA,
4483 };
4484
4485 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4486         {
4487                 .pa_start       = 0x48042000,
4488                 .pa_end         = 0x480420ff,
4489                 .flags          = ADDR_TYPE_RT
4490         },
4491         { }
4492 };
4493
4494 /* l4_per -> dss_rfbi */
4495 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4496         .master         = &omap44xx_l4_per_hwmod,
4497         .slave          = &omap44xx_dss_rfbi_hwmod,
4498         .clk            = "l4_div_ck",
4499         .addr           = omap44xx_dss_rfbi_addrs,
4500         .user           = OCP_USER_MPU,
4501 };
4502
4503 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4504         {
4505                 .pa_start       = 0x58003000,
4506                 .pa_end         = 0x580030ff,
4507                 .flags          = ADDR_TYPE_RT
4508         },
4509         { }
4510 };
4511
4512 /* l3_main_2 -> dss_venc */
4513 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4514         .master         = &omap44xx_l3_main_2_hwmod,
4515         .slave          = &omap44xx_dss_venc_hwmod,
4516         .clk            = "dss_fck",
4517         .addr           = omap44xx_dss_venc_dma_addrs,
4518         .user           = OCP_USER_SDMA,
4519 };
4520
4521 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4522         {
4523                 .pa_start       = 0x48043000,
4524                 .pa_end         = 0x480430ff,
4525                 .flags          = ADDR_TYPE_RT
4526         },
4527         { }
4528 };
4529
4530 /* l4_per -> dss_venc */
4531 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4532         .master         = &omap44xx_l4_per_hwmod,
4533         .slave          = &omap44xx_dss_venc_hwmod,
4534         .clk            = "l4_div_ck",
4535         .addr           = omap44xx_dss_venc_addrs,
4536         .user           = OCP_USER_MPU,
4537 };
4538
4539 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4540         {
4541                 .pa_start       = 0x48078000,
4542                 .pa_end         = 0x48078fff,
4543                 .flags          = ADDR_TYPE_RT
4544         },
4545         { }
4546 };
4547
4548 /* l4_per -> elm */
4549 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4550         .master         = &omap44xx_l4_per_hwmod,
4551         .slave          = &omap44xx_elm_hwmod,
4552         .clk            = "l4_div_ck",
4553         .addr           = omap44xx_elm_addrs,
4554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4555 };
4556
4557 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4558         {
4559                 .pa_start       = 0x4c000000,
4560                 .pa_end         = 0x4c0000ff,
4561                 .flags          = ADDR_TYPE_RT
4562         },
4563         { }
4564 };
4565
4566 /* emif_fw -> emif1 */
4567 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4568         .master         = &omap44xx_emif_fw_hwmod,
4569         .slave          = &omap44xx_emif1_hwmod,
4570         .clk            = "l3_div_ck",
4571         .addr           = omap44xx_emif1_addrs,
4572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4573 };
4574
4575 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4576         {
4577                 .pa_start       = 0x4d000000,
4578                 .pa_end         = 0x4d0000ff,
4579                 .flags          = ADDR_TYPE_RT
4580         },
4581         { }
4582 };
4583
4584 /* emif_fw -> emif2 */
4585 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4586         .master         = &omap44xx_emif_fw_hwmod,
4587         .slave          = &omap44xx_emif2_hwmod,
4588         .clk            = "l3_div_ck",
4589         .addr           = omap44xx_emif2_addrs,
4590         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4591 };
4592
4593 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4594         {
4595                 .pa_start       = 0x4a10a000,
4596                 .pa_end         = 0x4a10a1ff,
4597                 .flags          = ADDR_TYPE_RT
4598         },
4599         { }
4600 };
4601
4602 /* l4_cfg -> fdif */
4603 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4604         .master         = &omap44xx_l4_cfg_hwmod,
4605         .slave          = &omap44xx_fdif_hwmod,
4606         .clk            = "l4_div_ck",
4607         .addr           = omap44xx_fdif_addrs,
4608         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4609 };
4610
4611 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4612         {
4613                 .pa_start       = 0x4a310000,
4614                 .pa_end         = 0x4a3101ff,
4615                 .flags          = ADDR_TYPE_RT
4616         },
4617         { }
4618 };
4619
4620 /* l4_wkup -> gpio1 */
4621 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4622         .master         = &omap44xx_l4_wkup_hwmod,
4623         .slave          = &omap44xx_gpio1_hwmod,
4624         .clk            = "l4_wkup_clk_mux_ck",
4625         .addr           = omap44xx_gpio1_addrs,
4626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4627 };
4628
4629 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4630         {
4631                 .pa_start       = 0x48055000,
4632                 .pa_end         = 0x480551ff,
4633                 .flags          = ADDR_TYPE_RT
4634         },
4635         { }
4636 };
4637
4638 /* l4_per -> gpio2 */
4639 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4640         .master         = &omap44xx_l4_per_hwmod,
4641         .slave          = &omap44xx_gpio2_hwmod,
4642         .clk            = "l4_div_ck",
4643         .addr           = omap44xx_gpio2_addrs,
4644         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4645 };
4646
4647 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4648         {
4649                 .pa_start       = 0x48057000,
4650                 .pa_end         = 0x480571ff,
4651                 .flags          = ADDR_TYPE_RT
4652         },
4653         { }
4654 };
4655
4656 /* l4_per -> gpio3 */
4657 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4658         .master         = &omap44xx_l4_per_hwmod,
4659         .slave          = &omap44xx_gpio3_hwmod,
4660         .clk            = "l4_div_ck",
4661         .addr           = omap44xx_gpio3_addrs,
4662         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4663 };
4664
4665 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4666         {
4667                 .pa_start       = 0x48059000,
4668                 .pa_end         = 0x480591ff,
4669                 .flags          = ADDR_TYPE_RT
4670         },
4671         { }
4672 };
4673
4674 /* l4_per -> gpio4 */
4675 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4676         .master         = &omap44xx_l4_per_hwmod,
4677         .slave          = &omap44xx_gpio4_hwmod,
4678         .clk            = "l4_div_ck",
4679         .addr           = omap44xx_gpio4_addrs,
4680         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4681 };
4682
4683 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4684         {
4685                 .pa_start       = 0x4805b000,
4686                 .pa_end         = 0x4805b1ff,
4687                 .flags          = ADDR_TYPE_RT
4688         },
4689         { }
4690 };
4691
4692 /* l4_per -> gpio5 */
4693 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4694         .master         = &omap44xx_l4_per_hwmod,
4695         .slave          = &omap44xx_gpio5_hwmod,
4696         .clk            = "l4_div_ck",
4697         .addr           = omap44xx_gpio5_addrs,
4698         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4699 };
4700
4701 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4702         {
4703                 .pa_start       = 0x4805d000,
4704                 .pa_end         = 0x4805d1ff,
4705                 .flags          = ADDR_TYPE_RT
4706         },
4707         { }
4708 };
4709
4710 /* l4_per -> gpio6 */
4711 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4712         .master         = &omap44xx_l4_per_hwmod,
4713         .slave          = &omap44xx_gpio6_hwmod,
4714         .clk            = "l4_div_ck",
4715         .addr           = omap44xx_gpio6_addrs,
4716         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4717 };
4718
4719 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4720         {
4721                 .pa_start       = 0x50000000,
4722                 .pa_end         = 0x500003ff,
4723                 .flags          = ADDR_TYPE_RT
4724         },
4725         { }
4726 };
4727
4728 /* l3_main_2 -> gpmc */
4729 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4730         .master         = &omap44xx_l3_main_2_hwmod,
4731         .slave          = &omap44xx_gpmc_hwmod,
4732         .clk            = "l3_div_ck",
4733         .addr           = omap44xx_gpmc_addrs,
4734         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4735 };
4736
4737 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4738         {
4739                 .pa_start       = 0x56000000,
4740                 .pa_end         = 0x5600ffff,
4741                 .flags          = ADDR_TYPE_RT
4742         },
4743         { }
4744 };
4745
4746 /* l3_main_2 -> gpu */
4747 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4748         .master         = &omap44xx_l3_main_2_hwmod,
4749         .slave          = &omap44xx_gpu_hwmod,
4750         .clk            = "l3_div_ck",
4751         .addr           = omap44xx_gpu_addrs,
4752         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4753 };
4754
4755 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4756         {
4757                 .pa_start       = 0x480b2000,
4758                 .pa_end         = 0x480b201f,
4759                 .flags          = ADDR_TYPE_RT
4760         },
4761         { }
4762 };
4763
4764 /* l4_per -> hdq1w */
4765 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4766         .master         = &omap44xx_l4_per_hwmod,
4767         .slave          = &omap44xx_hdq1w_hwmod,
4768         .clk            = "l4_div_ck",
4769         .addr           = omap44xx_hdq1w_addrs,
4770         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4771 };
4772
4773 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4774         {
4775                 .pa_start       = 0x4a058000,
4776                 .pa_end         = 0x4a05bfff,
4777                 .flags          = ADDR_TYPE_RT
4778         },
4779         { }
4780 };
4781
4782 /* l4_cfg -> hsi */
4783 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4784         .master         = &omap44xx_l4_cfg_hwmod,
4785         .slave          = &omap44xx_hsi_hwmod,
4786         .clk            = "l4_div_ck",
4787         .addr           = omap44xx_hsi_addrs,
4788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4789 };
4790
4791 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4792         {
4793                 .pa_start       = 0x48070000,
4794                 .pa_end         = 0x480700ff,
4795                 .flags          = ADDR_TYPE_RT
4796         },
4797         { }
4798 };
4799
4800 /* l4_per -> i2c1 */
4801 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4802         .master         = &omap44xx_l4_per_hwmod,
4803         .slave          = &omap44xx_i2c1_hwmod,
4804         .clk            = "l4_div_ck",
4805         .addr           = omap44xx_i2c1_addrs,
4806         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4807 };
4808
4809 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4810         {
4811                 .pa_start       = 0x48072000,
4812                 .pa_end         = 0x480720ff,
4813                 .flags          = ADDR_TYPE_RT
4814         },
4815         { }
4816 };
4817
4818 /* l4_per -> i2c2 */
4819 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4820         .master         = &omap44xx_l4_per_hwmod,
4821         .slave          = &omap44xx_i2c2_hwmod,
4822         .clk            = "l4_div_ck",
4823         .addr           = omap44xx_i2c2_addrs,
4824         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4825 };
4826
4827 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4828         {
4829                 .pa_start       = 0x48060000,
4830                 .pa_end         = 0x480600ff,
4831                 .flags          = ADDR_TYPE_RT
4832         },
4833         { }
4834 };
4835
4836 /* l4_per -> i2c3 */
4837 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4838         .master         = &omap44xx_l4_per_hwmod,
4839         .slave          = &omap44xx_i2c3_hwmod,
4840         .clk            = "l4_div_ck",
4841         .addr           = omap44xx_i2c3_addrs,
4842         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4843 };
4844
4845 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4846         {
4847                 .pa_start       = 0x48350000,
4848                 .pa_end         = 0x483500ff,
4849                 .flags          = ADDR_TYPE_RT
4850         },
4851         { }
4852 };
4853
4854 /* l4_per -> i2c4 */
4855 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4856         .master         = &omap44xx_l4_per_hwmod,
4857         .slave          = &omap44xx_i2c4_hwmod,
4858         .clk            = "l4_div_ck",
4859         .addr           = omap44xx_i2c4_addrs,
4860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4861 };
4862
4863 /* l3_main_2 -> ipu */
4864 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4865         .master         = &omap44xx_l3_main_2_hwmod,
4866         .slave          = &omap44xx_ipu_hwmod,
4867         .clk            = "l3_div_ck",
4868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4869 };
4870
4871 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4872         {
4873                 .pa_start       = 0x52000000,
4874                 .pa_end         = 0x520000ff,
4875                 .flags          = ADDR_TYPE_RT
4876         },
4877         { }
4878 };
4879
4880 /* l3_main_2 -> iss */
4881 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4882         .master         = &omap44xx_l3_main_2_hwmod,
4883         .slave          = &omap44xx_iss_hwmod,
4884         .clk            = "l3_div_ck",
4885         .addr           = omap44xx_iss_addrs,
4886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4887 };
4888
4889 /* iva -> sl2if */
4890 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4891         .master         = &omap44xx_iva_hwmod,
4892         .slave          = &omap44xx_sl2if_hwmod,
4893         .clk            = "dpll_iva_m5x2_ck",
4894         .user           = OCP_USER_IVA,
4895 };
4896
4897 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4898         {
4899                 .pa_start       = 0x5a000000,
4900                 .pa_end         = 0x5a07ffff,
4901                 .flags          = ADDR_TYPE_RT
4902         },
4903         { }
4904 };
4905
4906 /* l3_main_2 -> iva */
4907 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4908         .master         = &omap44xx_l3_main_2_hwmod,
4909         .slave          = &omap44xx_iva_hwmod,
4910         .clk            = "l3_div_ck",
4911         .addr           = omap44xx_iva_addrs,
4912         .user           = OCP_USER_MPU,
4913 };
4914
4915 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4916         {
4917                 .pa_start       = 0x4a31c000,
4918                 .pa_end         = 0x4a31c07f,
4919                 .flags          = ADDR_TYPE_RT
4920         },
4921         { }
4922 };
4923
4924 /* l4_wkup -> kbd */
4925 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4926         .master         = &omap44xx_l4_wkup_hwmod,
4927         .slave          = &omap44xx_kbd_hwmod,
4928         .clk            = "l4_wkup_clk_mux_ck",
4929         .addr           = omap44xx_kbd_addrs,
4930         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4931 };
4932
4933 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4934         {
4935                 .pa_start       = 0x4a0f4000,
4936                 .pa_end         = 0x4a0f41ff,
4937                 .flags          = ADDR_TYPE_RT
4938         },
4939         { }
4940 };
4941
4942 /* l4_cfg -> mailbox */
4943 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4944         .master         = &omap44xx_l4_cfg_hwmod,
4945         .slave          = &omap44xx_mailbox_hwmod,
4946         .clk            = "l4_div_ck",
4947         .addr           = omap44xx_mailbox_addrs,
4948         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4949 };
4950
4951 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4952         {
4953                 .pa_start       = 0x40128000,
4954                 .pa_end         = 0x401283ff,
4955                 .flags          = ADDR_TYPE_RT
4956         },
4957         { }
4958 };
4959
4960 /* l4_abe -> mcasp */
4961 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4962         .master         = &omap44xx_l4_abe_hwmod,
4963         .slave          = &omap44xx_mcasp_hwmod,
4964         .clk            = "ocp_abe_iclk",
4965         .addr           = omap44xx_mcasp_addrs,
4966         .user           = OCP_USER_MPU,
4967 };
4968
4969 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4970         {
4971                 .pa_start       = 0x49028000,
4972                 .pa_end         = 0x490283ff,
4973                 .flags          = ADDR_TYPE_RT
4974         },
4975         { }
4976 };
4977
4978 /* l4_abe -> mcasp (dma) */
4979 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4980         .master         = &omap44xx_l4_abe_hwmod,
4981         .slave          = &omap44xx_mcasp_hwmod,
4982         .clk            = "ocp_abe_iclk",
4983         .addr           = omap44xx_mcasp_dma_addrs,
4984         .user           = OCP_USER_SDMA,
4985 };
4986
4987 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4988         {
4989                 .name           = "mpu",
4990                 .pa_start       = 0x40122000,
4991                 .pa_end         = 0x401220ff,
4992                 .flags          = ADDR_TYPE_RT
4993         },
4994         { }
4995 };
4996
4997 /* l4_abe -> mcbsp1 */
4998 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4999         .master         = &omap44xx_l4_abe_hwmod,
5000         .slave          = &omap44xx_mcbsp1_hwmod,
5001         .clk            = "ocp_abe_iclk",
5002         .addr           = omap44xx_mcbsp1_addrs,
5003         .user           = OCP_USER_MPU,
5004 };
5005
5006 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5007         {
5008                 .name           = "dma",
5009                 .pa_start       = 0x49022000,
5010                 .pa_end         = 0x490220ff,
5011                 .flags          = ADDR_TYPE_RT
5012         },
5013         { }
5014 };
5015
5016 /* l4_abe -> mcbsp1 (dma) */
5017 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5018         .master         = &omap44xx_l4_abe_hwmod,
5019         .slave          = &omap44xx_mcbsp1_hwmod,
5020         .clk            = "ocp_abe_iclk",
5021         .addr           = omap44xx_mcbsp1_dma_addrs,
5022         .user           = OCP_USER_SDMA,
5023 };
5024
5025 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5026         {
5027                 .name           = "mpu",
5028                 .pa_start       = 0x40124000,
5029                 .pa_end         = 0x401240ff,
5030                 .flags          = ADDR_TYPE_RT
5031         },
5032         { }
5033 };
5034
5035 /* l4_abe -> mcbsp2 */
5036 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5037         .master         = &omap44xx_l4_abe_hwmod,
5038         .slave          = &omap44xx_mcbsp2_hwmod,
5039         .clk            = "ocp_abe_iclk",
5040         .addr           = omap44xx_mcbsp2_addrs,
5041         .user           = OCP_USER_MPU,
5042 };
5043
5044 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5045         {
5046                 .name           = "dma",
5047                 .pa_start       = 0x49024000,
5048                 .pa_end         = 0x490240ff,
5049                 .flags          = ADDR_TYPE_RT
5050         },
5051         { }
5052 };
5053
5054 /* l4_abe -> mcbsp2 (dma) */
5055 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5056         .master         = &omap44xx_l4_abe_hwmod,
5057         .slave          = &omap44xx_mcbsp2_hwmod,
5058         .clk            = "ocp_abe_iclk",
5059         .addr           = omap44xx_mcbsp2_dma_addrs,
5060         .user           = OCP_USER_SDMA,
5061 };
5062
5063 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5064         {
5065                 .name           = "mpu",
5066                 .pa_start       = 0x40126000,
5067                 .pa_end         = 0x401260ff,
5068                 .flags          = ADDR_TYPE_RT
5069         },
5070         { }
5071 };
5072
5073 /* l4_abe -> mcbsp3 */
5074 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5075         .master         = &omap44xx_l4_abe_hwmod,
5076         .slave          = &omap44xx_mcbsp3_hwmod,
5077         .clk            = "ocp_abe_iclk",
5078         .addr           = omap44xx_mcbsp3_addrs,
5079         .user           = OCP_USER_MPU,
5080 };
5081
5082 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5083         {
5084                 .name           = "dma",
5085                 .pa_start       = 0x49026000,
5086                 .pa_end         = 0x490260ff,
5087                 .flags          = ADDR_TYPE_RT
5088         },
5089         { }
5090 };
5091
5092 /* l4_abe -> mcbsp3 (dma) */
5093 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5094         .master         = &omap44xx_l4_abe_hwmod,
5095         .slave          = &omap44xx_mcbsp3_hwmod,
5096         .clk            = "ocp_abe_iclk",
5097         .addr           = omap44xx_mcbsp3_dma_addrs,
5098         .user           = OCP_USER_SDMA,
5099 };
5100
5101 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5102         {
5103                 .pa_start       = 0x48096000,
5104                 .pa_end         = 0x480960ff,
5105                 .flags          = ADDR_TYPE_RT
5106         },
5107         { }
5108 };
5109
5110 /* l4_per -> mcbsp4 */
5111 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5112         .master         = &omap44xx_l4_per_hwmod,
5113         .slave          = &omap44xx_mcbsp4_hwmod,
5114         .clk            = "l4_div_ck",
5115         .addr           = omap44xx_mcbsp4_addrs,
5116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5117 };
5118
5119 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5120         {
5121                 .pa_start       = 0x40132000,
5122                 .pa_end         = 0x4013207f,
5123                 .flags          = ADDR_TYPE_RT
5124         },
5125         { }
5126 };
5127
5128 /* l4_abe -> mcpdm */
5129 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5130         .master         = &omap44xx_l4_abe_hwmod,
5131         .slave          = &omap44xx_mcpdm_hwmod,
5132         .clk            = "ocp_abe_iclk",
5133         .addr           = omap44xx_mcpdm_addrs,
5134         .user           = OCP_USER_MPU,
5135 };
5136
5137 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5138         {
5139                 .pa_start       = 0x49032000,
5140                 .pa_end         = 0x4903207f,
5141                 .flags          = ADDR_TYPE_RT
5142         },
5143         { }
5144 };
5145
5146 /* l4_abe -> mcpdm (dma) */
5147 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5148         .master         = &omap44xx_l4_abe_hwmod,
5149         .slave          = &omap44xx_mcpdm_hwmod,
5150         .clk            = "ocp_abe_iclk",
5151         .addr           = omap44xx_mcpdm_dma_addrs,
5152         .user           = OCP_USER_SDMA,
5153 };
5154
5155 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5156         {
5157                 .pa_start       = 0x48098000,
5158                 .pa_end         = 0x480981ff,
5159                 .flags          = ADDR_TYPE_RT
5160         },
5161         { }
5162 };
5163
5164 /* l4_per -> mcspi1 */
5165 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5166         .master         = &omap44xx_l4_per_hwmod,
5167         .slave          = &omap44xx_mcspi1_hwmod,
5168         .clk            = "l4_div_ck",
5169         .addr           = omap44xx_mcspi1_addrs,
5170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5171 };
5172
5173 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5174         {
5175                 .pa_start       = 0x4809a000,
5176                 .pa_end         = 0x4809a1ff,
5177                 .flags          = ADDR_TYPE_RT
5178         },
5179         { }
5180 };
5181
5182 /* l4_per -> mcspi2 */
5183 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5184         .master         = &omap44xx_l4_per_hwmod,
5185         .slave          = &omap44xx_mcspi2_hwmod,
5186         .clk            = "l4_div_ck",
5187         .addr           = omap44xx_mcspi2_addrs,
5188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5189 };
5190
5191 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5192         {
5193                 .pa_start       = 0x480b8000,
5194                 .pa_end         = 0x480b81ff,
5195                 .flags          = ADDR_TYPE_RT
5196         },
5197         { }
5198 };
5199
5200 /* l4_per -> mcspi3 */
5201 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5202         .master         = &omap44xx_l4_per_hwmod,
5203         .slave          = &omap44xx_mcspi3_hwmod,
5204         .clk            = "l4_div_ck",
5205         .addr           = omap44xx_mcspi3_addrs,
5206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5207 };
5208
5209 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5210         {
5211                 .pa_start       = 0x480ba000,
5212                 .pa_end         = 0x480ba1ff,
5213                 .flags          = ADDR_TYPE_RT
5214         },
5215         { }
5216 };
5217
5218 /* l4_per -> mcspi4 */
5219 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5220         .master         = &omap44xx_l4_per_hwmod,
5221         .slave          = &omap44xx_mcspi4_hwmod,
5222         .clk            = "l4_div_ck",
5223         .addr           = omap44xx_mcspi4_addrs,
5224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5225 };
5226
5227 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5228         {
5229                 .pa_start       = 0x4809c000,
5230                 .pa_end         = 0x4809c3ff,
5231                 .flags          = ADDR_TYPE_RT
5232         },
5233         { }
5234 };
5235
5236 /* l4_per -> mmc1 */
5237 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5238         .master         = &omap44xx_l4_per_hwmod,
5239         .slave          = &omap44xx_mmc1_hwmod,
5240         .clk            = "l4_div_ck",
5241         .addr           = omap44xx_mmc1_addrs,
5242         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5243 };
5244
5245 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5246         {
5247                 .pa_start       = 0x480b4000,
5248                 .pa_end         = 0x480b43ff,
5249                 .flags          = ADDR_TYPE_RT
5250         },
5251         { }
5252 };
5253
5254 /* l4_per -> mmc2 */
5255 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5256         .master         = &omap44xx_l4_per_hwmod,
5257         .slave          = &omap44xx_mmc2_hwmod,
5258         .clk            = "l4_div_ck",
5259         .addr           = omap44xx_mmc2_addrs,
5260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5261 };
5262
5263 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5264         {
5265                 .pa_start       = 0x480ad000,
5266                 .pa_end         = 0x480ad3ff,
5267                 .flags          = ADDR_TYPE_RT
5268         },
5269         { }
5270 };
5271
5272 /* l4_per -> mmc3 */
5273 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5274         .master         = &omap44xx_l4_per_hwmod,
5275         .slave          = &omap44xx_mmc3_hwmod,
5276         .clk            = "l4_div_ck",
5277         .addr           = omap44xx_mmc3_addrs,
5278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5279 };
5280
5281 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5282         {
5283                 .pa_start       = 0x480d1000,
5284                 .pa_end         = 0x480d13ff,
5285                 .flags          = ADDR_TYPE_RT
5286         },
5287         { }
5288 };
5289
5290 /* l4_per -> mmc4 */
5291 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5292         .master         = &omap44xx_l4_per_hwmod,
5293         .slave          = &omap44xx_mmc4_hwmod,
5294         .clk            = "l4_div_ck",
5295         .addr           = omap44xx_mmc4_addrs,
5296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5297 };
5298
5299 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5300         {
5301                 .pa_start       = 0x480d5000,
5302                 .pa_end         = 0x480d53ff,
5303                 .flags          = ADDR_TYPE_RT
5304         },
5305         { }
5306 };
5307
5308 /* l4_per -> mmc5 */
5309 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5310         .master         = &omap44xx_l4_per_hwmod,
5311         .slave          = &omap44xx_mmc5_hwmod,
5312         .clk            = "l4_div_ck",
5313         .addr           = omap44xx_mmc5_addrs,
5314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5315 };
5316
5317 /* l3_main_2 -> ocmc_ram */
5318 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5319         .master         = &omap44xx_l3_main_2_hwmod,
5320         .slave          = &omap44xx_ocmc_ram_hwmod,
5321         .clk            = "l3_div_ck",
5322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5323 };
5324
5325 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5326         {
5327                 .pa_start       = 0x4a0ad000,
5328                 .pa_end         = 0x4a0ad01f,
5329                 .flags          = ADDR_TYPE_RT
5330         },
5331         { }
5332 };
5333
5334 /* l4_cfg -> ocp2scp_usb_phy */
5335 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5336         .master         = &omap44xx_l4_cfg_hwmod,
5337         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5338         .clk            = "l4_div_ck",
5339         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5341 };
5342
5343 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5344         {
5345                 .pa_start       = 0x48243000,
5346                 .pa_end         = 0x48243fff,
5347                 .flags          = ADDR_TYPE_RT
5348         },
5349         { }
5350 };
5351
5352 /* mpu_private -> prcm_mpu */
5353 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5354         .master         = &omap44xx_mpu_private_hwmod,
5355         .slave          = &omap44xx_prcm_mpu_hwmod,
5356         .clk            = "l3_div_ck",
5357         .addr           = omap44xx_prcm_mpu_addrs,
5358         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5359 };
5360
5361 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5362         {
5363                 .pa_start       = 0x4a004000,
5364                 .pa_end         = 0x4a004fff,
5365                 .flags          = ADDR_TYPE_RT
5366         },
5367         { }
5368 };
5369
5370 /* l4_wkup -> cm_core_aon */
5371 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5372         .master         = &omap44xx_l4_wkup_hwmod,
5373         .slave          = &omap44xx_cm_core_aon_hwmod,
5374         .clk            = "l4_wkup_clk_mux_ck",
5375         .addr           = omap44xx_cm_core_aon_addrs,
5376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5377 };
5378
5379 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5380         {
5381                 .pa_start       = 0x4a008000,
5382                 .pa_end         = 0x4a009fff,
5383                 .flags          = ADDR_TYPE_RT
5384         },
5385         { }
5386 };
5387
5388 /* l4_cfg -> cm_core */
5389 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5390         .master         = &omap44xx_l4_cfg_hwmod,
5391         .slave          = &omap44xx_cm_core_hwmod,
5392         .clk            = "l4_div_ck",
5393         .addr           = omap44xx_cm_core_addrs,
5394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5395 };
5396
5397 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5398         {
5399                 .pa_start       = 0x4a306000,
5400                 .pa_end         = 0x4a307fff,
5401                 .flags          = ADDR_TYPE_RT
5402         },
5403         { }
5404 };
5405
5406 /* l4_wkup -> prm */
5407 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5408         .master         = &omap44xx_l4_wkup_hwmod,
5409         .slave          = &omap44xx_prm_hwmod,
5410         .clk            = "l4_wkup_clk_mux_ck",
5411         .addr           = omap44xx_prm_addrs,
5412         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5413 };
5414
5415 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5416         {
5417                 .pa_start       = 0x4a30a000,
5418                 .pa_end         = 0x4a30a7ff,
5419                 .flags          = ADDR_TYPE_RT
5420         },
5421         { }
5422 };
5423
5424 /* l4_wkup -> scrm */
5425 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5426         .master         = &omap44xx_l4_wkup_hwmod,
5427         .slave          = &omap44xx_scrm_hwmod,
5428         .clk            = "l4_wkup_clk_mux_ck",
5429         .addr           = omap44xx_scrm_addrs,
5430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5431 };
5432
5433 /* l3_main_2 -> sl2if */
5434 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5435         .master         = &omap44xx_l3_main_2_hwmod,
5436         .slave          = &omap44xx_sl2if_hwmod,
5437         .clk            = "l3_div_ck",
5438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5439 };
5440
5441 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5442         {
5443                 .pa_start       = 0x4012c000,
5444                 .pa_end         = 0x4012c3ff,
5445                 .flags          = ADDR_TYPE_RT
5446         },
5447         { }
5448 };
5449
5450 /* l4_abe -> slimbus1 */
5451 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5452         .master         = &omap44xx_l4_abe_hwmod,
5453         .slave          = &omap44xx_slimbus1_hwmod,
5454         .clk            = "ocp_abe_iclk",
5455         .addr           = omap44xx_slimbus1_addrs,
5456         .user           = OCP_USER_MPU,
5457 };
5458
5459 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5460         {
5461                 .pa_start       = 0x4902c000,
5462                 .pa_end         = 0x4902c3ff,
5463                 .flags          = ADDR_TYPE_RT
5464         },
5465         { }
5466 };
5467
5468 /* l4_abe -> slimbus1 (dma) */
5469 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5470         .master         = &omap44xx_l4_abe_hwmod,
5471         .slave          = &omap44xx_slimbus1_hwmod,
5472         .clk            = "ocp_abe_iclk",
5473         .addr           = omap44xx_slimbus1_dma_addrs,
5474         .user           = OCP_USER_SDMA,
5475 };
5476
5477 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5478         {
5479                 .pa_start       = 0x48076000,
5480                 .pa_end         = 0x480763ff,
5481                 .flags          = ADDR_TYPE_RT
5482         },
5483         { }
5484 };
5485
5486 /* l4_per -> slimbus2 */
5487 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5488         .master         = &omap44xx_l4_per_hwmod,
5489         .slave          = &omap44xx_slimbus2_hwmod,
5490         .clk            = "l4_div_ck",
5491         .addr           = omap44xx_slimbus2_addrs,
5492         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5493 };
5494
5495 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5496         {
5497                 .pa_start       = 0x4a0dd000,
5498                 .pa_end         = 0x4a0dd03f,
5499                 .flags          = ADDR_TYPE_RT
5500         },
5501         { }
5502 };
5503
5504 /* l4_cfg -> smartreflex_core */
5505 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5506         .master         = &omap44xx_l4_cfg_hwmod,
5507         .slave          = &omap44xx_smartreflex_core_hwmod,
5508         .clk            = "l4_div_ck",
5509         .addr           = omap44xx_smartreflex_core_addrs,
5510         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5511 };
5512
5513 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5514         {
5515                 .pa_start       = 0x4a0db000,
5516                 .pa_end         = 0x4a0db03f,
5517                 .flags          = ADDR_TYPE_RT
5518         },
5519         { }
5520 };
5521
5522 /* l4_cfg -> smartreflex_iva */
5523 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5524         .master         = &omap44xx_l4_cfg_hwmod,
5525         .slave          = &omap44xx_smartreflex_iva_hwmod,
5526         .clk            = "l4_div_ck",
5527         .addr           = omap44xx_smartreflex_iva_addrs,
5528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5529 };
5530
5531 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5532         {
5533                 .pa_start       = 0x4a0d9000,
5534                 .pa_end         = 0x4a0d903f,
5535                 .flags          = ADDR_TYPE_RT
5536         },
5537         { }
5538 };
5539
5540 /* l4_cfg -> smartreflex_mpu */
5541 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5542         .master         = &omap44xx_l4_cfg_hwmod,
5543         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5544         .clk            = "l4_div_ck",
5545         .addr           = omap44xx_smartreflex_mpu_addrs,
5546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5547 };
5548
5549 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5550         {
5551                 .pa_start       = 0x4a0f6000,
5552                 .pa_end         = 0x4a0f6fff,
5553                 .flags          = ADDR_TYPE_RT
5554         },
5555         { }
5556 };
5557
5558 /* l4_cfg -> spinlock */
5559 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5560         .master         = &omap44xx_l4_cfg_hwmod,
5561         .slave          = &omap44xx_spinlock_hwmod,
5562         .clk            = "l4_div_ck",
5563         .addr           = omap44xx_spinlock_addrs,
5564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5565 };
5566
5567 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5568         {
5569                 .pa_start       = 0x4a318000,
5570                 .pa_end         = 0x4a31807f,
5571                 .flags          = ADDR_TYPE_RT
5572         },
5573         { }
5574 };
5575
5576 /* l4_wkup -> timer1 */
5577 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5578         .master         = &omap44xx_l4_wkup_hwmod,
5579         .slave          = &omap44xx_timer1_hwmod,
5580         .clk            = "l4_wkup_clk_mux_ck",
5581         .addr           = omap44xx_timer1_addrs,
5582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5583 };
5584
5585 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5586         {
5587                 .pa_start       = 0x48032000,
5588                 .pa_end         = 0x4803207f,
5589                 .flags          = ADDR_TYPE_RT
5590         },
5591         { }
5592 };
5593
5594 /* l4_per -> timer2 */
5595 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5596         .master         = &omap44xx_l4_per_hwmod,
5597         .slave          = &omap44xx_timer2_hwmod,
5598         .clk            = "l4_div_ck",
5599         .addr           = omap44xx_timer2_addrs,
5600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5601 };
5602
5603 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5604         {
5605                 .pa_start       = 0x48034000,
5606                 .pa_end         = 0x4803407f,
5607                 .flags          = ADDR_TYPE_RT
5608         },
5609         { }
5610 };
5611
5612 /* l4_per -> timer3 */
5613 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5614         .master         = &omap44xx_l4_per_hwmod,
5615         .slave          = &omap44xx_timer3_hwmod,
5616         .clk            = "l4_div_ck",
5617         .addr           = omap44xx_timer3_addrs,
5618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5619 };
5620
5621 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5622         {
5623                 .pa_start       = 0x48036000,
5624                 .pa_end         = 0x4803607f,
5625                 .flags          = ADDR_TYPE_RT
5626         },
5627         { }
5628 };
5629
5630 /* l4_per -> timer4 */
5631 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5632         .master         = &omap44xx_l4_per_hwmod,
5633         .slave          = &omap44xx_timer4_hwmod,
5634         .clk            = "l4_div_ck",
5635         .addr           = omap44xx_timer4_addrs,
5636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5637 };
5638
5639 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5640         {
5641                 .pa_start       = 0x40138000,
5642                 .pa_end         = 0x4013807f,
5643                 .flags          = ADDR_TYPE_RT
5644         },
5645         { }
5646 };
5647
5648 /* l4_abe -> timer5 */
5649 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5650         .master         = &omap44xx_l4_abe_hwmod,
5651         .slave          = &omap44xx_timer5_hwmod,
5652         .clk            = "ocp_abe_iclk",
5653         .addr           = omap44xx_timer5_addrs,
5654         .user           = OCP_USER_MPU,
5655 };
5656
5657 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5658         {
5659                 .pa_start       = 0x49038000,
5660                 .pa_end         = 0x4903807f,
5661                 .flags          = ADDR_TYPE_RT
5662         },
5663         { }
5664 };
5665
5666 /* l4_abe -> timer5 (dma) */
5667 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5668         .master         = &omap44xx_l4_abe_hwmod,
5669         .slave          = &omap44xx_timer5_hwmod,
5670         .clk            = "ocp_abe_iclk",
5671         .addr           = omap44xx_timer5_dma_addrs,
5672         .user           = OCP_USER_SDMA,
5673 };
5674
5675 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5676         {
5677                 .pa_start       = 0x4013a000,
5678                 .pa_end         = 0x4013a07f,
5679                 .flags          = ADDR_TYPE_RT
5680         },
5681         { }
5682 };
5683
5684 /* l4_abe -> timer6 */
5685 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5686         .master         = &omap44xx_l4_abe_hwmod,
5687         .slave          = &omap44xx_timer6_hwmod,
5688         .clk            = "ocp_abe_iclk",
5689         .addr           = omap44xx_timer6_addrs,
5690         .user           = OCP_USER_MPU,
5691 };
5692
5693 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5694         {
5695                 .pa_start       = 0x4903a000,
5696                 .pa_end         = 0x4903a07f,
5697                 .flags          = ADDR_TYPE_RT
5698         },
5699         { }
5700 };
5701
5702 /* l4_abe -> timer6 (dma) */
5703 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5704         .master         = &omap44xx_l4_abe_hwmod,
5705         .slave          = &omap44xx_timer6_hwmod,
5706         .clk            = "ocp_abe_iclk",
5707         .addr           = omap44xx_timer6_dma_addrs,
5708         .user           = OCP_USER_SDMA,
5709 };
5710
5711 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5712         {
5713                 .pa_start       = 0x4013c000,
5714                 .pa_end         = 0x4013c07f,
5715                 .flags          = ADDR_TYPE_RT
5716         },
5717         { }
5718 };
5719
5720 /* l4_abe -> timer7 */
5721 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5722         .master         = &omap44xx_l4_abe_hwmod,
5723         .slave          = &omap44xx_timer7_hwmod,
5724         .clk            = "ocp_abe_iclk",
5725         .addr           = omap44xx_timer7_addrs,
5726         .user           = OCP_USER_MPU,
5727 };
5728
5729 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5730         {
5731                 .pa_start       = 0x4903c000,
5732                 .pa_end         = 0x4903c07f,
5733                 .flags          = ADDR_TYPE_RT
5734         },
5735         { }
5736 };
5737
5738 /* l4_abe -> timer7 (dma) */
5739 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5740         .master         = &omap44xx_l4_abe_hwmod,
5741         .slave          = &omap44xx_timer7_hwmod,
5742         .clk            = "ocp_abe_iclk",
5743         .addr           = omap44xx_timer7_dma_addrs,
5744         .user           = OCP_USER_SDMA,
5745 };
5746
5747 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5748         {
5749                 .pa_start       = 0x4013e000,
5750                 .pa_end         = 0x4013e07f,
5751                 .flags          = ADDR_TYPE_RT
5752         },
5753         { }
5754 };
5755
5756 /* l4_abe -> timer8 */
5757 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5758         .master         = &omap44xx_l4_abe_hwmod,
5759         .slave          = &omap44xx_timer8_hwmod,
5760         .clk            = "ocp_abe_iclk",
5761         .addr           = omap44xx_timer8_addrs,
5762         .user           = OCP_USER_MPU,
5763 };
5764
5765 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5766         {
5767                 .pa_start       = 0x4903e000,
5768                 .pa_end         = 0x4903e07f,
5769                 .flags          = ADDR_TYPE_RT
5770         },
5771         { }
5772 };
5773
5774 /* l4_abe -> timer8 (dma) */
5775 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5776         .master         = &omap44xx_l4_abe_hwmod,
5777         .slave          = &omap44xx_timer8_hwmod,
5778         .clk            = "ocp_abe_iclk",
5779         .addr           = omap44xx_timer8_dma_addrs,
5780         .user           = OCP_USER_SDMA,
5781 };
5782
5783 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5784         {
5785                 .pa_start       = 0x4803e000,
5786                 .pa_end         = 0x4803e07f,
5787                 .flags          = ADDR_TYPE_RT
5788         },
5789         { }
5790 };
5791
5792 /* l4_per -> timer9 */
5793 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5794         .master         = &omap44xx_l4_per_hwmod,
5795         .slave          = &omap44xx_timer9_hwmod,
5796         .clk            = "l4_div_ck",
5797         .addr           = omap44xx_timer9_addrs,
5798         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5799 };
5800
5801 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5802         {
5803                 .pa_start       = 0x48086000,
5804                 .pa_end         = 0x4808607f,
5805                 .flags          = ADDR_TYPE_RT
5806         },
5807         { }
5808 };
5809
5810 /* l4_per -> timer10 */
5811 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5812         .master         = &omap44xx_l4_per_hwmod,
5813         .slave          = &omap44xx_timer10_hwmod,
5814         .clk            = "l4_div_ck",
5815         .addr           = omap44xx_timer10_addrs,
5816         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5817 };
5818
5819 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5820         {
5821                 .pa_start       = 0x48088000,
5822                 .pa_end         = 0x4808807f,
5823                 .flags          = ADDR_TYPE_RT
5824         },
5825         { }
5826 };
5827
5828 /* l4_per -> timer11 */
5829 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5830         .master         = &omap44xx_l4_per_hwmod,
5831         .slave          = &omap44xx_timer11_hwmod,
5832         .clk            = "l4_div_ck",
5833         .addr           = omap44xx_timer11_addrs,
5834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5835 };
5836
5837 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5838         {
5839                 .pa_start       = 0x4806a000,
5840                 .pa_end         = 0x4806a0ff,
5841                 .flags          = ADDR_TYPE_RT
5842         },
5843         { }
5844 };
5845
5846 /* l4_per -> uart1 */
5847 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5848         .master         = &omap44xx_l4_per_hwmod,
5849         .slave          = &omap44xx_uart1_hwmod,
5850         .clk            = "l4_div_ck",
5851         .addr           = omap44xx_uart1_addrs,
5852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5853 };
5854
5855 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5856         {
5857                 .pa_start       = 0x4806c000,
5858                 .pa_end         = 0x4806c0ff,
5859                 .flags          = ADDR_TYPE_RT
5860         },
5861         { }
5862 };
5863
5864 /* l4_per -> uart2 */
5865 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5866         .master         = &omap44xx_l4_per_hwmod,
5867         .slave          = &omap44xx_uart2_hwmod,
5868         .clk            = "l4_div_ck",
5869         .addr           = omap44xx_uart2_addrs,
5870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5871 };
5872
5873 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5874         {
5875                 .pa_start       = 0x48020000,
5876                 .pa_end         = 0x480200ff,
5877                 .flags          = ADDR_TYPE_RT
5878         },
5879         { }
5880 };
5881
5882 /* l4_per -> uart3 */
5883 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5884         .master         = &omap44xx_l4_per_hwmod,
5885         .slave          = &omap44xx_uart3_hwmod,
5886         .clk            = "l4_div_ck",
5887         .addr           = omap44xx_uart3_addrs,
5888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5889 };
5890
5891 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5892         {
5893                 .pa_start       = 0x4806e000,
5894                 .pa_end         = 0x4806e0ff,
5895                 .flags          = ADDR_TYPE_RT
5896         },
5897         { }
5898 };
5899
5900 /* l4_per -> uart4 */
5901 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5902         .master         = &omap44xx_l4_per_hwmod,
5903         .slave          = &omap44xx_uart4_hwmod,
5904         .clk            = "l4_div_ck",
5905         .addr           = omap44xx_uart4_addrs,
5906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5907 };
5908
5909 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5910         {
5911                 .pa_start       = 0x4a0a9000,
5912                 .pa_end         = 0x4a0a93ff,
5913                 .flags          = ADDR_TYPE_RT
5914         },
5915         { }
5916 };
5917
5918 /* l4_cfg -> usb_host_fs */
5919 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
5920         .master         = &omap44xx_l4_cfg_hwmod,
5921         .slave          = &omap44xx_usb_host_fs_hwmod,
5922         .clk            = "l4_div_ck",
5923         .addr           = omap44xx_usb_host_fs_addrs,
5924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5925 };
5926
5927 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5928         {
5929                 .name           = "uhh",
5930                 .pa_start       = 0x4a064000,
5931                 .pa_end         = 0x4a0647ff,
5932                 .flags          = ADDR_TYPE_RT
5933         },
5934         {
5935                 .name           = "ohci",
5936                 .pa_start       = 0x4a064800,
5937                 .pa_end         = 0x4a064bff,
5938         },
5939         {
5940                 .name           = "ehci",
5941                 .pa_start       = 0x4a064c00,
5942                 .pa_end         = 0x4a064fff,
5943         },
5944         {}
5945 };
5946
5947 /* l4_cfg -> usb_host_hs */
5948 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5949         .master         = &omap44xx_l4_cfg_hwmod,
5950         .slave          = &omap44xx_usb_host_hs_hwmod,
5951         .clk            = "l4_div_ck",
5952         .addr           = omap44xx_usb_host_hs_addrs,
5953         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5954 };
5955
5956 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5957         {
5958                 .pa_start       = 0x4a0ab000,
5959                 .pa_end         = 0x4a0ab7ff,
5960                 .flags          = ADDR_TYPE_RT
5961         },
5962         { }
5963 };
5964
5965 /* l4_cfg -> usb_otg_hs */
5966 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5967         .master         = &omap44xx_l4_cfg_hwmod,
5968         .slave          = &omap44xx_usb_otg_hs_hwmod,
5969         .clk            = "l4_div_ck",
5970         .addr           = omap44xx_usb_otg_hs_addrs,
5971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5972 };
5973
5974 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5975         {
5976                 .name           = "tll",
5977                 .pa_start       = 0x4a062000,
5978                 .pa_end         = 0x4a063fff,
5979                 .flags          = ADDR_TYPE_RT
5980         },
5981         {}
5982 };
5983
5984 /* l4_cfg -> usb_tll_hs */
5985 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5986         .master         = &omap44xx_l4_cfg_hwmod,
5987         .slave          = &omap44xx_usb_tll_hs_hwmod,
5988         .clk            = "l4_div_ck",
5989         .addr           = omap44xx_usb_tll_hs_addrs,
5990         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5991 };
5992
5993 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5994         {
5995                 .pa_start       = 0x4a314000,
5996                 .pa_end         = 0x4a31407f,
5997                 .flags          = ADDR_TYPE_RT
5998         },
5999         { }
6000 };
6001
6002 /* l4_wkup -> wd_timer2 */
6003 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6004         .master         = &omap44xx_l4_wkup_hwmod,
6005         .slave          = &omap44xx_wd_timer2_hwmod,
6006         .clk            = "l4_wkup_clk_mux_ck",
6007         .addr           = omap44xx_wd_timer2_addrs,
6008         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6009 };
6010
6011 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6012         {
6013                 .pa_start       = 0x40130000,
6014                 .pa_end         = 0x4013007f,
6015                 .flags          = ADDR_TYPE_RT
6016         },
6017         { }
6018 };
6019
6020 /* l4_abe -> wd_timer3 */
6021 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6022         .master         = &omap44xx_l4_abe_hwmod,
6023         .slave          = &omap44xx_wd_timer3_hwmod,
6024         .clk            = "ocp_abe_iclk",
6025         .addr           = omap44xx_wd_timer3_addrs,
6026         .user           = OCP_USER_MPU,
6027 };
6028
6029 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6030         {
6031                 .pa_start       = 0x49030000,
6032                 .pa_end         = 0x4903007f,
6033                 .flags          = ADDR_TYPE_RT
6034         },
6035         { }
6036 };
6037
6038 /* l4_abe -> wd_timer3 (dma) */
6039 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6040         .master         = &omap44xx_l4_abe_hwmod,
6041         .slave          = &omap44xx_wd_timer3_hwmod,
6042         .clk            = "ocp_abe_iclk",
6043         .addr           = omap44xx_wd_timer3_dma_addrs,
6044         .user           = OCP_USER_SDMA,
6045 };
6046
6047 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6048         &omap44xx_c2c__c2c_target_fw,
6049         &omap44xx_l4_cfg__c2c_target_fw,
6050         &omap44xx_l3_main_1__dmm,
6051         &omap44xx_mpu__dmm,
6052         &omap44xx_c2c__emif_fw,
6053         &omap44xx_dmm__emif_fw,
6054         &omap44xx_l4_cfg__emif_fw,
6055         &omap44xx_iva__l3_instr,
6056         &omap44xx_l3_main_3__l3_instr,
6057         &omap44xx_ocp_wp_noc__l3_instr,
6058         &omap44xx_dsp__l3_main_1,
6059         &omap44xx_dss__l3_main_1,
6060         &omap44xx_l3_main_2__l3_main_1,
6061         &omap44xx_l4_cfg__l3_main_1,
6062         &omap44xx_mmc1__l3_main_1,
6063         &omap44xx_mmc2__l3_main_1,
6064         &omap44xx_mpu__l3_main_1,
6065         &omap44xx_c2c_target_fw__l3_main_2,
6066         &omap44xx_debugss__l3_main_2,
6067         &omap44xx_dma_system__l3_main_2,
6068         &omap44xx_fdif__l3_main_2,
6069         &omap44xx_gpu__l3_main_2,
6070         &omap44xx_hsi__l3_main_2,
6071         &omap44xx_ipu__l3_main_2,
6072         &omap44xx_iss__l3_main_2,
6073         &omap44xx_iva__l3_main_2,
6074         &omap44xx_l3_main_1__l3_main_2,
6075         &omap44xx_l4_cfg__l3_main_2,
6076         /* &omap44xx_usb_host_fs__l3_main_2, */
6077         &omap44xx_usb_host_hs__l3_main_2,
6078         &omap44xx_usb_otg_hs__l3_main_2,
6079         &omap44xx_l3_main_1__l3_main_3,
6080         &omap44xx_l3_main_2__l3_main_3,
6081         &omap44xx_l4_cfg__l3_main_3,
6082         /* &omap44xx_aess__l4_abe, */
6083         &omap44xx_dsp__l4_abe,
6084         &omap44xx_l3_main_1__l4_abe,
6085         &omap44xx_mpu__l4_abe,
6086         &omap44xx_l3_main_1__l4_cfg,
6087         &omap44xx_l3_main_2__l4_per,
6088         &omap44xx_l4_cfg__l4_wkup,
6089         &omap44xx_mpu__mpu_private,
6090         &omap44xx_l4_cfg__ocp_wp_noc,
6091         /* &omap44xx_l4_abe__aess, */
6092         /* &omap44xx_l4_abe__aess_dma, */
6093         &omap44xx_l3_main_2__c2c,
6094         &omap44xx_l4_wkup__counter_32k,
6095         &omap44xx_l4_cfg__ctrl_module_core,
6096         &omap44xx_l4_cfg__ctrl_module_pad_core,
6097         &omap44xx_l4_wkup__ctrl_module_wkup,
6098         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6099         &omap44xx_l3_instr__debugss,
6100         &omap44xx_l4_cfg__dma_system,
6101         &omap44xx_l4_abe__dmic,
6102         &omap44xx_l4_abe__dmic_dma,
6103         &omap44xx_dsp__iva,
6104         /* &omap44xx_dsp__sl2if, */
6105         &omap44xx_l4_cfg__dsp,
6106         &omap44xx_l3_main_2__dss,
6107         &omap44xx_l4_per__dss,
6108         &omap44xx_l3_main_2__dss_dispc,
6109         &omap44xx_l4_per__dss_dispc,
6110         &omap44xx_l3_main_2__dss_dsi1,
6111         &omap44xx_l4_per__dss_dsi1,
6112         &omap44xx_l3_main_2__dss_dsi2,
6113         &omap44xx_l4_per__dss_dsi2,
6114         &omap44xx_l3_main_2__dss_hdmi,
6115         &omap44xx_l4_per__dss_hdmi,
6116         &omap44xx_l3_main_2__dss_rfbi,
6117         &omap44xx_l4_per__dss_rfbi,
6118         &omap44xx_l3_main_2__dss_venc,
6119         &omap44xx_l4_per__dss_venc,
6120         &omap44xx_l4_per__elm,
6121         &omap44xx_emif_fw__emif1,
6122         &omap44xx_emif_fw__emif2,
6123         &omap44xx_l4_cfg__fdif,
6124         &omap44xx_l4_wkup__gpio1,
6125         &omap44xx_l4_per__gpio2,
6126         &omap44xx_l4_per__gpio3,
6127         &omap44xx_l4_per__gpio4,
6128         &omap44xx_l4_per__gpio5,
6129         &omap44xx_l4_per__gpio6,
6130         &omap44xx_l3_main_2__gpmc,
6131         &omap44xx_l3_main_2__gpu,
6132         &omap44xx_l4_per__hdq1w,
6133         &omap44xx_l4_cfg__hsi,
6134         &omap44xx_l4_per__i2c1,
6135         &omap44xx_l4_per__i2c2,
6136         &omap44xx_l4_per__i2c3,
6137         &omap44xx_l4_per__i2c4,
6138         &omap44xx_l3_main_2__ipu,
6139         &omap44xx_l3_main_2__iss,
6140         /* &omap44xx_iva__sl2if, */
6141         &omap44xx_l3_main_2__iva,
6142         &omap44xx_l4_wkup__kbd,
6143         &omap44xx_l4_cfg__mailbox,
6144         &omap44xx_l4_abe__mcasp,
6145         &omap44xx_l4_abe__mcasp_dma,
6146         &omap44xx_l4_abe__mcbsp1,
6147         &omap44xx_l4_abe__mcbsp1_dma,
6148         &omap44xx_l4_abe__mcbsp2,
6149         &omap44xx_l4_abe__mcbsp2_dma,
6150         &omap44xx_l4_abe__mcbsp3,
6151         &omap44xx_l4_abe__mcbsp3_dma,
6152         &omap44xx_l4_per__mcbsp4,
6153         &omap44xx_l4_abe__mcpdm,
6154         &omap44xx_l4_abe__mcpdm_dma,
6155         &omap44xx_l4_per__mcspi1,
6156         &omap44xx_l4_per__mcspi2,
6157         &omap44xx_l4_per__mcspi3,
6158         &omap44xx_l4_per__mcspi4,
6159         &omap44xx_l4_per__mmc1,
6160         &omap44xx_l4_per__mmc2,
6161         &omap44xx_l4_per__mmc3,
6162         &omap44xx_l4_per__mmc4,
6163         &omap44xx_l4_per__mmc5,
6164         &omap44xx_l3_main_2__ocmc_ram,
6165         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6166         &omap44xx_mpu_private__prcm_mpu,
6167         &omap44xx_l4_wkup__cm_core_aon,
6168         &omap44xx_l4_cfg__cm_core,
6169         &omap44xx_l4_wkup__prm,
6170         &omap44xx_l4_wkup__scrm,
6171         /* &omap44xx_l3_main_2__sl2if, */
6172         &omap44xx_l4_abe__slimbus1,
6173         &omap44xx_l4_abe__slimbus1_dma,
6174         &omap44xx_l4_per__slimbus2,
6175         &omap44xx_l4_cfg__smartreflex_core,
6176         &omap44xx_l4_cfg__smartreflex_iva,
6177         &omap44xx_l4_cfg__smartreflex_mpu,
6178         &omap44xx_l4_cfg__spinlock,
6179         &omap44xx_l4_wkup__timer1,
6180         &omap44xx_l4_per__timer2,
6181         &omap44xx_l4_per__timer3,
6182         &omap44xx_l4_per__timer4,
6183         &omap44xx_l4_abe__timer5,
6184         &omap44xx_l4_abe__timer5_dma,
6185         &omap44xx_l4_abe__timer6,
6186         &omap44xx_l4_abe__timer6_dma,
6187         &omap44xx_l4_abe__timer7,
6188         &omap44xx_l4_abe__timer7_dma,
6189         &omap44xx_l4_abe__timer8,
6190         &omap44xx_l4_abe__timer8_dma,
6191         &omap44xx_l4_per__timer9,
6192         &omap44xx_l4_per__timer10,
6193         &omap44xx_l4_per__timer11,
6194         &omap44xx_l4_per__uart1,
6195         &omap44xx_l4_per__uart2,
6196         &omap44xx_l4_per__uart3,
6197         &omap44xx_l4_per__uart4,
6198         /* &omap44xx_l4_cfg__usb_host_fs, */
6199         &omap44xx_l4_cfg__usb_host_hs,
6200         &omap44xx_l4_cfg__usb_otg_hs,
6201         &omap44xx_l4_cfg__usb_tll_hs,
6202         &omap44xx_l4_wkup__wd_timer2,
6203         &omap44xx_l4_abe__wd_timer3,
6204         &omap44xx_l4_abe__wd_timer3_dma,
6205         NULL,
6206 };
6207
6208 int __init omap44xx_hwmod_init(void)
6209 {
6210         omap_hwmod_init();
6211         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6212 }
6213