Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_hwmod_33xx_data.c

   1 /*
   2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
   3  *
   4  * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is automatically generated from the AM33XX hardware databases.
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/i2c-omap.h>
  18
  19 #include "omap_hwmod.h"
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/spi-omap2-mcspi.h>
  22
  23 #include "omap_hwmod_common_data.h"
  24
  25 #include "control.h"
  26 #include "cm33xx.h"
  27 #include "prm33xx.h"
  28 #include "prm-regbits-33xx.h"
  29 #include "i2c.h"
  30 #include "mmc.h"
  31 #include "wd_timer.h"
  32
  33 /*
  34  * IP blocks
  35  */
  36
  37 /*
  38  * 'emif' class
  39  * instance(s): emif
  40  */
  41 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
  42         .rev_offs       = 0x0000,
  43 };
  44
  45 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
  46         .name           = "emif",
  47         .sysc           = &am33xx_emif_sysc,
  48 };
  49
  50 /* emif */
  51 static struct omap_hwmod am33xx_emif_hwmod = {
  52         .name           = "emif",
  53         .class          = &am33xx_emif_hwmod_class,
  54         .clkdm_name     = "l3_clkdm",
  55         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  56         .main_clk       = "dpll_ddr_m2_div2_ck",
  57         .prcm           = {
  58                 .omap4  = {
  59                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  60                         .modulemode     = MODULEMODE_SWCTRL,
  61                 },
  62         },
  63 };
  64
  65 /*
  66  * 'l3' class
  67  * instance(s): l3_main, l3_s, l3_instr
  68  */
  69 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  70         .name           = "l3",
  71 };
  72
  73 static struct omap_hwmod am33xx_l3_main_hwmod = {
  74         .name           = "l3_main",
  75         .class          = &am33xx_l3_hwmod_class,
  76         .clkdm_name     = "l3_clkdm",
  77         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  78         .main_clk       = "l3_gclk",
  79         .prcm           = {
  80                 .omap4  = {
  81                         .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
  82                         .modulemode     = MODULEMODE_SWCTRL,
  83                 },
  84         },
  85 };
  86
  87 /* l3_s */
  88 static struct omap_hwmod am33xx_l3_s_hwmod = {
  89         .name           = "l3_s",
  90         .class          = &am33xx_l3_hwmod_class,
  91         .clkdm_name     = "l3s_clkdm",
  92 };
  93
  94 /* l3_instr */
  95 static struct omap_hwmod am33xx_l3_instr_hwmod = {
  96         .name           = "l3_instr",
  97         .class          = &am33xx_l3_hwmod_class,
  98         .clkdm_name     = "l3_clkdm",
  99         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 100         .main_clk       = "l3_gclk",
 101         .prcm           = {
 102                 .omap4  = {
 103                         .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
 104                         .modulemode     = MODULEMODE_SWCTRL,
 105                 },
 106         },
 107 };
 108
 109 /*
 110  * 'l4' class
 111  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
 112  */
 113 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
 114         .name           = "l4",
 115 };
 116
 117 /* l4_ls */
 118 static struct omap_hwmod am33xx_l4_ls_hwmod = {
 119         .name           = "l4_ls",
 120         .class          = &am33xx_l4_hwmod_class,
 121         .clkdm_name     = "l4ls_clkdm",
 122         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 123         .main_clk       = "l4ls_gclk",
 124         .prcm           = {
 125                 .omap4  = {
 126                         .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
 127                         .modulemode     = MODULEMODE_SWCTRL,
 128                 },
 129         },
 130 };
 131
 132 /* l4_hs */
 133 static struct omap_hwmod am33xx_l4_hs_hwmod = {
 134         .name           = "l4_hs",
 135         .class          = &am33xx_l4_hwmod_class,
 136         .clkdm_name     = "l4hs_clkdm",
 137         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 138         .main_clk       = "l4hs_gclk",
 139         .prcm           = {
 140                 .omap4  = {
 141                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
 142                         .modulemode     = MODULEMODE_SWCTRL,
 143                 },
 144         },
 145 };
 146
 147
 148 /* l4_wkup */
 149 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
 150         .name           = "l4_wkup",
 151         .class          = &am33xx_l4_hwmod_class,
 152         .clkdm_name     = "l4_wkup_clkdm",
 153         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 154         .prcm           = {
 155                 .omap4  = {
 156                         .clkctrl_offs   = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 157                         .modulemode     = MODULEMODE_SWCTRL,
 158                 },
 159         },
 160 };
 161
 162 /*
 163  * 'mpu' class
 164  */
 165 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 166         .name   = "mpu",
 167 };
 168
 169 static struct omap_hwmod am33xx_mpu_hwmod = {
 170         .name           = "mpu",
 171         .class          = &am33xx_mpu_hwmod_class,
 172         .clkdm_name     = "mpu_clkdm",
 173         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 174         .main_clk       = "dpll_mpu_m2_ck",
 175         .prcm           = {
 176                 .omap4  = {
 177                         .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 178                         .modulemode     = MODULEMODE_SWCTRL,
 179                 },
 180         },
 181 };
 182
 183 /*
 184  * 'wakeup m3' class
 185  * Wakeup controller sub-system under wakeup domain
 186  */
 187 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 188         .name           = "wkup_m3",
 189 };
 190
 191 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
 192         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
 193 };
 194
 195 /* wkup_m3  */
 196 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
 197         .name           = "wkup_m3",
 198         .class          = &am33xx_wkup_m3_hwmod_class,
 199         .clkdm_name     = "l4_wkup_aon_clkdm",
 200         /* Keep hardreset asserted */
 201         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
 202         .main_clk       = "dpll_core_m4_div2_ck",
 203         .prcm           = {
 204                 .omap4  = {
 205                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
 206                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
 207                         .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
 208                         .modulemode     = MODULEMODE_SWCTRL,
 209                 },
 210         },
 211         .rst_lines      = am33xx_wkup_m3_resets,
 212         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
 213 };
 214
 215 /*
 216  * 'pru-icss' class
 217  * Programmable Real-Time Unit and Industrial Communication Subsystem
 218  */
 219 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 220         .name   = "pruss",
 221 };
 222
 223 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 224         { .name = "pruss", .rst_shift = 1 },
 225 };
 226
 227 /* pru-icss */
 228 /* Pseudo hwmod for reset control purpose only */
 229 static struct omap_hwmod am33xx_pruss_hwmod = {
 230         .name           = "pruss",
 231         .class          = &am33xx_pruss_hwmod_class,
 232         .clkdm_name     = "pruss_ocp_clkdm",
 233         .main_clk       = "pruss_ocp_gclk",
 234         .prcm           = {
 235                 .omap4  = {
 236                         .clkctrl_offs   = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
 237                         .rstctrl_offs   = AM33XX_RM_PER_RSTCTRL_OFFSET,
 238                         .modulemode     = MODULEMODE_SWCTRL,
 239                 },
 240         },
 241         .rst_lines      = am33xx_pruss_resets,
 242         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 243 };
 244
 245 /* gfx */
 246 /* Pseudo hwmod for reset control purpose only */
 247 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 248         .name   = "gfx",
 249 };
 250
 251 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 252         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 253 };
 254
 255 static struct omap_hwmod am33xx_gfx_hwmod = {
 256         .name           = "gfx",
 257         .class          = &am33xx_gfx_hwmod_class,
 258         .clkdm_name     = "gfx_l3_clkdm",
 259         .main_clk       = "gfx_fck_div_ck",
 260         .prcm           = {
 261                 .omap4  = {
 262                         .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
 263                         .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
 264                         .rstst_offs     = AM33XX_RM_GFX_RSTST_OFFSET,
 265                         .modulemode     = MODULEMODE_SWCTRL,
 266                 },
 267         },
 268         .rst_lines      = am33xx_gfx_resets,
 269         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 270 };
 271
 272 /*
 273  * 'prcm' class
 274  * power and reset manager (whole prcm infrastructure)
 275  */
 276 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 277         .name   = "prcm",
 278 };
 279
 280 /* prcm */
 281 static struct omap_hwmod am33xx_prcm_hwmod = {
 282         .name           = "prcm",
 283         .class          = &am33xx_prcm_hwmod_class,
 284         .clkdm_name     = "l4_wkup_clkdm",
 285 };
 286
 287 /*
 288  * 'adc/tsc' class
 289  * TouchScreen Controller (Anolog-To-Digital Converter)
 290  */
 291 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
 292         .rev_offs       = 0x00,
 293         .sysc_offs      = 0x10,
 294         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 295         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 296                         SIDLE_SMART_WKUP),
 297         .sysc_fields    = &omap_hwmod_sysc_type2,
 298 };
 299
 300 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
 301         .name           = "adc_tsc",
 302         .sysc           = &am33xx_adc_tsc_sysc,
 303 };
 304
 305 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 306         .name           = "adc_tsc",
 307         .class          = &am33xx_adc_tsc_hwmod_class,
 308         .clkdm_name     = "l4_wkup_clkdm",
 309         .main_clk       = "adc_tsc_fck",
 310         .prcm           = {
 311                 .omap4  = {
 312                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 313                         .modulemode     = MODULEMODE_SWCTRL,
 314                 },
 315         },
 316 };
 317
 318 /*
 319  * Modules omap_hwmod structures
 320  *
 321  * The following IPs are excluded for the moment because:
 322  * - They do not need an explicit SW control using omap_hwmod API.
 323  * - They still need to be validated with the driver
 324  *   properly adapted to omap_hwmod / omap_device
 325  *
 326  *    - cEFUSE (doesn't fall under any ocp_if)
 327  *    - clkdiv32k
 328  *    - ocp watch point
 329  */
 330 #if 0
 331 /*
 332  * 'cefuse' class
 333  */
 334 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
 335         .name           = "cefuse",
 336 };
 337
 338 static struct omap_hwmod am33xx_cefuse_hwmod = {
 339         .name           = "cefuse",
 340         .class          = &am33xx_cefuse_hwmod_class,
 341         .clkdm_name     = "l4_cefuse_clkdm",
 342         .main_clk       = "cefuse_fck",
 343         .prcm           = {
 344                 .omap4  = {
 345                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
 346                         .modulemode     = MODULEMODE_SWCTRL,
 347                 },
 348         },
 349 };
 350
 351 /*
 352  * 'clkdiv32k' class
 353  */
 354 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
 355         .name           = "clkdiv32k",
 356 };
 357
 358 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 359         .name           = "clkdiv32k",
 360         .class          = &am33xx_clkdiv32k_hwmod_class,
 361         .clkdm_name     = "clk_24mhz_clkdm",
 362         .main_clk       = "clkdiv32k_ick",
 363         .prcm           = {
 364                 .omap4  = {
 365                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 366                         .modulemode     = MODULEMODE_SWCTRL,
 367                 },
 368         },
 369 };
 370
 371 /* ocpwp */
 372 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 373         .name           = "ocpwp",
 374 };
 375
 376 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 377         .name           = "ocpwp",
 378         .class          = &am33xx_ocpwp_hwmod_class,
 379         .clkdm_name     = "l4ls_clkdm",
 380         .main_clk       = "l4ls_gclk",
 381         .prcm           = {
 382                 .omap4  = {
 383                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 384                         .modulemode     = MODULEMODE_SWCTRL,
 385                 },
 386         },
 387 };
 388 #endif
 389
 390 /*
 391  * 'aes0' class
 392  */
 393 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 394         .rev_offs       = 0x80,
 395         .sysc_offs      = 0x84,
 396         .syss_offs      = 0x88,
 397         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 398 };
 399
 400 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 401         .name           = "aes0",
 402         .sysc           = &am33xx_aes0_sysc,
 403 };
 404
 405 static struct omap_hwmod am33xx_aes0_hwmod = {
 406         .name           = "aes",
 407         .class          = &am33xx_aes0_hwmod_class,
 408         .clkdm_name     = "l3_clkdm",
 409         .main_clk       = "aes0_fck",
 410         .prcm           = {
 411                 .omap4  = {
 412                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
 413                         .modulemode     = MODULEMODE_SWCTRL,
 414                 },
 415         },
 416 };
 417
 418 /* sha0 HIB2 (the 'P' (public) device) */
 419 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 420         .rev_offs       = 0x100,
 421         .sysc_offs      = 0x110,
 422         .syss_offs      = 0x114,
 423         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 424 };
 425
 426 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 427         .name           = "sha0",
 428         .sysc           = &am33xx_sha0_sysc,
 429 };
 430
 431 static struct omap_hwmod am33xx_sha0_hwmod = {
 432         .name           = "sham",
 433         .class          = &am33xx_sha0_hwmod_class,
 434         .clkdm_name     = "l3_clkdm",
 435         .main_clk       = "l3_gclk",
 436         .prcm           = {
 437                 .omap4  = {
 438                         .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
 439                         .modulemode     = MODULEMODE_SWCTRL,
 440                 },
 441         },
 442 };
 443
 444 /* ocmcram */
 445 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 446         .name = "ocmcram",
 447 };
 448
 449 static struct omap_hwmod am33xx_ocmcram_hwmod = {
 450         .name           = "ocmcram",
 451         .class          = &am33xx_ocmcram_hwmod_class,
 452         .clkdm_name     = "l3_clkdm",
 453         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 454         .main_clk       = "l3_gclk",
 455         .prcm           = {
 456                 .omap4  = {
 457                         .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
 458                         .modulemode     = MODULEMODE_SWCTRL,
 459                 },
 460         },
 461 };
 462
 463 /*
 464  * 'debugss' class
 465  * debug sub system
 466  */
 467 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
 468         { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
 469         { .role = "dbg_clka", .clk = "dbg_clka_ck" },
 470 };
 471
 472 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 473         .name           = "debugss",
 474 };
 475
 476 static struct omap_hwmod am33xx_debugss_hwmod = {
 477         .name           = "debugss",
 478         .class          = &am33xx_debugss_hwmod_class,
 479         .clkdm_name     = "l3_aon_clkdm",
 480         .main_clk       = "trace_clk_div_ck",
 481         .prcm           = {
 482                 .omap4  = {
 483                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 484                         .modulemode     = MODULEMODE_SWCTRL,
 485                 },
 486         },
 487         .opt_clks       = debugss_opt_clks,
 488         .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
 489 };
 490
 491 /* 'smartreflex' class */
 492 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 493         .name           = "smartreflex",
 494 };
 495
 496 /* smartreflex0 */
 497 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
 498         .name           = "smartreflex0",
 499         .class          = &am33xx_smartreflex_hwmod_class,
 500         .clkdm_name     = "l4_wkup_clkdm",
 501         .main_clk       = "smartreflex0_fck",
 502         .prcm           = {
 503                 .omap4  = {
 504                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
 505                         .modulemode     = MODULEMODE_SWCTRL,
 506                 },
 507         },
 508 };
 509
 510 /* smartreflex1 */
 511 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
 512         .name           = "smartreflex1",
 513         .class          = &am33xx_smartreflex_hwmod_class,
 514         .clkdm_name     = "l4_wkup_clkdm",
 515         .main_clk       = "smartreflex1_fck",
 516         .prcm           = {
 517                 .omap4  = {
 518                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
 519                         .modulemode     = MODULEMODE_SWCTRL,
 520                 },
 521         },
 522 };
 523
 524 /*
 525  * 'control' module class
 526  */
 527 static struct omap_hwmod_class am33xx_control_hwmod_class = {
 528         .name           = "control",
 529 };
 530
 531 static struct omap_hwmod am33xx_control_hwmod = {
 532         .name           = "control",
 533         .class          = &am33xx_control_hwmod_class,
 534         .clkdm_name     = "l4_wkup_clkdm",
 535         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 536         .main_clk       = "dpll_core_m4_div2_ck",
 537         .prcm           = {
 538                 .omap4  = {
 539                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
 540                         .modulemode     = MODULEMODE_SWCTRL,
 541                 },
 542         },
 543 };
 544
 545 /*
 546  * 'cpgmac' class
 547  * cpsw/cpgmac sub system
 548  */
 549 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 550         .rev_offs       = 0x0,
 551         .sysc_offs      = 0x8,
 552         .syss_offs      = 0x4,
 553         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 554                            SYSS_HAS_RESET_STATUS),
 555         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 556                            MSTANDBY_NO),
 557         .sysc_fields    = &omap_hwmod_sysc_type3,
 558 };
 559
 560 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 561         .name           = "cpgmac0",
 562         .sysc           = &am33xx_cpgmac_sysc,
 563 };
 564
 565 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
 566         .name           = "cpgmac0",
 567         .class          = &am33xx_cpgmac0_hwmod_class,
 568         .clkdm_name     = "cpsw_125mhz_clkdm",
 569         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 570         .main_clk       = "cpsw_125mhz_gclk",
 571         .mpu_rt_idx     = 1,
 572         .prcm           = {
 573                 .omap4  = {
 574                         .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
 575                         .modulemode     = MODULEMODE_SWCTRL,
 576                 },
 577         },
 578 };
 579
 580 /*
 581  * mdio class
 582  */
 583 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 584         .name           = "davinci_mdio",
 585 };
 586
 587 static struct omap_hwmod am33xx_mdio_hwmod = {
 588         .name           = "davinci_mdio",
 589         .class          = &am33xx_mdio_hwmod_class,
 590         .clkdm_name     = "cpsw_125mhz_clkdm",
 591         .main_clk       = "cpsw_125mhz_gclk",
 592 };
 593
 594 /*
 595  * dcan class
 596  */
 597 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 598         .name = "d_can",
 599 };
 600
 601 /* dcan0 */
 602 static struct omap_hwmod am33xx_dcan0_hwmod = {
 603         .name           = "d_can0",
 604         .class          = &am33xx_dcan_hwmod_class,
 605         .clkdm_name     = "l4ls_clkdm",
 606         .main_clk       = "dcan0_fck",
 607         .prcm           = {
 608                 .omap4  = {
 609                         .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
 610                         .modulemode     = MODULEMODE_SWCTRL,
 611                 },
 612         },
 613 };
 614
 615 /* dcan1 */
 616 static struct omap_hwmod am33xx_dcan1_hwmod = {
 617         .name           = "d_can1",
 618         .class          = &am33xx_dcan_hwmod_class,
 619         .clkdm_name     = "l4ls_clkdm",
 620         .main_clk       = "dcan1_fck",
 621         .prcm           = {
 622                 .omap4  = {
 623                         .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
 624                         .modulemode     = MODULEMODE_SWCTRL,
 625                 },
 626         },
 627 };
 628
 629 /* elm */
 630 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 631         .rev_offs       = 0x0000,
 632         .sysc_offs      = 0x0010,
 633         .syss_offs      = 0x0014,
 634         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 635                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 636                         SYSS_HAS_RESET_STATUS),
 637         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 638         .sysc_fields    = &omap_hwmod_sysc_type1,
 639 };
 640
 641 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 642         .name           = "elm",
 643         .sysc           = &am33xx_elm_sysc,
 644 };
 645
 646 static struct omap_hwmod am33xx_elm_hwmod = {
 647         .name           = "elm",
 648         .class          = &am33xx_elm_hwmod_class,
 649         .clkdm_name     = "l4ls_clkdm",
 650         .main_clk       = "l4ls_gclk",
 651         .prcm           = {
 652                 .omap4  = {
 653                         .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
 654                         .modulemode     = MODULEMODE_SWCTRL,
 655                 },
 656         },
 657 };
 658
 659 /* pwmss  */
 660 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 661         .rev_offs       = 0x0,
 662         .sysc_offs      = 0x4,
 663         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 664         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 665                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 666                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 667         .sysc_fields    = &omap_hwmod_sysc_type2,
 668 };
 669
 670 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 671         .name           = "epwmss",
 672         .sysc           = &am33xx_epwmss_sysc,
 673 };
 674
 675 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
 676         .name           = "ecap",
 677 };
 678
 679 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
 680         .name           = "eqep",
 681 };
 682
 683 static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
 684         .name           = "ehrpwm",
 685 };
 686
 687 /* epwmss0 */
 688 static struct omap_hwmod am33xx_epwmss0_hwmod = {
 689         .name           = "epwmss0",
 690         .class          = &am33xx_epwmss_hwmod_class,
 691         .clkdm_name     = "l4ls_clkdm",
 692         .main_clk       = "l4ls_gclk",
 693         .prcm           = {
 694                 .omap4  = {
 695                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
 696                         .modulemode     = MODULEMODE_SWCTRL,
 697                 },
 698         },
 699 };
 700
 701 /* ecap0 */
 702 static struct omap_hwmod am33xx_ecap0_hwmod = {
 703         .name           = "ecap0",
 704         .class          = &am33xx_ecap_hwmod_class,
 705         .clkdm_name     = "l4ls_clkdm",
 706         .main_clk       = "l4ls_gclk",
 707 };
 708
 709 /* eqep0 */
 710 static struct omap_hwmod am33xx_eqep0_hwmod = {
 711         .name           = "eqep0",
 712         .class          = &am33xx_eqep_hwmod_class,
 713         .clkdm_name     = "l4ls_clkdm",
 714         .main_clk       = "l4ls_gclk",
 715 };
 716
 717 /* ehrpwm0 */
 718 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
 719         .name           = "ehrpwm0",
 720         .class          = &am33xx_ehrpwm_hwmod_class,
 721         .clkdm_name     = "l4ls_clkdm",
 722         .main_clk       = "l4ls_gclk",
 723 };
 724
 725 /* epwmss1 */
 726 static struct omap_hwmod am33xx_epwmss1_hwmod = {
 727         .name           = "epwmss1",
 728         .class          = &am33xx_epwmss_hwmod_class,
 729         .clkdm_name     = "l4ls_clkdm",
 730         .main_clk       = "l4ls_gclk",
 731         .prcm           = {
 732                 .omap4  = {
 733                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
 734                         .modulemode     = MODULEMODE_SWCTRL,
 735                 },
 736         },
 737 };
 738
 739 /* ecap1 */
 740 static struct omap_hwmod am33xx_ecap1_hwmod = {
 741         .name           = "ecap1",
 742         .class          = &am33xx_ecap_hwmod_class,
 743         .clkdm_name     = "l4ls_clkdm",
 744         .main_clk       = "l4ls_gclk",
 745 };
 746
 747 /* eqep1 */
 748 static struct omap_hwmod am33xx_eqep1_hwmod = {
 749         .name           = "eqep1",
 750         .class          = &am33xx_eqep_hwmod_class,
 751         .clkdm_name     = "l4ls_clkdm",
 752         .main_clk       = "l4ls_gclk",
 753 };
 754
 755 /* ehrpwm1 */
 756 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
 757         .name           = "ehrpwm1",
 758         .class          = &am33xx_ehrpwm_hwmod_class,
 759         .clkdm_name     = "l4ls_clkdm",
 760         .main_clk       = "l4ls_gclk",
 761 };
 762
 763 /* epwmss2 */
 764 static struct omap_hwmod am33xx_epwmss2_hwmod = {
 765         .name           = "epwmss2",
 766         .class          = &am33xx_epwmss_hwmod_class,
 767         .clkdm_name     = "l4ls_clkdm",
 768         .main_clk       = "l4ls_gclk",
 769         .prcm           = {
 770                 .omap4  = {
 771                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
 772                         .modulemode     = MODULEMODE_SWCTRL,
 773                 },
 774         },
 775 };
 776
 777 /* ecap2 */
 778 static struct omap_hwmod am33xx_ecap2_hwmod = {
 779         .name           = "ecap2",
 780         .class          = &am33xx_ecap_hwmod_class,
 781         .clkdm_name     = "l4ls_clkdm",
 782         .main_clk       = "l4ls_gclk",
 783 };
 784
 785 /* eqep2 */
 786 static struct omap_hwmod am33xx_eqep2_hwmod = {
 787         .name           = "eqep2",
 788         .class          = &am33xx_eqep_hwmod_class,
 789         .clkdm_name     = "l4ls_clkdm",
 790         .main_clk       = "l4ls_gclk",
 791 };
 792
 793 /* ehrpwm2 */
 794 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 795         .name           = "ehrpwm2",
 796         .class          = &am33xx_ehrpwm_hwmod_class,
 797         .clkdm_name     = "l4ls_clkdm",
 798         .main_clk       = "l4ls_gclk",
 799 };
 800
 801 /*
 802  * 'gpio' class: for gpio 0,1,2,3
 803  */
 804 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 805         .rev_offs       = 0x0000,
 806         .sysc_offs      = 0x0010,
 807         .syss_offs      = 0x0114,
 808         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 809                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 810                           SYSS_HAS_RESET_STATUS),
 811         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 812                           SIDLE_SMART_WKUP),
 813         .sysc_fields    = &omap_hwmod_sysc_type1,
 814 };
 815
 816 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 817         .name           = "gpio",
 818         .sysc           = &am33xx_gpio_sysc,
 819         .rev            = 2,
 820 };
 821
 822 static struct omap_gpio_dev_attr gpio_dev_attr = {
 823         .bank_width     = 32,
 824         .dbck_flag      = true,
 825 };
 826
 827 /* gpio0 */
 828 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
 829         { .role = "dbclk", .clk = "gpio0_dbclk" },
 830 };
 831
 832 static struct omap_hwmod am33xx_gpio0_hwmod = {
 833         .name           = "gpio1",
 834         .class          = &am33xx_gpio_hwmod_class,
 835         .clkdm_name     = "l4_wkup_clkdm",
 836         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 837         .main_clk       = "dpll_core_m4_div2_ck",
 838         .prcm           = {
 839                 .omap4  = {
 840                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
 841                         .modulemode     = MODULEMODE_SWCTRL,
 842                 },
 843         },
 844         .opt_clks       = gpio0_opt_clks,
 845         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
 846         .dev_attr       = &gpio_dev_attr,
 847 };
 848
 849 /* gpio1 */
 850 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 851         { .role = "dbclk", .clk = "gpio1_dbclk" },
 852 };
 853
 854 static struct omap_hwmod am33xx_gpio1_hwmod = {
 855         .name           = "gpio2",
 856         .class          = &am33xx_gpio_hwmod_class,
 857         .clkdm_name     = "l4ls_clkdm",
 858         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 859         .main_clk       = "l4ls_gclk",
 860         .prcm           = {
 861                 .omap4  = {
 862                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
 863                         .modulemode     = MODULEMODE_SWCTRL,
 864                 },
 865         },
 866         .opt_clks       = gpio1_opt_clks,
 867         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 868         .dev_attr       = &gpio_dev_attr,
 869 };
 870
 871 /* gpio2 */
 872 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 873         { .role = "dbclk", .clk = "gpio2_dbclk" },
 874 };
 875
 876 static struct omap_hwmod am33xx_gpio2_hwmod = {
 877         .name           = "gpio3",
 878         .class          = &am33xx_gpio_hwmod_class,
 879         .clkdm_name     = "l4ls_clkdm",
 880         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 881         .main_clk       = "l4ls_gclk",
 882         .prcm           = {
 883                 .omap4  = {
 884                         .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
 885                         .modulemode     = MODULEMODE_SWCTRL,
 886                 },
 887         },
 888         .opt_clks       = gpio2_opt_clks,
 889         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 890         .dev_attr       = &gpio_dev_attr,
 891 };
 892
 893 /* gpio3 */
 894 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 895         { .role = "dbclk", .clk = "gpio3_dbclk" },
 896 };
 897
 898 static struct omap_hwmod am33xx_gpio3_hwmod = {
 899         .name           = "gpio4",
 900         .class          = &am33xx_gpio_hwmod_class,
 901         .clkdm_name     = "l4ls_clkdm",
 902         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 903         .main_clk       = "l4ls_gclk",
 904         .prcm           = {
 905                 .omap4  = {
 906                         .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
 907                         .modulemode     = MODULEMODE_SWCTRL,
 908                 },
 909         },
 910         .opt_clks       = gpio3_opt_clks,
 911         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 912         .dev_attr       = &gpio_dev_attr,
 913 };
 914
 915 /* gpmc */
 916 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 917         .rev_offs       = 0x0,
 918         .sysc_offs      = 0x10,
 919         .syss_offs      = 0x14,
 920         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 921                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 922         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 923         .sysc_fields    = &omap_hwmod_sysc_type1,
 924 };
 925
 926 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 927         .name           = "gpmc",
 928         .sysc           = &gpmc_sysc,
 929 };
 930
 931 static struct omap_hwmod am33xx_gpmc_hwmod = {
 932         .name           = "gpmc",
 933         .class          = &am33xx_gpmc_hwmod_class,
 934         .clkdm_name     = "l3s_clkdm",
 935         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 936         .main_clk       = "l3s_gclk",
 937         .prcm           = {
 938                 .omap4  = {
 939                         .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
 940                         .modulemode     = MODULEMODE_SWCTRL,
 941                 },
 942         },
 943 };
 944
 945 /* 'i2c' class */
 946 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
 947         .sysc_offs      = 0x0010,
 948         .syss_offs      = 0x0090,
 949         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 950                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 951                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 952         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 953                           SIDLE_SMART_WKUP),
 954         .sysc_fields    = &omap_hwmod_sysc_type1,
 955 };
 956
 957 static struct omap_hwmod_class i2c_class = {
 958         .name           = "i2c",
 959         .sysc           = &am33xx_i2c_sysc,
 960         .rev            = OMAP_I2C_IP_VERSION_2,
 961         .reset          = &omap_i2c_reset,
 962 };
 963
 964 static struct omap_i2c_dev_attr i2c_dev_attr = {
 965         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 966 };
 967
 968 /* i2c1 */
 969 static struct omap_hwmod am33xx_i2c1_hwmod = {
 970         .name           = "i2c1",
 971         .class          = &i2c_class,
 972         .clkdm_name     = "l4_wkup_clkdm",
 973         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 974         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
 975         .prcm           = {
 976                 .omap4  = {
 977                         .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
 978                         .modulemode     = MODULEMODE_SWCTRL,
 979                 },
 980         },
 981         .dev_attr       = &i2c_dev_attr,
 982 };
 983
 984 /* i2c1 */
 985 static struct omap_hwmod am33xx_i2c2_hwmod = {
 986         .name           = "i2c2",
 987         .class          = &i2c_class,
 988         .clkdm_name     = "l4ls_clkdm",
 989         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 990         .main_clk       = "dpll_per_m2_div4_ck",
 991         .prcm           = {
 992                 .omap4 = {
 993                         .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
 994                         .modulemode     = MODULEMODE_SWCTRL,
 995                 },
 996         },
 997         .dev_attr       = &i2c_dev_attr,
 998 };
 999
1000 /* i2c3 */
1001 static struct omap_hwmod am33xx_i2c3_hwmod = {
1002         .name           = "i2c3",
1003         .class          = &i2c_class,
1004         .clkdm_name     = "l4ls_clkdm",
1005         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1006         .main_clk       = "dpll_per_m2_div4_ck",
1007         .prcm           = {
1008                 .omap4  = {
1009                         .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1010                         .modulemode     = MODULEMODE_SWCTRL,
1011                 },
1012         },
1013         .dev_attr       = &i2c_dev_attr,
1014 };
1015
1016
1017 /* lcdc */
1018 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1019         .rev_offs       = 0x0,
1020         .sysc_offs      = 0x54,
1021         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1022         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1023         .sysc_fields    = &omap_hwmod_sysc_type2,
1024 };
1025
1026 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1027         .name           = "lcdc",
1028         .sysc           = &lcdc_sysc,
1029 };
1030
1031 static struct omap_hwmod am33xx_lcdc_hwmod = {
1032         .name           = "lcdc",
1033         .class          = &am33xx_lcdc_hwmod_class,
1034         .clkdm_name     = "lcdc_clkdm",
1035         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1036         .main_clk       = "lcd_gclk",
1037         .prcm           = {
1038                 .omap4  = {
1039                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1040                         .modulemode     = MODULEMODE_SWCTRL,
1041                 },
1042         },
1043 };
1044
1045 /*
1046  * 'mailbox' class
1047  * mailbox module allowing communication between the on-chip processors using a
1048  * queued mailbox-interrupt mechanism.
1049  */
1050 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1051         .rev_offs       = 0x0000,
1052         .sysc_offs      = 0x0010,
1053         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1054                           SYSC_HAS_SOFTRESET),
1055         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1056         .sysc_fields    = &omap_hwmod_sysc_type2,
1057 };
1058
1059 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1060         .name   = "mailbox",
1061         .sysc   = &am33xx_mailbox_sysc,
1062 };
1063
1064 static struct omap_hwmod am33xx_mailbox_hwmod = {
1065         .name           = "mailbox",
1066         .class          = &am33xx_mailbox_hwmod_class,
1067         .clkdm_name     = "l4ls_clkdm",
1068         .main_clk       = "l4ls_gclk",
1069         .prcm = {
1070                 .omap4 = {
1071                         .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1072                         .modulemode     = MODULEMODE_SWCTRL,
1073                 },
1074         },
1075 };
1076
1077 /*
1078  * 'mcasp' class
1079  */
1080 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1081         .rev_offs       = 0x0,
1082         .sysc_offs      = 0x4,
1083         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1084         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1085         .sysc_fields    = &omap_hwmod_sysc_type3,
1086 };
1087
1088 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1089         .name           = "mcasp",
1090         .sysc           = &am33xx_mcasp_sysc,
1091 };
1092
1093 /* mcasp0 */
1094 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1095         .name           = "mcasp0",
1096         .class          = &am33xx_mcasp_hwmod_class,
1097         .clkdm_name     = "l3s_clkdm",
1098         .main_clk       = "mcasp0_fck",
1099         .prcm           = {
1100                 .omap4  = {
1101                         .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1102                         .modulemode     = MODULEMODE_SWCTRL,
1103                 },
1104         },
1105 };
1106
1107 /* mcasp1 */
1108 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1109         .name           = "mcasp1",
1110         .class          = &am33xx_mcasp_hwmod_class,
1111         .clkdm_name     = "l3s_clkdm",
1112         .main_clk       = "mcasp1_fck",
1113         .prcm           = {
1114                 .omap4  = {
1115                         .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1116                         .modulemode     = MODULEMODE_SWCTRL,
1117                 },
1118         },
1119 };
1120
1121 /* 'mmc' class */
1122 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1123         .rev_offs       = 0x1fc,
1124         .sysc_offs      = 0x10,
1125         .syss_offs      = 0x14,
1126         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1127                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1128                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1129         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1130         .sysc_fields    = &omap_hwmod_sysc_type1,
1131 };
1132
1133 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1134         .name           = "mmc",
1135         .sysc           = &am33xx_mmc_sysc,
1136 };
1137
1138 /* mmc0 */
1139 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1140         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1141 };
1142
1143 static struct omap_hwmod am33xx_mmc0_hwmod = {
1144         .name           = "mmc1",
1145         .class          = &am33xx_mmc_hwmod_class,
1146         .clkdm_name     = "l4ls_clkdm",
1147         .main_clk       = "mmc_clk",
1148         .prcm           = {
1149                 .omap4  = {
1150                         .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1151                         .modulemode     = MODULEMODE_SWCTRL,
1152                 },
1153         },
1154         .dev_attr       = &am33xx_mmc0_dev_attr,
1155 };
1156
1157 /* mmc1 */
1158 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1159         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1160 };
1161
1162 static struct omap_hwmod am33xx_mmc1_hwmod = {
1163         .name           = "mmc2",
1164         .class          = &am33xx_mmc_hwmod_class,
1165         .clkdm_name     = "l4ls_clkdm",
1166         .main_clk       = "mmc_clk",
1167         .prcm           = {
1168                 .omap4  = {
1169                         .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1170                         .modulemode     = MODULEMODE_SWCTRL,
1171                 },
1172         },
1173         .dev_attr       = &am33xx_mmc1_dev_attr,
1174 };
1175
1176 /* mmc2 */
1177 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1178         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1179 };
1180 static struct omap_hwmod am33xx_mmc2_hwmod = {
1181         .name           = "mmc3",
1182         .class          = &am33xx_mmc_hwmod_class,
1183         .clkdm_name     = "l3s_clkdm",
1184         .main_clk       = "mmc_clk",
1185         .prcm           = {
1186                 .omap4  = {
1187                         .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1188                         .modulemode     = MODULEMODE_SWCTRL,
1189                 },
1190         },
1191         .dev_attr       = &am33xx_mmc2_dev_attr,
1192 };
1193
1194 /*
1195  * 'rtc' class
1196  * rtc subsystem
1197  */
1198 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1199         .rev_offs       = 0x0074,
1200         .sysc_offs      = 0x0078,
1201         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1202         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
1203                           SIDLE_SMART | SIDLE_SMART_WKUP),
1204         .sysc_fields    = &omap_hwmod_sysc_type3,
1205 };
1206
1207 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1208         .name           = "rtc",
1209         .sysc           = &am33xx_rtc_sysc,
1210 };
1211
1212 static struct omap_hwmod am33xx_rtc_hwmod = {
1213         .name           = "rtc",
1214         .class          = &am33xx_rtc_hwmod_class,
1215         .clkdm_name     = "l4_rtc_clkdm",
1216         .main_clk       = "clk_32768_ck",
1217         .prcm           = {
1218                 .omap4  = {
1219                         .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1220                         .modulemode     = MODULEMODE_SWCTRL,
1221                 },
1222         },
1223 };
1224
1225 /* 'spi' class */
1226 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1227         .rev_offs       = 0x0000,
1228         .sysc_offs      = 0x0110,
1229         .syss_offs      = 0x0114,
1230         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1231                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1232                           SYSS_HAS_RESET_STATUS),
1233         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1234         .sysc_fields    = &omap_hwmod_sysc_type1,
1235 };
1236
1237 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1238         .name           = "mcspi",
1239         .sysc           = &am33xx_mcspi_sysc,
1240         .rev            = OMAP4_MCSPI_REV,
1241 };
1242
1243 /* spi0 */
1244 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1245         .num_chipselect = 2,
1246 };
1247 static struct omap_hwmod am33xx_spi0_hwmod = {
1248         .name           = "spi0",
1249         .class          = &am33xx_spi_hwmod_class,
1250         .clkdm_name     = "l4ls_clkdm",
1251         .main_clk       = "dpll_per_m2_div4_ck",
1252         .prcm           = {
1253                 .omap4  = {
1254                         .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1255                         .modulemode     = MODULEMODE_SWCTRL,
1256                 },
1257         },
1258         .dev_attr       = &mcspi_attrib,
1259 };
1260
1261 /* spi1 */
1262 static struct omap_hwmod am33xx_spi1_hwmod = {
1263         .name           = "spi1",
1264         .class          = &am33xx_spi_hwmod_class,
1265         .clkdm_name     = "l4ls_clkdm",
1266         .main_clk       = "dpll_per_m2_div4_ck",
1267         .prcm           = {
1268                 .omap4  = {
1269                         .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1270                         .modulemode     = MODULEMODE_SWCTRL,
1271                 },
1272         },
1273         .dev_attr       = &mcspi_attrib,
1274 };
1275
1276 /*
1277  * 'spinlock' class
1278  * spinlock provides hardware assistance for synchronizing the
1279  * processes running on multiple processors
1280  */
1281 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1282         .name           = "spinlock",
1283 };
1284
1285 static struct omap_hwmod am33xx_spinlock_hwmod = {
1286         .name           = "spinlock",
1287         .class          = &am33xx_spinlock_hwmod_class,
1288         .clkdm_name     = "l4ls_clkdm",
1289         .main_clk       = "l4ls_gclk",
1290         .prcm           = {
1291                 .omap4  = {
1292                         .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1293                         .modulemode     = MODULEMODE_SWCTRL,
1294                 },
1295         },
1296 };
1297
1298 /* 'timer 2-7' class */
1299 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1300         .rev_offs       = 0x0000,
1301         .sysc_offs      = 0x0010,
1302         .syss_offs      = 0x0014,
1303         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1304         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1305                           SIDLE_SMART_WKUP),
1306         .sysc_fields    = &omap_hwmod_sysc_type2,
1307 };
1308
1309 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1310         .name           = "timer",
1311         .sysc           = &am33xx_timer_sysc,
1312 };
1313
1314 /* timer1 1ms */
1315 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1316         .rev_offs       = 0x0000,
1317         .sysc_offs      = 0x0010,
1318         .syss_offs      = 0x0014,
1319         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1320                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1321                         SYSS_HAS_RESET_STATUS),
1322         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1323         .sysc_fields    = &omap_hwmod_sysc_type1,
1324 };
1325
1326 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1327         .name           = "timer",
1328         .sysc           = &am33xx_timer1ms_sysc,
1329 };
1330
1331 static struct omap_hwmod am33xx_timer1_hwmod = {
1332         .name           = "timer1",
1333         .class          = &am33xx_timer1ms_hwmod_class,
1334         .clkdm_name     = "l4_wkup_clkdm",
1335         .main_clk       = "timer1_fck",
1336         .prcm           = {
1337                 .omap4  = {
1338                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1339                         .modulemode     = MODULEMODE_SWCTRL,
1340                 },
1341         },
1342 };
1343
1344 static struct omap_hwmod am33xx_timer2_hwmod = {
1345         .name           = "timer2",
1346         .class          = &am33xx_timer_hwmod_class,
1347         .clkdm_name     = "l4ls_clkdm",
1348         .main_clk       = "timer2_fck",
1349         .prcm           = {
1350                 .omap4  = {
1351                         .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1352                         .modulemode     = MODULEMODE_SWCTRL,
1353                 },
1354         },
1355 };
1356
1357 static struct omap_hwmod am33xx_timer3_hwmod = {
1358         .name           = "timer3",
1359         .class          = &am33xx_timer_hwmod_class,
1360         .clkdm_name     = "l4ls_clkdm",
1361         .main_clk       = "timer3_fck",
1362         .prcm           = {
1363                 .omap4  = {
1364                         .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1365                         .modulemode     = MODULEMODE_SWCTRL,
1366                 },
1367         },
1368 };
1369
1370 static struct omap_hwmod am33xx_timer4_hwmod = {
1371         .name           = "timer4",
1372         .class          = &am33xx_timer_hwmod_class,
1373         .clkdm_name     = "l4ls_clkdm",
1374         .main_clk       = "timer4_fck",
1375         .prcm           = {
1376                 .omap4  = {
1377                         .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1378                         .modulemode     = MODULEMODE_SWCTRL,
1379                 },
1380         },
1381 };
1382
1383 static struct omap_hwmod am33xx_timer5_hwmod = {
1384         .name           = "timer5",
1385         .class          = &am33xx_timer_hwmod_class,
1386         .clkdm_name     = "l4ls_clkdm",
1387         .main_clk       = "timer5_fck",
1388         .prcm           = {
1389                 .omap4  = {
1390                         .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1391                         .modulemode     = MODULEMODE_SWCTRL,
1392                 },
1393         },
1394 };
1395
1396 static struct omap_hwmod am33xx_timer6_hwmod = {
1397         .name           = "timer6",
1398         .class          = &am33xx_timer_hwmod_class,
1399         .clkdm_name     = "l4ls_clkdm",
1400         .main_clk       = "timer6_fck",
1401         .prcm           = {
1402                 .omap4  = {
1403                         .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1404                         .modulemode     = MODULEMODE_SWCTRL,
1405                 },
1406         },
1407 };
1408
1409 static struct omap_hwmod am33xx_timer7_hwmod = {
1410         .name           = "timer7",
1411         .class          = &am33xx_timer_hwmod_class,
1412         .clkdm_name     = "l4ls_clkdm",
1413         .main_clk       = "timer7_fck",
1414         .prcm           = {
1415                 .omap4  = {
1416                         .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1417                         .modulemode     = MODULEMODE_SWCTRL,
1418                 },
1419         },
1420 };
1421
1422 /* tpcc */
1423 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1424         .name           = "tpcc",
1425 };
1426
1427 static struct omap_hwmod am33xx_tpcc_hwmod = {
1428         .name           = "tpcc",
1429         .class          = &am33xx_tpcc_hwmod_class,
1430         .clkdm_name     = "l3_clkdm",
1431         .main_clk       = "l3_gclk",
1432         .prcm           = {
1433                 .omap4  = {
1434                         .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1435                         .modulemode     = MODULEMODE_SWCTRL,
1436                 },
1437         },
1438 };
1439
1440 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1441         .rev_offs       = 0x0,
1442         .sysc_offs      = 0x10,
1443         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1444                           SYSC_HAS_MIDLEMODE),
1445         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1446         .sysc_fields    = &omap_hwmod_sysc_type2,
1447 };
1448
1449 /* 'tptc' class */
1450 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1451         .name           = "tptc",
1452         .sysc           = &am33xx_tptc_sysc,
1453 };
1454
1455 /* tptc0 */
1456 static struct omap_hwmod am33xx_tptc0_hwmod = {
1457         .name           = "tptc0",
1458         .class          = &am33xx_tptc_hwmod_class,
1459         .clkdm_name     = "l3_clkdm",
1460         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1461         .main_clk       = "l3_gclk",
1462         .prcm           = {
1463                 .omap4  = {
1464                         .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1465                         .modulemode     = MODULEMODE_SWCTRL,
1466                 },
1467         },
1468 };
1469
1470 /* tptc1 */
1471 static struct omap_hwmod am33xx_tptc1_hwmod = {
1472         .name           = "tptc1",
1473         .class          = &am33xx_tptc_hwmod_class,
1474         .clkdm_name     = "l3_clkdm",
1475         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1476         .main_clk       = "l3_gclk",
1477         .prcm           = {
1478                 .omap4  = {
1479                         .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1480                         .modulemode     = MODULEMODE_SWCTRL,
1481                 },
1482         },
1483 };
1484
1485 /* tptc2 */
1486 static struct omap_hwmod am33xx_tptc2_hwmod = {
1487         .name           = "tptc2",
1488         .class          = &am33xx_tptc_hwmod_class,
1489         .clkdm_name     = "l3_clkdm",
1490         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1491         .main_clk       = "l3_gclk",
1492         .prcm           = {
1493                 .omap4  = {
1494                         .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1495                         .modulemode     = MODULEMODE_SWCTRL,
1496                 },
1497         },
1498 };
1499
1500 /* 'uart' class */
1501 static struct omap_hwmod_class_sysconfig uart_sysc = {
1502         .rev_offs       = 0x50,
1503         .sysc_offs      = 0x54,
1504         .syss_offs      = 0x58,
1505         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1506                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1507         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1508                           SIDLE_SMART_WKUP),
1509         .sysc_fields    = &omap_hwmod_sysc_type1,
1510 };
1511
1512 static struct omap_hwmod_class uart_class = {
1513         .name           = "uart",
1514         .sysc           = &uart_sysc,
1515 };
1516
1517 /* uart1 */
1518 static struct omap_hwmod am33xx_uart1_hwmod = {
1519         .name           = "uart1",
1520         .class          = &uart_class,
1521         .clkdm_name     = "l4_wkup_clkdm",
1522         .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1523         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1524         .prcm           = {
1525                 .omap4  = {
1526                         .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1527                         .modulemode     = MODULEMODE_SWCTRL,
1528                 },
1529         },
1530 };
1531
1532 static struct omap_hwmod am33xx_uart2_hwmod = {
1533         .name           = "uart2",
1534         .class          = &uart_class,
1535         .clkdm_name     = "l4ls_clkdm",
1536         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1537         .main_clk       = "dpll_per_m2_div4_ck",
1538         .prcm           = {
1539                 .omap4  = {
1540                         .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1541                         .modulemode     = MODULEMODE_SWCTRL,
1542                 },
1543         },
1544 };
1545
1546 /* uart3 */
1547 static struct omap_hwmod am33xx_uart3_hwmod = {
1548         .name           = "uart3",
1549         .class          = &uart_class,
1550         .clkdm_name     = "l4ls_clkdm",
1551         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1552         .main_clk       = "dpll_per_m2_div4_ck",
1553         .prcm           = {
1554                 .omap4  = {
1555                         .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
1556                         .modulemode     = MODULEMODE_SWCTRL,
1557                 },
1558         },
1559 };
1560
1561 static struct omap_hwmod am33xx_uart4_hwmod = {
1562         .name           = "uart4",
1563         .class          = &uart_class,
1564         .clkdm_name     = "l4ls_clkdm",
1565         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1566         .main_clk       = "dpll_per_m2_div4_ck",
1567         .prcm           = {
1568                 .omap4  = {
1569                         .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
1570                         .modulemode     = MODULEMODE_SWCTRL,
1571                 },
1572         },
1573 };
1574
1575 static struct omap_hwmod am33xx_uart5_hwmod = {
1576         .name           = "uart5",
1577         .class          = &uart_class,
1578         .clkdm_name     = "l4ls_clkdm",
1579         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1580         .main_clk       = "dpll_per_m2_div4_ck",
1581         .prcm           = {
1582                 .omap4  = {
1583                         .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
1584                         .modulemode     = MODULEMODE_SWCTRL,
1585                 },
1586         },
1587 };
1588
1589 static struct omap_hwmod am33xx_uart6_hwmod = {
1590         .name           = "uart6",
1591         .class          = &uart_class,
1592         .clkdm_name     = "l4ls_clkdm",
1593         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1594         .main_clk       = "dpll_per_m2_div4_ck",
1595         .prcm           = {
1596                 .omap4  = {
1597                         .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
1598                         .modulemode     = MODULEMODE_SWCTRL,
1599                 },
1600         },
1601 };
1602
1603 /* 'wd_timer' class */
1604 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1605         .rev_offs       = 0x0,
1606         .sysc_offs      = 0x10,
1607         .syss_offs      = 0x14,
1608         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1609                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1610         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1611                         SIDLE_SMART_WKUP),
1612         .sysc_fields    = &omap_hwmod_sysc_type1,
1613 };
1614
1615 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1616         .name           = "wd_timer",
1617         .sysc           = &wdt_sysc,
1618         .pre_shutdown   = &omap2_wd_timer_disable,
1619 };
1620
1621 /*
1622  * XXX: device.c file uses hardcoded name for watchdog timer
1623  * driver "wd_timer2, so we are also using same name as of now...
1624  */
1625 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
1626         .name           = "wd_timer2",
1627         .class          = &am33xx_wd_timer_hwmod_class,
1628         .clkdm_name     = "l4_wkup_clkdm",
1629         .flags          = HWMOD_SWSUP_SIDLE,
1630         .main_clk       = "wdt1_fck",
1631         .prcm           = {
1632                 .omap4  = {
1633                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
1634                         .modulemode     = MODULEMODE_SWCTRL,
1635                 },
1636         },
1637 };
1638
1639 /*
1640  * 'usb_otg' class
1641  * high-speed on-the-go universal serial bus (usb_otg) controller
1642  */
1643 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
1644         .rev_offs       = 0x0,
1645         .sysc_offs      = 0x10,
1646         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1647         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1648                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1649         .sysc_fields    = &omap_hwmod_sysc_type2,
1650 };
1651
1652 static struct omap_hwmod_class am33xx_usbotg_class = {
1653         .name           = "usbotg",
1654         .sysc           = &am33xx_usbhsotg_sysc,
1655 };
1656
1657 static struct omap_hwmod am33xx_usbss_hwmod = {
1658         .name           = "usb_otg_hs",
1659         .class          = &am33xx_usbotg_class,
1660         .clkdm_name     = "l3s_clkdm",
1661         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1662         .main_clk       = "usbotg_fck",
1663         .prcm           = {
1664                 .omap4  = {
1665                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
1666                         .modulemode     = MODULEMODE_SWCTRL,
1667                 },
1668         },
1669 };
1670
1671
1672 /*
1673  * Interfaces
1674  */
1675
1676 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
1677         {
1678                 .pa_start       = 0x4c000000,
1679                 .pa_end         = 0x4c000fff,
1680                 .flags          = ADDR_TYPE_RT
1681         },
1682         { }
1683 };
1684 /* l3 main -> emif */
1685 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
1686         .master         = &am33xx_l3_main_hwmod,
1687         .slave          = &am33xx_emif_hwmod,
1688         .clk            = "dpll_core_m4_ck",
1689         .addr           = am33xx_emif_addrs,
1690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1691 };
1692
1693 /* mpu -> l3 main */
1694 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
1695         .master         = &am33xx_mpu_hwmod,
1696         .slave          = &am33xx_l3_main_hwmod,
1697         .clk            = "dpll_mpu_m2_ck",
1698         .user           = OCP_USER_MPU,
1699 };
1700
1701 /* l3 main -> l4 hs */
1702 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
1703         .master         = &am33xx_l3_main_hwmod,
1704         .slave          = &am33xx_l4_hs_hwmod,
1705         .clk            = "l3s_gclk",
1706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1707 };
1708
1709 /* l3 main -> l3 s */
1710 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
1711         .master         = &am33xx_l3_main_hwmod,
1712         .slave          = &am33xx_l3_s_hwmod,
1713         .clk            = "l3s_gclk",
1714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1715 };
1716
1717 /* l3 s -> l4 per/ls */
1718 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
1719         .master         = &am33xx_l3_s_hwmod,
1720         .slave          = &am33xx_l4_ls_hwmod,
1721         .clk            = "l3s_gclk",
1722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1723 };
1724
1725 /* l3 s -> l4 wkup */
1726 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
1727         .master         = &am33xx_l3_s_hwmod,
1728         .slave          = &am33xx_l4_wkup_hwmod,
1729         .clk            = "l3s_gclk",
1730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1731 };
1732
1733 /* l3 main -> l3 instr */
1734 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
1735         .master         = &am33xx_l3_main_hwmod,
1736         .slave          = &am33xx_l3_instr_hwmod,
1737         .clk            = "l3s_gclk",
1738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1739 };
1740
1741 /* mpu -> prcm */
1742 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
1743         .master         = &am33xx_mpu_hwmod,
1744         .slave          = &am33xx_prcm_hwmod,
1745         .clk            = "dpll_mpu_m2_ck",
1746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1747 };
1748
1749 /* l3 s -> l3 main*/
1750 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
1751         .master         = &am33xx_l3_s_hwmod,
1752         .slave          = &am33xx_l3_main_hwmod,
1753         .clk            = "l3s_gclk",
1754         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1755 };
1756
1757 /* pru-icss -> l3 main */
1758 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
1759         .master         = &am33xx_pruss_hwmod,
1760         .slave          = &am33xx_l3_main_hwmod,
1761         .clk            = "l3_gclk",
1762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1763 };
1764
1765 /* wkup m3 -> l4 wkup */
1766 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
1767         .master         = &am33xx_wkup_m3_hwmod,
1768         .slave          = &am33xx_l4_wkup_hwmod,
1769         .clk            = "dpll_core_m4_div2_ck",
1770         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1771 };
1772
1773 /* gfx -> l3 main */
1774 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
1775         .master         = &am33xx_gfx_hwmod,
1776         .slave          = &am33xx_l3_main_hwmod,
1777         .clk            = "dpll_core_m4_ck",
1778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1779 };
1780
1781 /* l4 wkup -> wkup m3 */
1782 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
1783         .master         = &am33xx_l4_wkup_hwmod,
1784         .slave          = &am33xx_wkup_m3_hwmod,
1785         .clk            = "dpll_core_m4_div2_ck",
1786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1787 };
1788
1789 /* l4 hs -> pru-icss */
1790 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
1791         .master         = &am33xx_l4_hs_hwmod,
1792         .slave          = &am33xx_pruss_hwmod,
1793         .clk            = "dpll_core_m4_ck",
1794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1795 };
1796
1797 /* l3 main -> gfx */
1798 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
1799         .master         = &am33xx_l3_main_hwmod,
1800         .slave          = &am33xx_gfx_hwmod,
1801         .clk            = "dpll_core_m4_ck",
1802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1803 };
1804
1805 /* l3_main -> debugss */
1806 static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
1807         {
1808                 .pa_start       = 0x4b000000,
1809                 .pa_end         = 0x4b000000 + SZ_16M - 1,
1810                 .flags          = ADDR_TYPE_RT
1811         },
1812         { }
1813 };
1814
1815 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
1816         .master         = &am33xx_l3_main_hwmod,
1817         .slave          = &am33xx_debugss_hwmod,
1818         .clk            = "dpll_core_m4_ck",
1819         .addr           = am33xx_debugss_addrs,
1820         .user           = OCP_USER_MPU,
1821 };
1822
1823 /* l4 wkup -> smartreflex0 */
1824 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
1825         .master         = &am33xx_l4_wkup_hwmod,
1826         .slave          = &am33xx_smartreflex0_hwmod,
1827         .clk            = "dpll_core_m4_div2_ck",
1828         .user           = OCP_USER_MPU,
1829 };
1830
1831 /* l4 wkup -> smartreflex1 */
1832 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
1833         .master         = &am33xx_l4_wkup_hwmod,
1834         .slave          = &am33xx_smartreflex1_hwmod,
1835         .clk            = "dpll_core_m4_div2_ck",
1836         .user           = OCP_USER_MPU,
1837 };
1838
1839 /* l4 wkup -> control */
1840 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
1841         .master         = &am33xx_l4_wkup_hwmod,
1842         .slave          = &am33xx_control_hwmod,
1843         .clk            = "dpll_core_m4_div2_ck",
1844         .user           = OCP_USER_MPU,
1845 };
1846
1847 /* l4 wkup -> rtc */
1848 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
1849         .master         = &am33xx_l4_wkup_hwmod,
1850         .slave          = &am33xx_rtc_hwmod,
1851         .clk            = "clkdiv32k_ick",
1852         .user           = OCP_USER_MPU,
1853 };
1854
1855 /* l4 per/ls -> DCAN0 */
1856 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
1857         .master         = &am33xx_l4_ls_hwmod,
1858         .slave          = &am33xx_dcan0_hwmod,
1859         .clk            = "l4ls_gclk",
1860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1861 };
1862
1863 /* l4 per/ls -> DCAN1 */
1864 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
1865         .master         = &am33xx_l4_ls_hwmod,
1866         .slave          = &am33xx_dcan1_hwmod,
1867         .clk            = "l4ls_gclk",
1868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1869 };
1870
1871 /* l4 per/ls -> GPIO2 */
1872 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
1873         .master         = &am33xx_l4_ls_hwmod,
1874         .slave          = &am33xx_gpio1_hwmod,
1875         .clk            = "l4ls_gclk",
1876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1877 };
1878
1879 /* l4 per/ls -> gpio3 */
1880 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
1881         .master         = &am33xx_l4_ls_hwmod,
1882         .slave          = &am33xx_gpio2_hwmod,
1883         .clk            = "l4ls_gclk",
1884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1885 };
1886
1887 /* l4 per/ls -> gpio4 */
1888 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
1889         .master         = &am33xx_l4_ls_hwmod,
1890         .slave          = &am33xx_gpio3_hwmod,
1891         .clk            = "l4ls_gclk",
1892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1893 };
1894
1895 /* L4 WKUP -> I2C1 */
1896 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
1897         .master         = &am33xx_l4_wkup_hwmod,
1898         .slave          = &am33xx_i2c1_hwmod,
1899         .clk            = "dpll_core_m4_div2_ck",
1900         .user           = OCP_USER_MPU,
1901 };
1902
1903 /* L4 WKUP -> GPIO1 */
1904 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
1905         .master         = &am33xx_l4_wkup_hwmod,
1906         .slave          = &am33xx_gpio0_hwmod,
1907         .clk            = "dpll_core_m4_div2_ck",
1908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1909 };
1910
1911 /* L4 WKUP -> ADC_TSC */
1912 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
1913         {
1914                 .pa_start       = 0x44E0D000,
1915                 .pa_end         = 0x44E0D000 + SZ_8K - 1,
1916                 .flags          = ADDR_TYPE_RT
1917         },
1918         { }
1919 };
1920
1921 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
1922         .master         = &am33xx_l4_wkup_hwmod,
1923         .slave          = &am33xx_adc_tsc_hwmod,
1924         .clk            = "dpll_core_m4_div2_ck",
1925         .addr           = am33xx_adc_tsc_addrs,
1926         .user           = OCP_USER_MPU,
1927 };
1928
1929 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
1930         .master         = &am33xx_l4_hs_hwmod,
1931         .slave          = &am33xx_cpgmac0_hwmod,
1932         .clk            = "cpsw_125mhz_gclk",
1933         .user           = OCP_USER_MPU,
1934 };
1935
1936 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
1937         .master         = &am33xx_cpgmac0_hwmod,
1938         .slave          = &am33xx_mdio_hwmod,
1939         .user           = OCP_USER_MPU,
1940 };
1941
1942 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
1943         {
1944                 .pa_start       = 0x48080000,
1945                 .pa_end         = 0x48080000 + SZ_8K - 1,
1946                 .flags          = ADDR_TYPE_RT
1947         },
1948         { }
1949 };
1950
1951 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
1952         .master         = &am33xx_l4_ls_hwmod,
1953         .slave          = &am33xx_elm_hwmod,
1954         .clk            = "l4ls_gclk",
1955         .addr           = am33xx_elm_addr_space,
1956         .user           = OCP_USER_MPU,
1957 };
1958
1959 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
1960         {
1961                 .pa_start       = 0x48300000,
1962                 .pa_end         = 0x48300000 + SZ_16 - 1,
1963                 .flags          = ADDR_TYPE_RT
1964         },
1965         { }
1966 };
1967
1968 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
1969         .master         = &am33xx_l4_ls_hwmod,
1970         .slave          = &am33xx_epwmss0_hwmod,
1971         .clk            = "l4ls_gclk",
1972         .addr           = am33xx_epwmss0_addr_space,
1973         .user           = OCP_USER_MPU,
1974 };
1975
1976 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
1977         .master         = &am33xx_epwmss0_hwmod,
1978         .slave          = &am33xx_ecap0_hwmod,
1979         .clk            = "l4ls_gclk",
1980         .user           = OCP_USER_MPU,
1981 };
1982
1983 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
1984         .master         = &am33xx_epwmss0_hwmod,
1985         .slave          = &am33xx_eqep0_hwmod,
1986         .clk            = "l4ls_gclk",
1987         .user           = OCP_USER_MPU,
1988 };
1989
1990 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
1991         .master         = &am33xx_epwmss0_hwmod,
1992         .slave          = &am33xx_ehrpwm0_hwmod,
1993         .clk            = "l4ls_gclk",
1994         .user           = OCP_USER_MPU,
1995 };
1996
1997
1998 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
1999         {
2000                 .pa_start       = 0x48302000,
2001                 .pa_end         = 0x48302000 + SZ_16 - 1,
2002                 .flags          = ADDR_TYPE_RT
2003         },
2004         { }
2005 };
2006
2007 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2008         .master         = &am33xx_l4_ls_hwmod,
2009         .slave          = &am33xx_epwmss1_hwmod,
2010         .clk            = "l4ls_gclk",
2011         .addr           = am33xx_epwmss1_addr_space,
2012         .user           = OCP_USER_MPU,
2013 };
2014
2015 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2016         .master         = &am33xx_epwmss1_hwmod,
2017         .slave          = &am33xx_ecap1_hwmod,
2018         .clk            = "l4ls_gclk",
2019         .user           = OCP_USER_MPU,
2020 };
2021
2022 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2023         .master         = &am33xx_epwmss1_hwmod,
2024         .slave          = &am33xx_eqep1_hwmod,
2025         .clk            = "l4ls_gclk",
2026         .user           = OCP_USER_MPU,
2027 };
2028
2029 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2030         .master         = &am33xx_epwmss1_hwmod,
2031         .slave          = &am33xx_ehrpwm1_hwmod,
2032         .clk            = "l4ls_gclk",
2033         .user           = OCP_USER_MPU,
2034 };
2035
2036 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2037         {
2038                 .pa_start       = 0x48304000,
2039                 .pa_end         = 0x48304000 + SZ_16 - 1,
2040                 .flags          = ADDR_TYPE_RT
2041         },
2042         { }
2043 };
2044
2045 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2046         .master         = &am33xx_l4_ls_hwmod,
2047         .slave          = &am33xx_epwmss2_hwmod,
2048         .clk            = "l4ls_gclk",
2049         .addr           = am33xx_epwmss2_addr_space,
2050         .user           = OCP_USER_MPU,
2051 };
2052
2053 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2054         .master         = &am33xx_epwmss2_hwmod,
2055         .slave          = &am33xx_ecap2_hwmod,
2056         .clk            = "l4ls_gclk",
2057         .user           = OCP_USER_MPU,
2058 };
2059
2060 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2061         .master         = &am33xx_epwmss2_hwmod,
2062         .slave          = &am33xx_eqep2_hwmod,
2063         .clk            = "l4ls_gclk",
2064         .user           = OCP_USER_MPU,
2065 };
2066
2067 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2068         .master         = &am33xx_epwmss2_hwmod,
2069         .slave          = &am33xx_ehrpwm2_hwmod,
2070         .clk            = "l4ls_gclk",
2071         .user           = OCP_USER_MPU,
2072 };
2073
2074 /* l3s cfg -> gpmc */
2075 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2076         {
2077                 .pa_start       = 0x50000000,
2078                 .pa_end         = 0x50000000 + SZ_8K - 1,
2079                 .flags          = ADDR_TYPE_RT,
2080         },
2081         { }
2082 };
2083
2084 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2085         .master         = &am33xx_l3_s_hwmod,
2086         .slave          = &am33xx_gpmc_hwmod,
2087         .clk            = "l3s_gclk",
2088         .addr           = am33xx_gpmc_addr_space,
2089         .user           = OCP_USER_MPU,
2090 };
2091
2092 /* i2c2 */
2093 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2094         .master         = &am33xx_l4_ls_hwmod,
2095         .slave          = &am33xx_i2c2_hwmod,
2096         .clk            = "l4ls_gclk",
2097         .user           = OCP_USER_MPU,
2098 };
2099
2100 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2101         .master         = &am33xx_l4_ls_hwmod,
2102         .slave          = &am33xx_i2c3_hwmod,
2103         .clk            = "l4ls_gclk",
2104         .user           = OCP_USER_MPU,
2105 };
2106
2107 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2108         {
2109                 .pa_start       = 0x4830E000,
2110                 .pa_end         = 0x4830E000 + SZ_8K - 1,
2111                 .flags          = ADDR_TYPE_RT,
2112         },
2113         { }
2114 };
2115
2116 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2117         .master         = &am33xx_l3_main_hwmod,
2118         .slave          = &am33xx_lcdc_hwmod,
2119         .clk            = "dpll_core_m4_ck",
2120         .addr           = am33xx_lcdc_addr_space,
2121         .user           = OCP_USER_MPU,
2122 };
2123
2124 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2125         {
2126                 .pa_start       = 0x480C8000,
2127                 .pa_end         = 0x480C8000 + (SZ_4K - 1),
2128                 .flags          = ADDR_TYPE_RT
2129         },
2130         { }
2131 };
2132
2133 /* l4 ls -> mailbox */
2134 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2135         .master         = &am33xx_l4_ls_hwmod,
2136         .slave          = &am33xx_mailbox_hwmod,
2137         .clk            = "l4ls_gclk",
2138         .addr           = am33xx_mailbox_addrs,
2139         .user           = OCP_USER_MPU,
2140 };
2141
2142 /* l4 ls -> spinlock */
2143 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2144         .master         = &am33xx_l4_ls_hwmod,
2145         .slave          = &am33xx_spinlock_hwmod,
2146         .clk            = "l4ls_gclk",
2147         .user           = OCP_USER_MPU,
2148 };
2149
2150 /* l4 ls -> mcasp0 */
2151 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2152         {
2153                 .pa_start       = 0x48038000,
2154                 .pa_end         = 0x48038000 + SZ_8K - 1,
2155                 .flags          = ADDR_TYPE_RT
2156         },
2157         { }
2158 };
2159
2160 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2161         .master         = &am33xx_l4_ls_hwmod,
2162         .slave          = &am33xx_mcasp0_hwmod,
2163         .clk            = "l4ls_gclk",
2164         .addr           = am33xx_mcasp0_addr_space,
2165         .user           = OCP_USER_MPU,
2166 };
2167
2168 /* l4 ls -> mcasp1 */
2169 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2170         {
2171                 .pa_start       = 0x4803C000,
2172                 .pa_end         = 0x4803C000 + SZ_8K - 1,
2173                 .flags          = ADDR_TYPE_RT
2174         },
2175         { }
2176 };
2177
2178 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2179         .master         = &am33xx_l4_ls_hwmod,
2180         .slave          = &am33xx_mcasp1_hwmod,
2181         .clk            = "l4ls_gclk",
2182         .addr           = am33xx_mcasp1_addr_space,
2183         .user           = OCP_USER_MPU,
2184 };
2185
2186 /* l4 ls -> mmc0 */
2187 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2188         {
2189                 .pa_start       = 0x48060100,
2190                 .pa_end         = 0x48060100 + SZ_4K - 1,
2191                 .flags          = ADDR_TYPE_RT,
2192         },
2193         { }
2194 };
2195
2196 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
2197         .master         = &am33xx_l4_ls_hwmod,
2198         .slave          = &am33xx_mmc0_hwmod,
2199         .clk            = "l4ls_gclk",
2200         .addr           = am33xx_mmc0_addr_space,
2201         .user           = OCP_USER_MPU,
2202 };
2203
2204 /* l4 ls -> mmc1 */
2205 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
2206         {
2207                 .pa_start       = 0x481d8100,
2208                 .pa_end         = 0x481d8100 + SZ_4K - 1,
2209                 .flags          = ADDR_TYPE_RT,
2210         },
2211         { }
2212 };
2213
2214 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
2215         .master         = &am33xx_l4_ls_hwmod,
2216         .slave          = &am33xx_mmc1_hwmod,
2217         .clk            = "l4ls_gclk",
2218         .addr           = am33xx_mmc1_addr_space,
2219         .user           = OCP_USER_MPU,
2220 };
2221
2222 /* l3 s -> mmc2 */
2223 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
2224         {
2225                 .pa_start       = 0x47810100,
2226                 .pa_end         = 0x47810100 + SZ_64K - 1,
2227                 .flags          = ADDR_TYPE_RT,
2228         },
2229         { }
2230 };
2231
2232 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
2233         .master         = &am33xx_l3_s_hwmod,
2234         .slave          = &am33xx_mmc2_hwmod,
2235         .clk            = "l3s_gclk",
2236         .addr           = am33xx_mmc2_addr_space,
2237         .user           = OCP_USER_MPU,
2238 };
2239
2240 /* l4 ls -> mcspi0 */
2241 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
2242         .master         = &am33xx_l4_ls_hwmod,
2243         .slave          = &am33xx_spi0_hwmod,
2244         .clk            = "l4ls_gclk",
2245         .user           = OCP_USER_MPU,
2246 };
2247
2248 /* l4 ls -> mcspi1 */
2249 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
2250         .master         = &am33xx_l4_ls_hwmod,
2251         .slave          = &am33xx_spi1_hwmod,
2252         .clk            = "l4ls_gclk",
2253         .user           = OCP_USER_MPU,
2254 };
2255
2256 /* l4 wkup -> timer1 */
2257 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
2258         .master         = &am33xx_l4_wkup_hwmod,
2259         .slave          = &am33xx_timer1_hwmod,
2260         .clk            = "dpll_core_m4_div2_ck",
2261         .user           = OCP_USER_MPU,
2262 };
2263
2264 /* l4 per -> timer2 */
2265 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
2266         .master         = &am33xx_l4_ls_hwmod,
2267         .slave          = &am33xx_timer2_hwmod,
2268         .clk            = "l4ls_gclk",
2269         .user           = OCP_USER_MPU,
2270 };
2271
2272 /* l4 per -> timer3 */
2273 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
2274         .master         = &am33xx_l4_ls_hwmod,
2275         .slave          = &am33xx_timer3_hwmod,
2276         .clk            = "l4ls_gclk",
2277         .user           = OCP_USER_MPU,
2278 };
2279
2280 /* l4 per -> timer4 */
2281 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
2282         .master         = &am33xx_l4_ls_hwmod,
2283         .slave          = &am33xx_timer4_hwmod,
2284         .clk            = "l4ls_gclk",
2285         .user           = OCP_USER_MPU,
2286 };
2287
2288 /* l4 per -> timer5 */
2289 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
2290         .master         = &am33xx_l4_ls_hwmod,
2291         .slave          = &am33xx_timer5_hwmod,
2292         .clk            = "l4ls_gclk",
2293         .user           = OCP_USER_MPU,
2294 };
2295
2296 /* l4 per -> timer6 */
2297 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
2298         .master         = &am33xx_l4_ls_hwmod,
2299         .slave          = &am33xx_timer6_hwmod,
2300         .clk            = "l4ls_gclk",
2301         .user           = OCP_USER_MPU,
2302 };
2303
2304 /* l4 per -> timer7 */
2305 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
2306         .master         = &am33xx_l4_ls_hwmod,
2307         .slave          = &am33xx_timer7_hwmod,
2308         .clk            = "l4ls_gclk",
2309         .user           = OCP_USER_MPU,
2310 };
2311
2312 /* l3 main -> tpcc */
2313 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
2314         .master         = &am33xx_l3_main_hwmod,
2315         .slave          = &am33xx_tpcc_hwmod,
2316         .clk            = "l3_gclk",
2317         .user           = OCP_USER_MPU,
2318 };
2319
2320 /* l3 main -> tpcc0 */
2321 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2322         {
2323                 .pa_start       = 0x49800000,
2324                 .pa_end         = 0x49800000 + SZ_8K - 1,
2325                 .flags          = ADDR_TYPE_RT,
2326         },
2327         { }
2328 };
2329
2330 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2331         .master         = &am33xx_l3_main_hwmod,
2332         .slave          = &am33xx_tptc0_hwmod,
2333         .clk            = "l3_gclk",
2334         .addr           = am33xx_tptc0_addr_space,
2335         .user           = OCP_USER_MPU,
2336 };
2337
2338 /* l3 main -> tpcc1 */
2339 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2340         {
2341                 .pa_start       = 0x49900000,
2342                 .pa_end         = 0x49900000 + SZ_8K - 1,
2343                 .flags          = ADDR_TYPE_RT,
2344         },
2345         { }
2346 };
2347
2348 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2349         .master         = &am33xx_l3_main_hwmod,
2350         .slave          = &am33xx_tptc1_hwmod,
2351         .clk            = "l3_gclk",
2352         .addr           = am33xx_tptc1_addr_space,
2353         .user           = OCP_USER_MPU,
2354 };
2355
2356 /* l3 main -> tpcc2 */
2357 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2358         {
2359                 .pa_start       = 0x49a00000,
2360                 .pa_end         = 0x49a00000 + SZ_8K - 1,
2361                 .flags          = ADDR_TYPE_RT,
2362         },
2363         { }
2364 };
2365
2366 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2367         .master         = &am33xx_l3_main_hwmod,
2368         .slave          = &am33xx_tptc2_hwmod,
2369         .clk            = "l3_gclk",
2370         .addr           = am33xx_tptc2_addr_space,
2371         .user           = OCP_USER_MPU,
2372 };
2373
2374 /* l4 wkup -> uart1 */
2375 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2376         .master         = &am33xx_l4_wkup_hwmod,
2377         .slave          = &am33xx_uart1_hwmod,
2378         .clk            = "dpll_core_m4_div2_ck",
2379         .user           = OCP_USER_MPU,
2380 };
2381
2382 /* l4 ls -> uart2 */
2383 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2384         .master         = &am33xx_l4_ls_hwmod,
2385         .slave          = &am33xx_uart2_hwmod,
2386         .clk            = "l4ls_gclk",
2387         .user           = OCP_USER_MPU,
2388 };
2389
2390 /* l4 ls -> uart3 */
2391 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2392         .master         = &am33xx_l4_ls_hwmod,
2393         .slave          = &am33xx_uart3_hwmod,
2394         .clk            = "l4ls_gclk",
2395         .user           = OCP_USER_MPU,
2396 };
2397
2398 /* l4 ls -> uart4 */
2399 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2400         .master         = &am33xx_l4_ls_hwmod,
2401         .slave          = &am33xx_uart4_hwmod,
2402         .clk            = "l4ls_gclk",
2403         .user           = OCP_USER_MPU,
2404 };
2405
2406 /* l4 ls -> uart5 */
2407 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2408         .master         = &am33xx_l4_ls_hwmod,
2409         .slave          = &am33xx_uart5_hwmod,
2410         .clk            = "l4ls_gclk",
2411         .user           = OCP_USER_MPU,
2412 };
2413
2414 /* l4 ls -> uart6 */
2415 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2416         .master         = &am33xx_l4_ls_hwmod,
2417         .slave          = &am33xx_uart6_hwmod,
2418         .clk            = "l4ls_gclk",
2419         .user           = OCP_USER_MPU,
2420 };
2421
2422 /* l4 wkup -> wd_timer1 */
2423 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
2424         .master         = &am33xx_l4_wkup_hwmod,
2425         .slave          = &am33xx_wd_timer1_hwmod,
2426         .clk            = "dpll_core_m4_div2_ck",
2427         .user           = OCP_USER_MPU,
2428 };
2429
2430 /* usbss */
2431 /* l3 s -> USBSS interface */
2432 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
2433         .master         = &am33xx_l3_s_hwmod,
2434         .slave          = &am33xx_usbss_hwmod,
2435         .clk            = "l3s_gclk",
2436         .user           = OCP_USER_MPU,
2437         .flags          = OCPIF_SWSUP_IDLE,
2438 };
2439
2440 /* l3 main -> ocmc */
2441 static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
2442         .master         = &am33xx_l3_main_hwmod,
2443         .slave          = &am33xx_ocmcram_hwmod,
2444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2445 };
2446
2447 /* l3 main -> sha0 HIB2 */
2448 static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
2449         {
2450                 .pa_start       = 0x53100000,
2451                 .pa_end         = 0x53100000 + SZ_512 - 1,
2452                 .flags          = ADDR_TYPE_RT
2453         },
2454         { }
2455 };
2456
2457 static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
2458         .master         = &am33xx_l3_main_hwmod,
2459         .slave          = &am33xx_sha0_hwmod,
2460         .clk            = "sha0_fck",
2461         .addr           = am33xx_sha0_addrs,
2462         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2463 };
2464
2465 /* l3 main -> AES0 HIB2 */
2466 static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
2467         {
2468                 .pa_start       = 0x53500000,
2469                 .pa_end         = 0x53500000 + SZ_1M - 1,
2470                 .flags          = ADDR_TYPE_RT
2471         },
2472         { }
2473 };
2474
2475 static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
2476         .master         = &am33xx_l3_main_hwmod,
2477         .slave          = &am33xx_aes0_hwmod,
2478         .clk            = "aes0_fck",
2479         .addr           = am33xx_aes0_addrs,
2480         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2481 };
2482
2483 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
2484         &am33xx_l3_main__emif,
2485         &am33xx_mpu__l3_main,
2486         &am33xx_mpu__prcm,
2487         &am33xx_l3_s__l4_ls,
2488         &am33xx_l3_s__l4_wkup,
2489         &am33xx_l3_main__l4_hs,
2490         &am33xx_l3_main__l3_s,
2491         &am33xx_l3_main__l3_instr,
2492         &am33xx_l3_main__gfx,
2493         &am33xx_l3_s__l3_main,
2494         &am33xx_pruss__l3_main,
2495         &am33xx_wkup_m3__l4_wkup,
2496         &am33xx_gfx__l3_main,
2497         &am33xx_l3_main__debugss,
2498         &am33xx_l4_wkup__wkup_m3,
2499         &am33xx_l4_wkup__control,
2500         &am33xx_l4_wkup__smartreflex0,
2501         &am33xx_l4_wkup__smartreflex1,
2502         &am33xx_l4_wkup__uart1,
2503         &am33xx_l4_wkup__timer1,
2504         &am33xx_l4_wkup__rtc,
2505         &am33xx_l4_wkup__i2c1,
2506         &am33xx_l4_wkup__gpio0,
2507         &am33xx_l4_wkup__adc_tsc,
2508         &am33xx_l4_wkup__wd_timer1,
2509         &am33xx_l4_hs__pruss,
2510         &am33xx_l4_per__dcan0,
2511         &am33xx_l4_per__dcan1,
2512         &am33xx_l4_per__gpio1,
2513         &am33xx_l4_per__gpio2,
2514         &am33xx_l4_per__gpio3,
2515         &am33xx_l4_per__i2c2,
2516         &am33xx_l4_per__i2c3,
2517         &am33xx_l4_per__mailbox,
2518         &am33xx_l4_ls__mcasp0,
2519         &am33xx_l4_ls__mcasp1,
2520         &am33xx_l4_ls__mmc0,
2521         &am33xx_l4_ls__mmc1,
2522         &am33xx_l3_s__mmc2,
2523         &am33xx_l4_ls__timer2,
2524         &am33xx_l4_ls__timer3,
2525         &am33xx_l4_ls__timer4,
2526         &am33xx_l4_ls__timer5,
2527         &am33xx_l4_ls__timer6,
2528         &am33xx_l4_ls__timer7,
2529         &am33xx_l3_main__tpcc,
2530         &am33xx_l4_ls__uart2,
2531         &am33xx_l4_ls__uart3,
2532         &am33xx_l4_ls__uart4,
2533         &am33xx_l4_ls__uart5,
2534         &am33xx_l4_ls__uart6,
2535         &am33xx_l4_ls__spinlock,
2536         &am33xx_l4_ls__elm,
2537         &am33xx_l4_ls__epwmss0,
2538         &am33xx_epwmss0__ecap0,
2539         &am33xx_epwmss0__eqep0,
2540         &am33xx_epwmss0__ehrpwm0,
2541         &am33xx_l4_ls__epwmss1,
2542         &am33xx_epwmss1__ecap1,
2543         &am33xx_epwmss1__eqep1,
2544         &am33xx_epwmss1__ehrpwm1,
2545         &am33xx_l4_ls__epwmss2,
2546         &am33xx_epwmss2__ecap2,
2547         &am33xx_epwmss2__eqep2,
2548         &am33xx_epwmss2__ehrpwm2,
2549         &am33xx_l3_s__gpmc,
2550         &am33xx_l3_main__lcdc,
2551         &am33xx_l4_ls__mcspi0,
2552         &am33xx_l4_ls__mcspi1,
2553         &am33xx_l3_main__tptc0,
2554         &am33xx_l3_main__tptc1,
2555         &am33xx_l3_main__tptc2,
2556         &am33xx_l3_main__ocmc,
2557         &am33xx_l3_s__usbss,
2558         &am33xx_l4_hs__cpgmac0,
2559         &am33xx_cpgmac0__mdio,
2560         &am33xx_l3_main__sha0,
2561         &am33xx_l3_main__aes0,
2562         NULL,
2563 };
2564
2565 int __init am33xx_hwmod_init(void)
2566 {
2567         omap_hwmod_init();
2568         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
2569 }