2 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
4 * Copyright (C) 2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <plat/omap_hwmod.h>
13 #include <plat/serial.h>
15 #include <plat/common.h>
18 #include "omap_hwmod_common_data.h"
22 static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
26 .sysc_flags = (SYSC_HAS_SIDLEMODE |
27 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
28 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
29 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
30 .sysc_fields = &omap_hwmod_sysc_type1,
33 struct omap_hwmod_class omap2_uart_class = {
35 .sysc = &omap2_uart_sysc,
43 static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
47 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
48 SYSS_HAS_RESET_STATUS),
49 .sysc_fields = &omap_hwmod_sysc_type1,
52 struct omap_hwmod_class omap2_dss_hwmod_class = {
54 .sysc = &omap2_dss_sysc,
55 .reset = omap_dss_reset,
60 * remote frame buffer interface
63 static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
67 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
69 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
70 .sysc_fields = &omap_hwmod_sysc_type1,
73 struct omap_hwmod_class omap2_rfbi_hwmod_class = {
75 .sysc = &omap2_rfbi_sysc,
83 struct omap_hwmod_class omap2_venc_hwmod_class = {
88 /* Common DMA request line data */
89 struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
90 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
91 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
95 struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
96 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
97 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
101 struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
102 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
103 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
107 struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
108 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
109 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
113 struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
114 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
115 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
119 struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
120 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
121 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
122 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
123 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
124 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
125 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
126 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
127 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
131 struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
132 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
133 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
134 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
135 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
139 struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
140 { .name = "rx", .dma_req = 32 },
141 { .name = "tx", .dma_req = 31 },
145 struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
146 { .name = "rx", .dma_req = 34 },
147 { .name = "tx", .dma_req = 33 },
151 struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
152 { .name = "rx", .dma_req = 18 },
153 { .name = "tx", .dma_req = 17 },
157 /* Other IP block data */
161 * omap_hwmod class data
164 struct omap_hwmod_class l3_hwmod_class = {
168 struct omap_hwmod_class l4_hwmod_class = {
172 struct omap_hwmod_class mpu_hwmod_class = {
176 struct omap_hwmod_class iva_hwmod_class = {
180 /* Common MPU IRQ line data */
182 struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
183 { .irq = 37 + OMAP_INTC_START, },
187 struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
188 { .irq = 38 + OMAP_INTC_START, },
192 struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
193 { .irq = 39 + OMAP_INTC_START, },
197 struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
198 { .irq = 40 + OMAP_INTC_START, },
202 struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
203 { .irq = 41 + OMAP_INTC_START, },
207 struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
208 { .irq = 42 + OMAP_INTC_START, },
212 struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
213 { .irq = 43 + OMAP_INTC_START, },
217 struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
218 { .irq = 44 + OMAP_INTC_START, },
222 struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
223 { .irq = 45 + OMAP_INTC_START, },
227 struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
228 { .irq = 46 + OMAP_INTC_START, },
232 struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
233 { .irq = 47 + OMAP_INTC_START, },
237 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
238 { .irq = 72 + OMAP_INTC_START, },
242 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
243 { .irq = 73 + OMAP_INTC_START, },
247 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
248 { .irq = 74 + OMAP_INTC_START, },
252 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
253 { .irq = 25 + OMAP_INTC_START, },
257 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
258 { .irq = 56 + OMAP_INTC_START, },
262 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
263 { .irq = 57 + OMAP_INTC_START, },
267 struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
268 { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
272 struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
273 { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
277 struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
278 { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
282 struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
283 { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
287 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
288 { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
289 { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
290 { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
291 { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
295 struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
296 { .irq = 65 + OMAP_INTC_START, },
300 struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
301 { .irq = 66 + OMAP_INTC_START, },
305 struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
309 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
310 SYSS_HAS_RESET_STATUS),
311 .sysc_fields = &omap_hwmod_sysc_type1,
314 struct omap_hwmod_class omap2_hdq1w_class = {
316 .sysc = &omap2_hdq1w_sysc,
317 .reset = &omap_hdq1w_reset,
320 struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
321 { .irq = 58 + OMAP_INTC_START, },