Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <plat-omap/dma-omap.h>
  14
  15 #include "../plat-omap/common.h"
  16
  17 #include "omap_hwmod.h"
  18 #include "hdq1w.h"
  19
  20 #include "omap_hwmod_common_data.h"
  21 #include "dma.h"
  22
  23 /* UART */
  24
  25 static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
  26         .rev_offs       = 0x50,
  27         .sysc_offs      = 0x54,
  28         .syss_offs      = 0x58,
  29         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
  30                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  31                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  32         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  33         .sysc_fields    = &omap_hwmod_sysc_type1,
  34 };
  35
  36 struct omap_hwmod_class omap2_uart_class = {
  37         .name   = "uart",
  38         .sysc   = &omap2_uart_sysc,
  39 };
  40
  41 /*
  42  * 'dss' class
  43  * display sub-system
  44  */
  45
  46 static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
  47         .rev_offs       = 0x0000,
  48         .sysc_offs      = 0x0010,
  49         .syss_offs      = 0x0014,
  50         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  51                            SYSS_HAS_RESET_STATUS),
  52         .sysc_fields    = &omap_hwmod_sysc_type1,
  53 };
  54
  55 struct omap_hwmod_class omap2_dss_hwmod_class = {
  56         .name   = "dss",
  57         .sysc   = &omap2_dss_sysc,
  58         .reset  = omap_dss_reset,
  59 };
  60
  61 /*
  62  * 'rfbi' class
  63  * remote frame buffer interface
  64  */
  65
  66 static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
  67         .rev_offs       = 0x0000,
  68         .sysc_offs      = 0x0010,
  69         .syss_offs      = 0x0014,
  70         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  71                            SYSC_HAS_AUTOIDLE),
  72         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  73         .sysc_fields    = &omap_hwmod_sysc_type1,
  74 };
  75
  76 struct omap_hwmod_class omap2_rfbi_hwmod_class = {
  77         .name   = "rfbi",
  78         .sysc   = &omap2_rfbi_sysc,
  79 };
  80
  81 /*
  82  * 'venc' class
  83  * video encoder
  84  */
  85
  86 struct omap_hwmod_class omap2_venc_hwmod_class = {
  87         .name = "venc",
  88 };
  89
  90
  91 /* Common DMA request line data */
  92 struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
  93         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
  94         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
  95         { .dma_req = -1 }
  96 };
  97
  98 struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
  99         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 100         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 101         { .dma_req = -1 }
 102 };
 103
 104 struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
 105         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 106         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 107         { .dma_req = -1 }
 108 };
 109
 110 struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
 111         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
 112         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
 113         { .dma_req = -1 }
 114 };
 115
 116 struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
 117         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
 118         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
 119         { .dma_req = -1 }
 120 };
 121
 122 struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
 123         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
 124         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
 125         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
 126         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
 127         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
 128         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
 129         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
 130         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
 131         { .dma_req = -1 }
 132 };
 133
 134 struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
 135         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
 136         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
 137         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
 138         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
 139         { .dma_req = -1 }
 140 };
 141
 142 struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
 143         { .name = "rx", .dma_req = 32 },
 144         { .name = "tx", .dma_req = 31 },
 145         { .dma_req = -1 }
 146 };
 147
 148 struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
 149         { .name = "rx", .dma_req = 34 },
 150         { .name = "tx", .dma_req = 33 },
 151         { .dma_req = -1 }
 152 };
 153
 154 struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
 155         { .name = "rx", .dma_req = 18 },
 156         { .name = "tx", .dma_req = 17 },
 157         { .dma_req = -1 }
 158 };
 159
 160 /* Other IP block data */
 161
 162
 163 /*
 164  * omap_hwmod class data
 165  */
 166
 167 struct omap_hwmod_class l3_hwmod_class = {
 168         .name = "l3"
 169 };
 170
 171 struct omap_hwmod_class l4_hwmod_class = {
 172         .name = "l4"
 173 };
 174
 175 struct omap_hwmod_class mpu_hwmod_class = {
 176         .name = "mpu"
 177 };
 178
 179 struct omap_hwmod_class iva_hwmod_class = {
 180         .name = "iva"
 181 };
 182
 183 /* Common MPU IRQ line data */
 184
 185 struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
 186         { .irq = 37 + OMAP_INTC_START, },
 187         { .irq = -1 },
 188 };
 189
 190 struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
 191         { .irq = 38 + OMAP_INTC_START, },
 192         { .irq = -1 },
 193 };
 194
 195 struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
 196         { .irq = 39 + OMAP_INTC_START, },
 197         { .irq = -1 },
 198 };
 199
 200 struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
 201         { .irq = 40 + OMAP_INTC_START, },
 202         { .irq = -1 },
 203 };
 204
 205 struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
 206         { .irq = 41 + OMAP_INTC_START, },
 207         { .irq = -1 },
 208 };
 209
 210 struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
 211         { .irq = 42 + OMAP_INTC_START, },
 212         { .irq = -1 },
 213 };
 214
 215 struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
 216         { .irq = 43 + OMAP_INTC_START, },
 217         { .irq = -1 },
 218 };
 219
 220 struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
 221         { .irq = 44 + OMAP_INTC_START, },
 222         { .irq = -1 },
 223 };
 224
 225 struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
 226         { .irq = 45 + OMAP_INTC_START, },
 227         { .irq = -1 },
 228 };
 229
 230 struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
 231         { .irq = 46 + OMAP_INTC_START, },
 232         { .irq = -1 },
 233 };
 234
 235 struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
 236         { .irq = 47 + OMAP_INTC_START, },
 237         { .irq = -1 },
 238 };
 239
 240 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
 241         { .irq = 72 + OMAP_INTC_START, },
 242         { .irq = -1 },
 243 };
 244
 245 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
 246         { .irq = 73 + OMAP_INTC_START, },
 247         { .irq = -1 },
 248 };
 249
 250 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
 251         { .irq = 74 + OMAP_INTC_START, },
 252         { .irq = -1 },
 253 };
 254
 255 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
 256         { .irq = 25 + OMAP_INTC_START, },
 257         { .irq = -1 },
 258 };
 259
 260 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
 261         { .irq = 56 + OMAP_INTC_START, },
 262         { .irq = -1 },
 263 };
 264
 265 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
 266         { .irq = 57 + OMAP_INTC_START, },
 267         { .irq = -1 },
 268 };
 269
 270 struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
 271         { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
 272         { .irq = -1 },
 273 };
 274
 275 struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
 276         { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
 277         { .irq = -1 },
 278 };
 279
 280 struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
 281         { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
 282         { .irq = -1 },
 283 };
 284
 285 struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
 286         { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
 287         { .irq = -1 },
 288 };
 289
 290 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
 291         { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
 292         { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
 293         { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
 294         { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
 295         { .irq = -1 },
 296 };
 297
 298 struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
 299         { .irq = 65 + OMAP_INTC_START, },
 300         { .irq = -1 },
 301 };
 302
 303 struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
 304         { .irq = 66 + OMAP_INTC_START, },
 305         { .irq = -1 },
 306 };
 307
 308 struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
 309         .rev_offs       = 0x0,
 310         .sysc_offs      = 0x14,
 311         .syss_offs      = 0x18,
 312         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 313                            SYSS_HAS_RESET_STATUS),
 314         .sysc_fields    = &omap_hwmod_sysc_type1,
 315 };
 316
 317 struct omap_hwmod_class omap2_hdq1w_class = {
 318         .name   = "hdq1w",
 319         .sysc   = &omap2_hdq1w_sysc,
 320         .reset  = &omap_hdq1w_reset,
 321 };
 322
 323 struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
 324         { .irq = 58 + OMAP_INTC_START, },
 325         { .irq = -1 },
 326 };
 327