Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcbsp.h>
  22 #include <plat/mcspi.h>
  23 #include <plat/dmtimer.h>
  24 #include <plat/mmc.h>
  25 #include <plat/l3_2xxx.h>
  26
  27 #include "omap_hwmod_common_data.h"
  28
  29 #include "prm-regbits-24xx.h"
  30 #include "cm-regbits-24xx.h"
  31 #include "wd_timer.h"
  32
  33 /*
  34  * OMAP2430 hardware module integration data
  35  *
  36  * ALl of the data in this section should be autogeneratable from the
  37  * TI hardware database or other technical documentation.  Data that
  38  * is driver-specific or driver-kernel integration-specific belongs
  39  * elsewhere.
  40  */
  41
  42 static struct omap_hwmod omap2430_mpu_hwmod;
  43 static struct omap_hwmod omap2430_iva_hwmod;
  44 static struct omap_hwmod omap2430_l3_main_hwmod;
  45 static struct omap_hwmod omap2430_l4_core_hwmod;
  46 static struct omap_hwmod omap2430_dss_core_hwmod;
  47 static struct omap_hwmod omap2430_dss_dispc_hwmod;
  48 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
  49 static struct omap_hwmod omap2430_dss_venc_hwmod;
  50 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  51 static struct omap_hwmod omap2430_gpio1_hwmod;
  52 static struct omap_hwmod omap2430_gpio2_hwmod;
  53 static struct omap_hwmod omap2430_gpio3_hwmod;
  54 static struct omap_hwmod omap2430_gpio4_hwmod;
  55 static struct omap_hwmod omap2430_gpio5_hwmod;
  56 static struct omap_hwmod omap2430_dma_system_hwmod;
  57 static struct omap_hwmod omap2430_mcbsp1_hwmod;
  58 static struct omap_hwmod omap2430_mcbsp2_hwmod;
  59 static struct omap_hwmod omap2430_mcbsp3_hwmod;
  60 static struct omap_hwmod omap2430_mcbsp4_hwmod;
  61 static struct omap_hwmod omap2430_mcbsp5_hwmod;
  62 static struct omap_hwmod omap2430_mcspi1_hwmod;
  63 static struct omap_hwmod omap2430_mcspi2_hwmod;
  64 static struct omap_hwmod omap2430_mcspi3_hwmod;
  65 static struct omap_hwmod omap2430_mmc1_hwmod;
  66 static struct omap_hwmod omap2430_mmc2_hwmod;
  67
  68 /* L3 -> L4_CORE interface */
  69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  70         .master = &omap2430_l3_main_hwmod,
  71         .slave  = &omap2430_l4_core_hwmod,
  72         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  73 };
  74
  75 /* MPU -> L3 interface */
  76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  77         .master = &omap2430_mpu_hwmod,
  78         .slave  = &omap2430_l3_main_hwmod,
  79         .user   = OCP_USER_MPU,
  80 };
  81
  82 /* Slave interfaces on the L3 interconnect */
  83 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  84         &omap2430_mpu__l3_main,
  85 };
  86
  87 /* DSS -> l3 */
  88 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
  89         .master         = &omap2430_dss_core_hwmod,
  90         .slave          = &omap2430_l3_main_hwmod,
  91         .fw = {
  92                 .omap2 = {
  93                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  94                         .flags  = OMAP_FIREWALL_L3,
  95                 }
  96         },
  97         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  98 };
  99
 100 /* Master interfaces on the L3 interconnect */
 101 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
 102         &omap2430_l3_main__l4_core,
 103 };
 104
 105 /* L3 */
 106 static struct omap_hwmod omap2430_l3_main_hwmod = {
 107         .name           = "l3_main",
 108         .class          = &l3_hwmod_class,
 109         .masters        = omap2430_l3_main_masters,
 110         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
 111         .slaves         = omap2430_l3_main_slaves,
 112         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
 113         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 114         .flags          = HWMOD_NO_IDLEST,
 115 };
 116
 117 static struct omap_hwmod omap2430_l4_wkup_hwmod;
 118 static struct omap_hwmod omap2430_uart1_hwmod;
 119 static struct omap_hwmod omap2430_uart2_hwmod;
 120 static struct omap_hwmod omap2430_uart3_hwmod;
 121 static struct omap_hwmod omap2430_i2c1_hwmod;
 122 static struct omap_hwmod omap2430_i2c2_hwmod;
 123
 124 static struct omap_hwmod omap2430_usbhsotg_hwmod;
 125
 126 /* l3_core -> usbhsotg  interface */
 127 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 128         .master         = &omap2430_usbhsotg_hwmod,
 129         .slave          = &omap2430_l3_main_hwmod,
 130         .clk            = "core_l3_ck",
 131         .user           = OCP_USER_MPU,
 132 };
 133
 134 /* L4 CORE -> I2C1 interface */
 135 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 136         .master         = &omap2430_l4_core_hwmod,
 137         .slave          = &omap2430_i2c1_hwmod,
 138         .clk            = "i2c1_ick",
 139         .addr           = omap2_i2c1_addr_space,
 140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 141 };
 142
 143 /* L4 CORE -> I2C2 interface */
 144 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 145         .master         = &omap2430_l4_core_hwmod,
 146         .slave          = &omap2430_i2c2_hwmod,
 147         .clk            = "i2c2_ick",
 148         .addr           = omap2_i2c2_addr_space,
 149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 150 };
 151
 152 /* L4_CORE -> L4_WKUP interface */
 153 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 154         .master = &omap2430_l4_core_hwmod,
 155         .slave  = &omap2430_l4_wkup_hwmod,
 156         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 157 };
 158
 159 /* L4 CORE -> UART1 interface */
 160 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 161         .master         = &omap2430_l4_core_hwmod,
 162         .slave          = &omap2430_uart1_hwmod,
 163         .clk            = "uart1_ick",
 164         .addr           = omap2xxx_uart1_addr_space,
 165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 166 };
 167
 168 /* L4 CORE -> UART2 interface */
 169 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 170         .master         = &omap2430_l4_core_hwmod,
 171         .slave          = &omap2430_uart2_hwmod,
 172         .clk            = "uart2_ick",
 173         .addr           = omap2xxx_uart2_addr_space,
 174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 175 };
 176
 177 /* L4 PER -> UART3 interface */
 178 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 179         .master         = &omap2430_l4_core_hwmod,
 180         .slave          = &omap2430_uart3_hwmod,
 181         .clk            = "uart3_ick",
 182         .addr           = omap2xxx_uart3_addr_space,
 183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 184 };
 185
 186 /*
 187 * usbhsotg interface data
 188 */
 189 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 190         {
 191                 .pa_start       = OMAP243X_HS_BASE,
 192                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 193                 .flags          = ADDR_TYPE_RT
 194         },
 195 };
 196
 197 /*  l4_core ->usbhsotg  interface */
 198 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 199         .master         = &omap2430_l4_core_hwmod,
 200         .slave          = &omap2430_usbhsotg_hwmod,
 201         .clk            = "usb_l4_ick",
 202         .addr           = omap2430_usbhsotg_addrs,
 203         .user           = OCP_USER_MPU,
 204 };
 205
 206 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
 207         &omap2430_usbhsotg__l3,
 208 };
 209
 210 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 211         &omap2430_l4_core__usbhsotg,
 212 };
 213
 214 /* L4 CORE -> MMC1 interface */
 215 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
 216         .master         = &omap2430_l4_core_hwmod,
 217         .slave          = &omap2430_mmc1_hwmod,
 218         .clk            = "mmchs1_ick",
 219         .addr           = omap2430_mmc1_addr_space,
 220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 221 };
 222
 223 /* L4 CORE -> MMC2 interface */
 224 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 225         .master         = &omap2430_l4_core_hwmod,
 226         .slave          = &omap2430_mmc2_hwmod,
 227         .clk            = "mmchs2_ick",
 228         .addr           = omap2430_mmc2_addr_space,
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230 };
 231
 232 /* Slave interfaces on the L4_CORE interconnect */
 233 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 234         &omap2430_l3_main__l4_core,
 235 };
 236
 237 /* Master interfaces on the L4_CORE interconnect */
 238 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 239         &omap2430_l4_core__l4_wkup,
 240         &omap2430_l4_core__mmc1,
 241         &omap2430_l4_core__mmc2,
 242 };
 243
 244 /* L4 CORE */
 245 static struct omap_hwmod omap2430_l4_core_hwmod = {
 246         .name           = "l4_core",
 247         .class          = &l4_hwmod_class,
 248         .masters        = omap2430_l4_core_masters,
 249         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 250         .slaves         = omap2430_l4_core_slaves,
 251         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 252         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 253         .flags          = HWMOD_NO_IDLEST,
 254 };
 255
 256 /* Slave interfaces on the L4_WKUP interconnect */
 257 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 258         &omap2430_l4_core__l4_wkup,
 259         &omap2_l4_core__uart1,
 260         &omap2_l4_core__uart2,
 261         &omap2_l4_core__uart3,
 262 };
 263
 264 /* Master interfaces on the L4_WKUP interconnect */
 265 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 266 };
 267
 268 /* l4 core -> mcspi1 interface */
 269 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 270         .master         = &omap2430_l4_core_hwmod,
 271         .slave          = &omap2430_mcspi1_hwmod,
 272         .clk            = "mcspi1_ick",
 273         .addr           = omap2_mcspi1_addr_space,
 274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 275 };
 276
 277 /* l4 core -> mcspi2 interface */
 278 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 279         .master         = &omap2430_l4_core_hwmod,
 280         .slave          = &omap2430_mcspi2_hwmod,
 281         .clk            = "mcspi2_ick",
 282         .addr           = omap2_mcspi2_addr_space,
 283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 284 };
 285
 286 /* l4 core -> mcspi3 interface */
 287 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 288         .master         = &omap2430_l4_core_hwmod,
 289         .slave          = &omap2430_mcspi3_hwmod,
 290         .clk            = "mcspi3_ick",
 291         .addr           = omap2430_mcspi3_addr_space,
 292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 293 };
 294
 295 /* L4 WKUP */
 296 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 297         .name           = "l4_wkup",
 298         .class          = &l4_hwmod_class,
 299         .masters        = omap2430_l4_wkup_masters,
 300         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 301         .slaves         = omap2430_l4_wkup_slaves,
 302         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 303         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 304         .flags          = HWMOD_NO_IDLEST,
 305 };
 306
 307 /* Master interfaces on the MPU device */
 308 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 309         &omap2430_mpu__l3_main,
 310 };
 311
 312 /* MPU */
 313 static struct omap_hwmod omap2430_mpu_hwmod = {
 314         .name           = "mpu",
 315         .class          = &mpu_hwmod_class,
 316         .main_clk       = "mpu_ck",
 317         .masters        = omap2430_mpu_masters,
 318         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 319         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 320 };
 321
 322 /*
 323  * IVA2_1 interface data
 324  */
 325
 326 /* IVA2 <- L3 interface */
 327 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 328         .master         = &omap2430_l3_main_hwmod,
 329         .slave          = &omap2430_iva_hwmod,
 330         .clk            = "dsp_fck",
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 335         &omap2430_l3__iva,
 336 };
 337
 338 /*
 339  * IVA2 (IVA2)
 340  */
 341
 342 static struct omap_hwmod omap2430_iva_hwmod = {
 343         .name           = "iva",
 344         .class          = &iva_hwmod_class,
 345         .masters        = omap2430_iva_masters,
 346         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 347         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 348 };
 349
 350 /* Timer Common */
 351 static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
 352         .rev_offs       = 0x0000,
 353         .sysc_offs      = 0x0010,
 354         .syss_offs      = 0x0014,
 355         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 356                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 357                            SYSC_HAS_AUTOIDLE),
 358         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 359         .sysc_fields    = &omap_hwmod_sysc_type1,
 360 };
 361
 362 static struct omap_hwmod_class omap2430_timer_hwmod_class = {
 363         .name = "timer",
 364         .sysc = &omap2430_timer_sysc,
 365         .rev = OMAP_TIMER_IP_VERSION_1,
 366 };
 367
 368 /* timer1 */
 369 static struct omap_hwmod omap2430_timer1_hwmod;
 370 static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
 371         { .irq = 37, },
 372 };
 373
 374 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 375         {
 376                 .pa_start       = 0x49018000,
 377                 .pa_end         = 0x49018000 + SZ_1K - 1,
 378                 .flags          = ADDR_TYPE_RT
 379         },
 380         { }
 381 };
 382
 383 /* l4_wkup -> timer1 */
 384 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 385         .master         = &omap2430_l4_wkup_hwmod,
 386         .slave          = &omap2430_timer1_hwmod,
 387         .clk            = "gpt1_ick",
 388         .addr           = omap2430_timer1_addrs,
 389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 390 };
 391
 392 /* timer1 slave port */
 393 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 394         &omap2430_l4_wkup__timer1,
 395 };
 396
 397 /* timer1 hwmod */
 398 static struct omap_hwmod omap2430_timer1_hwmod = {
 399         .name           = "timer1",
 400         .mpu_irqs       = omap2430_timer1_mpu_irqs,
 401         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
 402         .main_clk       = "gpt1_fck",
 403         .prcm           = {
 404                 .omap2 = {
 405                         .prcm_reg_id = 1,
 406                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 407                         .module_offs = WKUP_MOD,
 408                         .idlest_reg_id = 1,
 409                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 410                 },
 411         },
 412         .slaves         = omap2430_timer1_slaves,
 413         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
 414         .class          = &omap2430_timer_hwmod_class,
 415         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 416 };
 417
 418 /* timer2 */
 419 static struct omap_hwmod omap2430_timer2_hwmod;
 420 static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
 421         { .irq = 38, },
 422 };
 423
 424 /* l4_core -> timer2 */
 425 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 426         .master         = &omap2430_l4_core_hwmod,
 427         .slave          = &omap2430_timer2_hwmod,
 428         .clk            = "gpt2_ick",
 429         .addr           = omap2xxx_timer2_addrs,
 430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 431 };
 432
 433 /* timer2 slave port */
 434 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 435         &omap2430_l4_core__timer2,
 436 };
 437
 438 /* timer2 hwmod */
 439 static struct omap_hwmod omap2430_timer2_hwmod = {
 440         .name           = "timer2",
 441         .mpu_irqs       = omap2430_timer2_mpu_irqs,
 442         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
 443         .main_clk       = "gpt2_fck",
 444         .prcm           = {
 445                 .omap2 = {
 446                         .prcm_reg_id = 1,
 447                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 448                         .module_offs = CORE_MOD,
 449                         .idlest_reg_id = 1,
 450                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 451                 },
 452         },
 453         .slaves         = omap2430_timer2_slaves,
 454         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
 455         .class          = &omap2430_timer_hwmod_class,
 456         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 457 };
 458
 459 /* timer3 */
 460 static struct omap_hwmod omap2430_timer3_hwmod;
 461 static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
 462         { .irq = 39, },
 463 };
 464
 465 /* l4_core -> timer3 */
 466 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 467         .master         = &omap2430_l4_core_hwmod,
 468         .slave          = &omap2430_timer3_hwmod,
 469         .clk            = "gpt3_ick",
 470         .addr           = omap2xxx_timer3_addrs,
 471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 472 };
 473
 474 /* timer3 slave port */
 475 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 476         &omap2430_l4_core__timer3,
 477 };
 478
 479 /* timer3 hwmod */
 480 static struct omap_hwmod omap2430_timer3_hwmod = {
 481         .name           = "timer3",
 482         .mpu_irqs       = omap2430_timer3_mpu_irqs,
 483         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
 484         .main_clk       = "gpt3_fck",
 485         .prcm           = {
 486                 .omap2 = {
 487                         .prcm_reg_id = 1,
 488                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 489                         .module_offs = CORE_MOD,
 490                         .idlest_reg_id = 1,
 491                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 492                 },
 493         },
 494         .slaves         = omap2430_timer3_slaves,
 495         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
 496         .class          = &omap2430_timer_hwmod_class,
 497         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 498 };
 499
 500 /* timer4 */
 501 static struct omap_hwmod omap2430_timer4_hwmod;
 502 static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
 503         { .irq = 40, },
 504 };
 505
 506 /* l4_core -> timer4 */
 507 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 508         .master         = &omap2430_l4_core_hwmod,
 509         .slave          = &omap2430_timer4_hwmod,
 510         .clk            = "gpt4_ick",
 511         .addr           = omap2xxx_timer4_addrs,
 512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 513 };
 514
 515 /* timer4 slave port */
 516 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 517         &omap2430_l4_core__timer4,
 518 };
 519
 520 /* timer4 hwmod */
 521 static struct omap_hwmod omap2430_timer4_hwmod = {
 522         .name           = "timer4",
 523         .mpu_irqs       = omap2430_timer4_mpu_irqs,
 524         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
 525         .main_clk       = "gpt4_fck",
 526         .prcm           = {
 527                 .omap2 = {
 528                         .prcm_reg_id = 1,
 529                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 530                         .module_offs = CORE_MOD,
 531                         .idlest_reg_id = 1,
 532                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 533                 },
 534         },
 535         .slaves         = omap2430_timer4_slaves,
 536         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
 537         .class          = &omap2430_timer_hwmod_class,
 538         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 539 };
 540
 541 /* timer5 */
 542 static struct omap_hwmod omap2430_timer5_hwmod;
 543 static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
 544         { .irq = 41, },
 545 };
 546
 547 /* l4_core -> timer5 */
 548 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 549         .master         = &omap2430_l4_core_hwmod,
 550         .slave          = &omap2430_timer5_hwmod,
 551         .clk            = "gpt5_ick",
 552         .addr           = omap2xxx_timer5_addrs,
 553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 554 };
 555
 556 /* timer5 slave port */
 557 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 558         &omap2430_l4_core__timer5,
 559 };
 560
 561 /* timer5 hwmod */
 562 static struct omap_hwmod omap2430_timer5_hwmod = {
 563         .name           = "timer5",
 564         .mpu_irqs       = omap2430_timer5_mpu_irqs,
 565         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
 566         .main_clk       = "gpt5_fck",
 567         .prcm           = {
 568                 .omap2 = {
 569                         .prcm_reg_id = 1,
 570                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 571                         .module_offs = CORE_MOD,
 572                         .idlest_reg_id = 1,
 573                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 574                 },
 575         },
 576         .slaves         = omap2430_timer5_slaves,
 577         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
 578         .class          = &omap2430_timer_hwmod_class,
 579         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 580 };
 581
 582 /* timer6 */
 583 static struct omap_hwmod omap2430_timer6_hwmod;
 584 static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
 585         { .irq = 42, },
 586 };
 587
 588 /* l4_core -> timer6 */
 589 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 590         .master         = &omap2430_l4_core_hwmod,
 591         .slave          = &omap2430_timer6_hwmod,
 592         .clk            = "gpt6_ick",
 593         .addr           = omap2xxx_timer6_addrs,
 594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 595 };
 596
 597 /* timer6 slave port */
 598 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 599         &omap2430_l4_core__timer6,
 600 };
 601
 602 /* timer6 hwmod */
 603 static struct omap_hwmod omap2430_timer6_hwmod = {
 604         .name           = "timer6",
 605         .mpu_irqs       = omap2430_timer6_mpu_irqs,
 606         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
 607         .main_clk       = "gpt6_fck",
 608         .prcm           = {
 609                 .omap2 = {
 610                         .prcm_reg_id = 1,
 611                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 612                         .module_offs = CORE_MOD,
 613                         .idlest_reg_id = 1,
 614                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 615                 },
 616         },
 617         .slaves         = omap2430_timer6_slaves,
 618         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
 619         .class          = &omap2430_timer_hwmod_class,
 620         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 621 };
 622
 623 /* timer7 */
 624 static struct omap_hwmod omap2430_timer7_hwmod;
 625 static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
 626         { .irq = 43, },
 627 };
 628
 629 /* l4_core -> timer7 */
 630 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 631         .master         = &omap2430_l4_core_hwmod,
 632         .slave          = &omap2430_timer7_hwmod,
 633         .clk            = "gpt7_ick",
 634         .addr           = omap2xxx_timer7_addrs,
 635         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 636 };
 637
 638 /* timer7 slave port */
 639 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 640         &omap2430_l4_core__timer7,
 641 };
 642
 643 /* timer7 hwmod */
 644 static struct omap_hwmod omap2430_timer7_hwmod = {
 645         .name           = "timer7",
 646         .mpu_irqs       = omap2430_timer7_mpu_irqs,
 647         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
 648         .main_clk       = "gpt7_fck",
 649         .prcm           = {
 650                 .omap2 = {
 651                         .prcm_reg_id = 1,
 652                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 653                         .module_offs = CORE_MOD,
 654                         .idlest_reg_id = 1,
 655                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 656                 },
 657         },
 658         .slaves         = omap2430_timer7_slaves,
 659         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
 660         .class          = &omap2430_timer_hwmod_class,
 661         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 662 };
 663
 664 /* timer8 */
 665 static struct omap_hwmod omap2430_timer8_hwmod;
 666 static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
 667         { .irq = 44, },
 668 };
 669
 670 /* l4_core -> timer8 */
 671 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 672         .master         = &omap2430_l4_core_hwmod,
 673         .slave          = &omap2430_timer8_hwmod,
 674         .clk            = "gpt8_ick",
 675         .addr           = omap2xxx_timer8_addrs,
 676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 677 };
 678
 679 /* timer8 slave port */
 680 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 681         &omap2430_l4_core__timer8,
 682 };
 683
 684 /* timer8 hwmod */
 685 static struct omap_hwmod omap2430_timer8_hwmod = {
 686         .name           = "timer8",
 687         .mpu_irqs       = omap2430_timer8_mpu_irqs,
 688         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
 689         .main_clk       = "gpt8_fck",
 690         .prcm           = {
 691                 .omap2 = {
 692                         .prcm_reg_id = 1,
 693                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 694                         .module_offs = CORE_MOD,
 695                         .idlest_reg_id = 1,
 696                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 697                 },
 698         },
 699         .slaves         = omap2430_timer8_slaves,
 700         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
 701         .class          = &omap2430_timer_hwmod_class,
 702         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 703 };
 704
 705 /* timer9 */
 706 static struct omap_hwmod omap2430_timer9_hwmod;
 707 static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
 708         { .irq = 45, },
 709 };
 710
 711 /* l4_core -> timer9 */
 712 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 713         .master         = &omap2430_l4_core_hwmod,
 714         .slave          = &omap2430_timer9_hwmod,
 715         .clk            = "gpt9_ick",
 716         .addr           = omap2xxx_timer9_addrs,
 717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 718 };
 719
 720 /* timer9 slave port */
 721 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 722         &omap2430_l4_core__timer9,
 723 };
 724
 725 /* timer9 hwmod */
 726 static struct omap_hwmod omap2430_timer9_hwmod = {
 727         .name           = "timer9",
 728         .mpu_irqs       = omap2430_timer9_mpu_irqs,
 729         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
 730         .main_clk       = "gpt9_fck",
 731         .prcm           = {
 732                 .omap2 = {
 733                         .prcm_reg_id = 1,
 734                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 735                         .module_offs = CORE_MOD,
 736                         .idlest_reg_id = 1,
 737                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 738                 },
 739         },
 740         .slaves         = omap2430_timer9_slaves,
 741         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
 742         .class          = &omap2430_timer_hwmod_class,
 743         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 744 };
 745
 746 /* timer10 */
 747 static struct omap_hwmod omap2430_timer10_hwmod;
 748 static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
 749         { .irq = 46, },
 750 };
 751
 752 /* l4_core -> timer10 */
 753 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 754         .master         = &omap2430_l4_core_hwmod,
 755         .slave          = &omap2430_timer10_hwmod,
 756         .clk            = "gpt10_ick",
 757         .addr           = omap2_timer10_addrs,
 758         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 759 };
 760
 761 /* timer10 slave port */
 762 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 763         &omap2430_l4_core__timer10,
 764 };
 765
 766 /* timer10 hwmod */
 767 static struct omap_hwmod omap2430_timer10_hwmod = {
 768         .name           = "timer10",
 769         .mpu_irqs       = omap2430_timer10_mpu_irqs,
 770         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
 771         .main_clk       = "gpt10_fck",
 772         .prcm           = {
 773                 .omap2 = {
 774                         .prcm_reg_id = 1,
 775                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 776                         .module_offs = CORE_MOD,
 777                         .idlest_reg_id = 1,
 778                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 779                 },
 780         },
 781         .slaves         = omap2430_timer10_slaves,
 782         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
 783         .class          = &omap2430_timer_hwmod_class,
 784         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 785 };
 786
 787 /* timer11 */
 788 static struct omap_hwmod omap2430_timer11_hwmod;
 789 static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
 790         { .irq = 47, },
 791 };
 792
 793 /* l4_core -> timer11 */
 794 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 795         .master         = &omap2430_l4_core_hwmod,
 796         .slave          = &omap2430_timer11_hwmod,
 797         .clk            = "gpt11_ick",
 798         .addr           = omap2_timer11_addrs,
 799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 800 };
 801
 802 /* timer11 slave port */
 803 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 804         &omap2430_l4_core__timer11,
 805 };
 806
 807 /* timer11 hwmod */
 808 static struct omap_hwmod omap2430_timer11_hwmod = {
 809         .name           = "timer11",
 810         .mpu_irqs       = omap2430_timer11_mpu_irqs,
 811         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
 812         .main_clk       = "gpt11_fck",
 813         .prcm           = {
 814                 .omap2 = {
 815                         .prcm_reg_id = 1,
 816                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 817                         .module_offs = CORE_MOD,
 818                         .idlest_reg_id = 1,
 819                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 820                 },
 821         },
 822         .slaves         = omap2430_timer11_slaves,
 823         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
 824         .class          = &omap2430_timer_hwmod_class,
 825         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 826 };
 827
 828 /* timer12 */
 829 static struct omap_hwmod omap2430_timer12_hwmod;
 830 static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
 831         { .irq = 48, },
 832 };
 833
 834 /* l4_core -> timer12 */
 835 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
 836         .master         = &omap2430_l4_core_hwmod,
 837         .slave          = &omap2430_timer12_hwmod,
 838         .clk            = "gpt12_ick",
 839         .addr           = omap2xxx_timer12_addrs,
 840         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 841 };
 842
 843 /* timer12 slave port */
 844 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
 845         &omap2430_l4_core__timer12,
 846 };
 847
 848 /* timer12 hwmod */
 849 static struct omap_hwmod omap2430_timer12_hwmod = {
 850         .name           = "timer12",
 851         .mpu_irqs       = omap2430_timer12_mpu_irqs,
 852         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
 853         .main_clk       = "gpt12_fck",
 854         .prcm           = {
 855                 .omap2 = {
 856                         .prcm_reg_id = 1,
 857                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 858                         .module_offs = CORE_MOD,
 859                         .idlest_reg_id = 1,
 860                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 861                 },
 862         },
 863         .slaves         = omap2430_timer12_slaves,
 864         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
 865         .class          = &omap2430_timer_hwmod_class,
 866         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 867 };
 868
 869 /* l4_wkup -> wd_timer2 */
 870 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 871         {
 872                 .pa_start       = 0x49016000,
 873                 .pa_end         = 0x4901607f,
 874                 .flags          = ADDR_TYPE_RT
 875         },
 876         { }
 877 };
 878
 879 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 880         .master         = &omap2430_l4_wkup_hwmod,
 881         .slave          = &omap2430_wd_timer2_hwmod,
 882         .clk            = "mpu_wdt_ick",
 883         .addr           = omap2430_wd_timer2_addrs,
 884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 885 };
 886
 887 /*
 888  * 'wd_timer' class
 889  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 890  * overflow condition
 891  */
 892
 893 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
 894         .rev_offs       = 0x0,
 895         .sysc_offs      = 0x0010,
 896         .syss_offs      = 0x0014,
 897         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 898                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 899         .sysc_fields    = &omap_hwmod_sysc_type1,
 900 };
 901
 902 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
 903         .name           = "wd_timer",
 904         .sysc           = &omap2430_wd_timer_sysc,
 905         .pre_shutdown   = &omap2_wd_timer_disable
 906 };
 907
 908 /* wd_timer2 */
 909 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
 910         &omap2430_l4_wkup__wd_timer2,
 911 };
 912
 913 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
 914         .name           = "wd_timer2",
 915         .class          = &omap2430_wd_timer_hwmod_class,
 916         .main_clk       = "mpu_wdt_fck",
 917         .prcm           = {
 918                 .omap2 = {
 919                         .prcm_reg_id = 1,
 920                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 921                         .module_offs = WKUP_MOD,
 922                         .idlest_reg_id = 1,
 923                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 924                 },
 925         },
 926         .slaves         = omap2430_wd_timer2_slaves,
 927         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
 928         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 929 };
 930
 931 /* UART */
 932
 933 static struct omap_hwmod_class_sysconfig uart_sysc = {
 934         .rev_offs       = 0x50,
 935         .sysc_offs      = 0x54,
 936         .syss_offs      = 0x58,
 937         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 938                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 939                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 940         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 941         .sysc_fields    = &omap_hwmod_sysc_type1,
 942 };
 943
 944 static struct omap_hwmod_class uart_class = {
 945         .name = "uart",
 946         .sysc = &uart_sysc,
 947 };
 948
 949 /* UART1 */
 950
 951 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 952         { .irq = INT_24XX_UART1_IRQ, },
 953 };
 954
 955 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 956         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 957         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 958 };
 959
 960 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
 961         &omap2_l4_core__uart1,
 962 };
 963
 964 static struct omap_hwmod omap2430_uart1_hwmod = {
 965         .name           = "uart1",
 966         .mpu_irqs       = uart1_mpu_irqs,
 967         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 968         .sdma_reqs      = uart1_sdma_reqs,
 969         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 970         .main_clk       = "uart1_fck",
 971         .prcm           = {
 972                 .omap2 = {
 973                         .module_offs = CORE_MOD,
 974                         .prcm_reg_id = 1,
 975                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 976                         .idlest_reg_id = 1,
 977                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 978                 },
 979         },
 980         .slaves         = omap2430_uart1_slaves,
 981         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
 982         .class          = &uart_class,
 983         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 984 };
 985
 986 /* UART2 */
 987
 988 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 989         { .irq = INT_24XX_UART2_IRQ, },
 990 };
 991
 992 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 993         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 994         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 995 };
 996
 997 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
 998         &omap2_l4_core__uart2,
 999 };
1000
1001 static struct omap_hwmod omap2430_uart2_hwmod = {
1002         .name           = "uart2",
1003         .mpu_irqs       = uart2_mpu_irqs,
1004         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1005         .sdma_reqs      = uart2_sdma_reqs,
1006         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1007         .main_clk       = "uart2_fck",
1008         .prcm           = {
1009                 .omap2 = {
1010                         .module_offs = CORE_MOD,
1011                         .prcm_reg_id = 1,
1012                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
1013                         .idlest_reg_id = 1,
1014                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
1015                 },
1016         },
1017         .slaves         = omap2430_uart2_slaves,
1018         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
1019         .class          = &uart_class,
1020         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1021 };
1022
1023 /* UART3 */
1024
1025 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1026         { .irq = INT_24XX_UART3_IRQ, },
1027 };
1028
1029 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1030         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1031         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1032 };
1033
1034 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
1035         &omap2_l4_core__uart3,
1036 };
1037
1038 static struct omap_hwmod omap2430_uart3_hwmod = {
1039         .name           = "uart3",
1040         .mpu_irqs       = uart3_mpu_irqs,
1041         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1042         .sdma_reqs      = uart3_sdma_reqs,
1043         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1044         .main_clk       = "uart3_fck",
1045         .prcm           = {
1046                 .omap2 = {
1047                         .module_offs = CORE_MOD,
1048                         .prcm_reg_id = 2,
1049                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
1050                         .idlest_reg_id = 2,
1051                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
1052                 },
1053         },
1054         .slaves         = omap2430_uart3_slaves,
1055         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
1056         .class          = &uart_class,
1057         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1058 };
1059
1060 /*
1061  * 'dss' class
1062  * display sub-system
1063  */
1064
1065 static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
1066         .rev_offs       = 0x0000,
1067         .sysc_offs      = 0x0010,
1068         .syss_offs      = 0x0014,
1069         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1070         .sysc_fields    = &omap_hwmod_sysc_type1,
1071 };
1072
1073 static struct omap_hwmod_class omap2430_dss_hwmod_class = {
1074         .name = "dss",
1075         .sysc = &omap2430_dss_sysc,
1076 };
1077
1078 static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
1079         { .name = "dispc", .dma_req = 5 },
1080 };
1081
1082 /* dss */
1083 /* dss master ports */
1084 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
1085         &omap2430_dss__l3,
1086 };
1087
1088 /* l4_core -> dss */
1089 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
1090         .master         = &omap2430_l4_core_hwmod,
1091         .slave          = &omap2430_dss_core_hwmod,
1092         .clk            = "dss_ick",
1093         .addr           = omap2_dss_addrs,
1094         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1095 };
1096
1097 /* dss slave ports */
1098 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
1099         &omap2430_l4_core__dss,
1100 };
1101
1102 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1103         { .role = "tv_clk", .clk = "dss_54m_fck" },
1104         { .role = "sys_clk", .clk = "dss2_fck" },
1105 };
1106
1107 static struct omap_hwmod omap2430_dss_core_hwmod = {
1108         .name           = "dss_core",
1109         .class          = &omap2430_dss_hwmod_class,
1110         .main_clk       = "dss1_fck", /* instead of dss_fck */
1111         .sdma_reqs      = omap2430_dss_sdma_chs,
1112         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
1113         .prcm           = {
1114                 .omap2 = {
1115                         .prcm_reg_id = 1,
1116                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1117                         .module_offs = CORE_MOD,
1118                         .idlest_reg_id = 1,
1119                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1120                 },
1121         },
1122         .opt_clks       = dss_opt_clks,
1123         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1124         .slaves         = omap2430_dss_slaves,
1125         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
1126         .masters        = omap2430_dss_masters,
1127         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
1128         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1129         .flags          = HWMOD_NO_IDLEST,
1130 };
1131
1132 /*
1133  * 'dispc' class
1134  * display controller
1135  */
1136
1137 static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1138         .rev_offs       = 0x0000,
1139         .sysc_offs      = 0x0010,
1140         .syss_offs      = 0x0014,
1141         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1142                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1143         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1144                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1145         .sysc_fields    = &omap_hwmod_sysc_type1,
1146 };
1147
1148 static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1149         .name = "dispc",
1150         .sysc = &omap2430_dispc_sysc,
1151 };
1152
1153 static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
1154         { .irq = 25 },
1155 };
1156
1157 /* l4_core -> dss_dispc */
1158 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1159         .master         = &omap2430_l4_core_hwmod,
1160         .slave          = &omap2430_dss_dispc_hwmod,
1161         .clk            = "dss_ick",
1162         .addr           = omap2_dss_dispc_addrs,
1163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1164 };
1165
1166 /* dss_dispc slave ports */
1167 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1168         &omap2430_l4_core__dss_dispc,
1169 };
1170
1171 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1172         .name           = "dss_dispc",
1173         .class          = &omap2430_dispc_hwmod_class,
1174         .mpu_irqs       = omap2430_dispc_irqs,
1175         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dispc_irqs),
1176         .main_clk       = "dss1_fck",
1177         .prcm           = {
1178                 .omap2 = {
1179                         .prcm_reg_id = 1,
1180                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1181                         .module_offs = CORE_MOD,
1182                         .idlest_reg_id = 1,
1183                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1184                 },
1185         },
1186         .slaves         = omap2430_dss_dispc_slaves,
1187         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1188         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1189         .flags          = HWMOD_NO_IDLEST,
1190 };
1191
1192 /*
1193  * 'rfbi' class
1194  * remote frame buffer interface
1195  */
1196
1197 static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1198         .rev_offs       = 0x0000,
1199         .sysc_offs      = 0x0010,
1200         .syss_offs      = 0x0014,
1201         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1202                            SYSC_HAS_AUTOIDLE),
1203         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1204         .sysc_fields    = &omap_hwmod_sysc_type1,
1205 };
1206
1207 static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1208         .name = "rfbi",
1209         .sysc = &omap2430_rfbi_sysc,
1210 };
1211
1212 /* l4_core -> dss_rfbi */
1213 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1214         .master         = &omap2430_l4_core_hwmod,
1215         .slave          = &omap2430_dss_rfbi_hwmod,
1216         .clk            = "dss_ick",
1217         .addr           = omap2_dss_rfbi_addrs,
1218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1219 };
1220
1221 /* dss_rfbi slave ports */
1222 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1223         &omap2430_l4_core__dss_rfbi,
1224 };
1225
1226 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1227         .name           = "dss_rfbi",
1228         .class          = &omap2430_rfbi_hwmod_class,
1229         .main_clk       = "dss1_fck",
1230         .prcm           = {
1231                 .omap2 = {
1232                         .prcm_reg_id = 1,
1233                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1234                         .module_offs = CORE_MOD,
1235                 },
1236         },
1237         .slaves         = omap2430_dss_rfbi_slaves,
1238         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1239         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1240         .flags          = HWMOD_NO_IDLEST,
1241 };
1242
1243 /*
1244  * 'venc' class
1245  * video encoder
1246  */
1247
1248 static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1249         .name = "venc",
1250 };
1251
1252 /* l4_core -> dss_venc */
1253 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1254         .master         = &omap2430_l4_core_hwmod,
1255         .slave          = &omap2430_dss_venc_hwmod,
1256         .clk            = "dss_54m_fck",
1257         .addr           = omap2_dss_venc_addrs,
1258         .flags          = OCPIF_SWSUP_IDLE,
1259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1260 };
1261
1262 /* dss_venc slave ports */
1263 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1264         &omap2430_l4_core__dss_venc,
1265 };
1266
1267 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1268         .name           = "dss_venc",
1269         .class          = &omap2430_venc_hwmod_class,
1270         .main_clk       = "dss1_fck",
1271         .prcm           = {
1272                 .omap2 = {
1273                         .prcm_reg_id = 1,
1274                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1275                         .module_offs = CORE_MOD,
1276                 },
1277         },
1278         .slaves         = omap2430_dss_venc_slaves,
1279         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
1280         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1281         .flags          = HWMOD_NO_IDLEST,
1282 };
1283
1284 /* I2C common */
1285 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1286         .rev_offs       = 0x00,
1287         .sysc_offs      = 0x20,
1288         .syss_offs      = 0x10,
1289         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1290                            SYSS_HAS_RESET_STATUS),
1291         .sysc_fields    = &omap_hwmod_sysc_type1,
1292 };
1293
1294 static struct omap_hwmod_class i2c_class = {
1295         .name           = "i2c",
1296         .sysc           = &i2c_sysc,
1297 };
1298
1299 static struct omap_i2c_dev_attr i2c_dev_attr = {
1300         .fifo_depth     = 8, /* bytes */
1301 };
1302
1303 /* I2C1 */
1304
1305 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1306         { .irq = INT_24XX_I2C1_IRQ, },
1307 };
1308
1309 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1310         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1311         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1312 };
1313
1314 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1315         &omap2430_l4_core__i2c1,
1316 };
1317
1318 static struct omap_hwmod omap2430_i2c1_hwmod = {
1319         .name           = "i2c1",
1320         .mpu_irqs       = i2c1_mpu_irqs,
1321         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1322         .sdma_reqs      = i2c1_sdma_reqs,
1323         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1324         .main_clk       = "i2chs1_fck",
1325         .prcm           = {
1326                 .omap2 = {
1327                         /*
1328                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1329                          * I2CHS IP's do not follow the usual pattern.
1330                          * prcm_reg_id alone cannot be used to program
1331                          * the iclk and fclk. Needs to be handled using
1332                          * additional flags when clk handling is moved
1333                          * to hwmod framework.
1334                          */
1335                         .module_offs = CORE_MOD,
1336                         .prcm_reg_id = 1,
1337                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1338                         .idlest_reg_id = 1,
1339                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1340                 },
1341         },
1342         .slaves         = omap2430_i2c1_slaves,
1343         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
1344         .class          = &i2c_class,
1345         .dev_attr       = &i2c_dev_attr,
1346         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1347 };
1348
1349 /* I2C2 */
1350
1351 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1352         { .irq = INT_24XX_I2C2_IRQ, },
1353 };
1354
1355 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1356         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1357         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1358 };
1359
1360 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1361         &omap2430_l4_core__i2c2,
1362 };
1363
1364 static struct omap_hwmod omap2430_i2c2_hwmod = {
1365         .name           = "i2c2",
1366         .mpu_irqs       = i2c2_mpu_irqs,
1367         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1368         .sdma_reqs      = i2c2_sdma_reqs,
1369         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1370         .main_clk       = "i2chs2_fck",
1371         .prcm           = {
1372                 .omap2 = {
1373                         .module_offs = CORE_MOD,
1374                         .prcm_reg_id = 1,
1375                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1376                         .idlest_reg_id = 1,
1377                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1378                 },
1379         },
1380         .slaves         = omap2430_i2c2_slaves,
1381         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
1382         .class          = &i2c_class,
1383         .dev_attr       = &i2c_dev_attr,
1384         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1385 };
1386
1387 /* l4_wkup -> gpio1 */
1388 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1389         {
1390                 .pa_start       = 0x4900C000,
1391                 .pa_end         = 0x4900C1ff,
1392                 .flags          = ADDR_TYPE_RT
1393         },
1394         { }
1395 };
1396
1397 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1398         .master         = &omap2430_l4_wkup_hwmod,
1399         .slave          = &omap2430_gpio1_hwmod,
1400         .clk            = "gpios_ick",
1401         .addr           = omap2430_gpio1_addr_space,
1402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1403 };
1404
1405 /* l4_wkup -> gpio2 */
1406 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1407         {
1408                 .pa_start       = 0x4900E000,
1409                 .pa_end         = 0x4900E1ff,
1410                 .flags          = ADDR_TYPE_RT
1411         },
1412         { }
1413 };
1414
1415 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1416         .master         = &omap2430_l4_wkup_hwmod,
1417         .slave          = &omap2430_gpio2_hwmod,
1418         .clk            = "gpios_ick",
1419         .addr           = omap2430_gpio2_addr_space,
1420         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1421 };
1422
1423 /* l4_wkup -> gpio3 */
1424 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1425         {
1426                 .pa_start       = 0x49010000,
1427                 .pa_end         = 0x490101ff,
1428                 .flags          = ADDR_TYPE_RT
1429         },
1430         { }
1431 };
1432
1433 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1434         .master         = &omap2430_l4_wkup_hwmod,
1435         .slave          = &omap2430_gpio3_hwmod,
1436         .clk            = "gpios_ick",
1437         .addr           = omap2430_gpio3_addr_space,
1438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1439 };
1440
1441 /* l4_wkup -> gpio4 */
1442 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1443         {
1444                 .pa_start       = 0x49012000,
1445                 .pa_end         = 0x490121ff,
1446                 .flags          = ADDR_TYPE_RT
1447         },
1448         { }
1449 };
1450
1451 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1452         .master         = &omap2430_l4_wkup_hwmod,
1453         .slave          = &omap2430_gpio4_hwmod,
1454         .clk            = "gpios_ick",
1455         .addr           = omap2430_gpio4_addr_space,
1456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1457 };
1458
1459 /* l4_core -> gpio5 */
1460 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1461         {
1462                 .pa_start       = 0x480B6000,
1463                 .pa_end         = 0x480B61ff,
1464                 .flags          = ADDR_TYPE_RT
1465         },
1466         { }
1467 };
1468
1469 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1470         .master         = &omap2430_l4_core_hwmod,
1471         .slave          = &omap2430_gpio5_hwmod,
1472         .clk            = "gpio5_ick",
1473         .addr           = omap2430_gpio5_addr_space,
1474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1475 };
1476
1477 /* gpio dev_attr */
1478 static struct omap_gpio_dev_attr gpio_dev_attr = {
1479         .bank_width = 32,
1480         .dbck_flag = false,
1481 };
1482
1483 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1484         .rev_offs       = 0x0000,
1485         .sysc_offs      = 0x0010,
1486         .syss_offs      = 0x0014,
1487         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1488                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1489                            SYSS_HAS_RESET_STATUS),
1490         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1491         .sysc_fields    = &omap_hwmod_sysc_type1,
1492 };
1493
1494 /*
1495  * 'gpio' class
1496  * general purpose io module
1497  */
1498 static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1499         .name = "gpio",
1500         .sysc = &omap243x_gpio_sysc,
1501         .rev = 0,
1502 };
1503
1504 /* gpio1 */
1505 static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
1506         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1507 };
1508
1509 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1510         &omap2430_l4_wkup__gpio1,
1511 };
1512
1513 static struct omap_hwmod omap2430_gpio1_hwmod = {
1514         .name           = "gpio1",
1515         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1516         .mpu_irqs       = omap243x_gpio1_irqs,
1517         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
1518         .main_clk       = "gpios_fck",
1519         .prcm           = {
1520                 .omap2 = {
1521                         .prcm_reg_id = 1,
1522                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1523                         .module_offs = WKUP_MOD,
1524                         .idlest_reg_id = 1,
1525                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1526                 },
1527         },
1528         .slaves         = omap2430_gpio1_slaves,
1529         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
1530         .class          = &omap243x_gpio_hwmod_class,
1531         .dev_attr       = &gpio_dev_attr,
1532         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1533 };
1534
1535 /* gpio2 */
1536 static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
1537         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1538 };
1539
1540 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1541         &omap2430_l4_wkup__gpio2,
1542 };
1543
1544 static struct omap_hwmod omap2430_gpio2_hwmod = {
1545         .name           = "gpio2",
1546         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1547         .mpu_irqs       = omap243x_gpio2_irqs,
1548         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
1549         .main_clk       = "gpios_fck",
1550         .prcm           = {
1551                 .omap2 = {
1552                         .prcm_reg_id = 1,
1553                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1554                         .module_offs = WKUP_MOD,
1555                         .idlest_reg_id = 1,
1556                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1557                 },
1558         },
1559         .slaves         = omap2430_gpio2_slaves,
1560         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
1561         .class          = &omap243x_gpio_hwmod_class,
1562         .dev_attr       = &gpio_dev_attr,
1563         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1564 };
1565
1566 /* gpio3 */
1567 static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
1568         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1569 };
1570
1571 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1572         &omap2430_l4_wkup__gpio3,
1573 };
1574
1575 static struct omap_hwmod omap2430_gpio3_hwmod = {
1576         .name           = "gpio3",
1577         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1578         .mpu_irqs       = omap243x_gpio3_irqs,
1579         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
1580         .main_clk       = "gpios_fck",
1581         .prcm           = {
1582                 .omap2 = {
1583                         .prcm_reg_id = 1,
1584                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1585                         .module_offs = WKUP_MOD,
1586                         .idlest_reg_id = 1,
1587                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1588                 },
1589         },
1590         .slaves         = omap2430_gpio3_slaves,
1591         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
1592         .class          = &omap243x_gpio_hwmod_class,
1593         .dev_attr       = &gpio_dev_attr,
1594         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1595 };
1596
1597 /* gpio4 */
1598 static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
1599         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1600 };
1601
1602 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1603         &omap2430_l4_wkup__gpio4,
1604 };
1605
1606 static struct omap_hwmod omap2430_gpio4_hwmod = {
1607         .name           = "gpio4",
1608         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1609         .mpu_irqs       = omap243x_gpio4_irqs,
1610         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
1611         .main_clk       = "gpios_fck",
1612         .prcm           = {
1613                 .omap2 = {
1614                         .prcm_reg_id = 1,
1615                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1616                         .module_offs = WKUP_MOD,
1617                         .idlest_reg_id = 1,
1618                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1619                 },
1620         },
1621         .slaves         = omap2430_gpio4_slaves,
1622         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
1623         .class          = &omap243x_gpio_hwmod_class,
1624         .dev_attr       = &gpio_dev_attr,
1625         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1626 };
1627
1628 /* gpio5 */
1629 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1630         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1631 };
1632
1633 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1634         &omap2430_l4_core__gpio5,
1635 };
1636
1637 static struct omap_hwmod omap2430_gpio5_hwmod = {
1638         .name           = "gpio5",
1639         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1640         .mpu_irqs       = omap243x_gpio5_irqs,
1641         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
1642         .main_clk       = "gpio5_fck",
1643         .prcm           = {
1644                 .omap2 = {
1645                         .prcm_reg_id = 2,
1646                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1647                         .module_offs = CORE_MOD,
1648                         .idlest_reg_id = 2,
1649                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1650                 },
1651         },
1652         .slaves         = omap2430_gpio5_slaves,
1653         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
1654         .class          = &omap243x_gpio_hwmod_class,
1655         .dev_attr       = &gpio_dev_attr,
1656         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1657 };
1658
1659 /* dma_system */
1660 static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1661         .rev_offs       = 0x0000,
1662         .sysc_offs      = 0x002c,
1663         .syss_offs      = 0x0028,
1664         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1665                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1666                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1667         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1668         .sysc_fields    = &omap_hwmod_sysc_type1,
1669 };
1670
1671 static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1672         .name = "dma",
1673         .sysc = &omap2430_dma_sysc,
1674 };
1675
1676 /* dma attributes */
1677 static struct omap_dma_dev_attr dma_dev_attr = {
1678         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1679                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1680         .lch_count = 32,
1681 };
1682
1683 static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
1684         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1685         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1686         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1687         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1688 };
1689
1690 /* dma_system -> L3 */
1691 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1692         .master         = &omap2430_dma_system_hwmod,
1693         .slave          = &omap2430_l3_main_hwmod,
1694         .clk            = "core_l3_ck",
1695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1696 };
1697
1698 /* dma_system master ports */
1699 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1700         &omap2430_dma_system__l3,
1701 };
1702
1703 /* l4_core -> dma_system */
1704 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1705         .master         = &omap2430_l4_core_hwmod,
1706         .slave          = &omap2430_dma_system_hwmod,
1707         .clk            = "sdma_ick",
1708         .addr           = omap2_dma_system_addrs,
1709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1710 };
1711
1712 /* dma_system slave ports */
1713 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1714         &omap2430_l4_core__dma_system,
1715 };
1716
1717 static struct omap_hwmod omap2430_dma_system_hwmod = {
1718         .name           = "dma",
1719         .class          = &omap2430_dma_hwmod_class,
1720         .mpu_irqs       = omap2430_dma_system_irqs,
1721         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
1722         .main_clk       = "core_l3_ck",
1723         .slaves         = omap2430_dma_system_slaves,
1724         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
1725         .masters        = omap2430_dma_system_masters,
1726         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
1727         .dev_attr       = &dma_dev_attr,
1728         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1729         .flags          = HWMOD_NO_IDLEST,
1730 };
1731
1732 /*
1733  * 'mailbox' class
1734  * mailbox module allowing communication between the on-chip processors
1735  * using a queued mailbox-interrupt mechanism.
1736  */
1737
1738 static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1739         .rev_offs       = 0x000,
1740         .sysc_offs      = 0x010,
1741         .syss_offs      = 0x014,
1742         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1743                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1744         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1745         .sysc_fields    = &omap_hwmod_sysc_type1,
1746 };
1747
1748 static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1749         .name = "mailbox",
1750         .sysc = &omap2430_mailbox_sysc,
1751 };
1752
1753 /* mailbox */
1754 static struct omap_hwmod omap2430_mailbox_hwmod;
1755 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1756         { .irq = 26 },
1757 };
1758
1759 /* l4_core -> mailbox */
1760 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
1761         .master         = &omap2430_l4_core_hwmod,
1762         .slave          = &omap2430_mailbox_hwmod,
1763         .addr           = omap2_mailbox_addrs,
1764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1765 };
1766
1767 /* mailbox slave ports */
1768 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1769         &omap2430_l4_core__mailbox,
1770 };
1771
1772 static struct omap_hwmod omap2430_mailbox_hwmod = {
1773         .name           = "mailbox",
1774         .class          = &omap2430_mailbox_hwmod_class,
1775         .mpu_irqs       = omap2430_mailbox_irqs,
1776         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mailbox_irqs),
1777         .main_clk       = "mailboxes_ick",
1778         .prcm           = {
1779                 .omap2 = {
1780                         .prcm_reg_id = 1,
1781                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1782                         .module_offs = CORE_MOD,
1783                         .idlest_reg_id = 1,
1784                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1785                 },
1786         },
1787         .slaves         = omap2430_mailbox_slaves,
1788         .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
1789         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1790 };
1791
1792 /*
1793  * 'mcspi' class
1794  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1795  * bus
1796  */
1797
1798 static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
1799         .rev_offs       = 0x0000,
1800         .sysc_offs      = 0x0010,
1801         .syss_offs      = 0x0014,
1802         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1803                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1804                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1805         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1806         .sysc_fields    = &omap_hwmod_sysc_type1,
1807 };
1808
1809 static struct omap_hwmod_class omap2430_mcspi_class = {
1810         .name = "mcspi",
1811         .sysc = &omap2430_mcspi_sysc,
1812         .rev = OMAP2_MCSPI_REV,
1813 };
1814
1815 /* mcspi1 */
1816 static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
1817         { .irq = 65 },
1818 };
1819
1820 static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
1821         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1822         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1823         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1824         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1825         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1826         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1827         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1828         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1829 };
1830
1831 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1832         &omap2430_l4_core__mcspi1,
1833 };
1834
1835 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1836         .num_chipselect = 4,
1837 };
1838
1839 static struct omap_hwmod omap2430_mcspi1_hwmod = {
1840         .name           = "mcspi1_hwmod",
1841         .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
1842         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
1843         .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
1844         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
1845         .main_clk       = "mcspi1_fck",
1846         .prcm           = {
1847                 .omap2 = {
1848                         .module_offs = CORE_MOD,
1849                         .prcm_reg_id = 1,
1850                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1851                         .idlest_reg_id = 1,
1852                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1853                 },
1854         },
1855         .slaves         = omap2430_mcspi1_slaves,
1856         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
1857         .class          = &omap2430_mcspi_class,
1858         .dev_attr       = &omap_mcspi1_dev_attr,
1859         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1860 };
1861
1862 /* mcspi2 */
1863 static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
1864         { .irq = 66 },
1865 };
1866
1867 static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
1868         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1869         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1870         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1871         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1872 };
1873
1874 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1875         &omap2430_l4_core__mcspi2,
1876 };
1877
1878 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1879         .num_chipselect = 2,
1880 };
1881
1882 static struct omap_hwmod omap2430_mcspi2_hwmod = {
1883         .name           = "mcspi2_hwmod",
1884         .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
1885         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
1886         .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
1887         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
1888         .main_clk       = "mcspi2_fck",
1889         .prcm           = {
1890                 .omap2 = {
1891                         .module_offs = CORE_MOD,
1892                         .prcm_reg_id = 1,
1893                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1894                         .idlest_reg_id = 1,
1895                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1896                 },
1897         },
1898         .slaves         = omap2430_mcspi2_slaves,
1899         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
1900         .class          = &omap2430_mcspi_class,
1901         .dev_attr       = &omap_mcspi2_dev_attr,
1902         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1903 };
1904
1905 /* mcspi3 */
1906 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
1907         { .irq = 91 },
1908 };
1909
1910 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1911         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
1912         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
1913         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
1914         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1915 };
1916
1917 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1918         &omap2430_l4_core__mcspi3,
1919 };
1920
1921 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1922         .num_chipselect = 2,
1923 };
1924
1925 static struct omap_hwmod omap2430_mcspi3_hwmod = {
1926         .name           = "mcspi3_hwmod",
1927         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
1928         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
1929         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
1930         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
1931         .main_clk       = "mcspi3_fck",
1932         .prcm           = {
1933                 .omap2 = {
1934                         .module_offs = CORE_MOD,
1935                         .prcm_reg_id = 2,
1936                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
1937                         .idlest_reg_id = 2,
1938                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1939                 },
1940         },
1941         .slaves         = omap2430_mcspi3_slaves,
1942         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
1943         .class          = &omap2430_mcspi_class,
1944         .dev_attr       = &omap_mcspi3_dev_attr,
1945         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1946 };
1947
1948 /*
1949  * usbhsotg
1950  */
1951 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1952         .rev_offs       = 0x0400,
1953         .sysc_offs      = 0x0404,
1954         .syss_offs      = 0x0408,
1955         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1956                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1957                           SYSC_HAS_AUTOIDLE),
1958         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1959                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1960         .sysc_fields    = &omap_hwmod_sysc_type1,
1961 };
1962
1963 static struct omap_hwmod_class usbotg_class = {
1964         .name = "usbotg",
1965         .sysc = &omap2430_usbhsotg_sysc,
1966 };
1967
1968 /* usb_otg_hs */
1969 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
1970
1971         { .name = "mc", .irq = 92 },
1972         { .name = "dma", .irq = 93 },
1973 };
1974
1975 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1976         .name           = "usb_otg_hs",
1977         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
1978         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
1979         .main_clk       = "usbhs_ick",
1980         .prcm           = {
1981                 .omap2 = {
1982                         .prcm_reg_id = 1,
1983                         .module_bit = OMAP2430_EN_USBHS_MASK,
1984                         .module_offs = CORE_MOD,
1985                         .idlest_reg_id = 1,
1986                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1987                 },
1988         },
1989         .masters        = omap2430_usbhsotg_masters,
1990         .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
1991         .slaves         = omap2430_usbhsotg_slaves,
1992         .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1993         .class          = &usbotg_class,
1994         /*
1995          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1996          * broken when autoidle is enabled
1997          * workaround is to disable the autoidle bit at module level.
1998          */
1999         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2000                                 | HWMOD_SWSUP_MSTANDBY,
2001         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
2002 };
2003
2004 /*
2005  * 'mcbsp' class
2006  * multi channel buffered serial port controller
2007  */
2008
2009 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
2010         .rev_offs       = 0x007C,
2011         .sysc_offs      = 0x008C,
2012         .sysc_flags     = (SYSC_HAS_SOFTRESET),
2013         .sysc_fields    = &omap_hwmod_sysc_type1,
2014 };
2015
2016 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
2017         .name = "mcbsp",
2018         .sysc = &omap2430_mcbsp_sysc,
2019         .rev  = MCBSP_CONFIG_TYPE2,
2020 };
2021
2022 /* mcbsp1 */
2023 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
2024         { .name = "tx",         .irq = 59 },
2025         { .name = "rx",         .irq = 60 },
2026         { .name = "ovr",        .irq = 61 },
2027         { .name = "common",     .irq = 64 },
2028 };
2029
2030 static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
2031         { .name = "rx", .dma_req = 32 },
2032         { .name = "tx", .dma_req = 31 },
2033 };
2034
2035 /* l4_core -> mcbsp1 */
2036 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
2037         .master         = &omap2430_l4_core_hwmod,
2038         .slave          = &omap2430_mcbsp1_hwmod,
2039         .clk            = "mcbsp1_ick",
2040         .addr           = omap2_mcbsp1_addrs,
2041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2042 };
2043
2044 /* mcbsp1 slave ports */
2045 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
2046         &omap2430_l4_core__mcbsp1,
2047 };
2048
2049 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
2050         .name           = "mcbsp1",
2051         .class          = &omap2430_mcbsp_hwmod_class,
2052         .mpu_irqs       = omap2430_mcbsp1_irqs,
2053         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp1_irqs),
2054         .sdma_reqs      = omap2430_mcbsp1_sdma_chs,
2055         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
2056         .main_clk       = "mcbsp1_fck",
2057         .prcm           = {
2058                 .omap2 = {
2059                         .prcm_reg_id = 1,
2060                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2061                         .module_offs = CORE_MOD,
2062                         .idlest_reg_id = 1,
2063                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2064                 },
2065         },
2066         .slaves         = omap2430_mcbsp1_slaves,
2067         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
2068         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2069 };
2070
2071 /* mcbsp2 */
2072 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
2073         { .name = "tx",         .irq = 62 },
2074         { .name = "rx",         .irq = 63 },
2075         { .name = "common",     .irq = 16 },
2076 };
2077
2078 static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
2079         { .name = "rx", .dma_req = 34 },
2080         { .name = "tx", .dma_req = 33 },
2081 };
2082
2083 /* l4_core -> mcbsp2 */
2084 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
2085         .master         = &omap2430_l4_core_hwmod,
2086         .slave          = &omap2430_mcbsp2_hwmod,
2087         .clk            = "mcbsp2_ick",
2088         .addr           = omap2xxx_mcbsp2_addrs,
2089         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2090 };
2091
2092 /* mcbsp2 slave ports */
2093 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
2094         &omap2430_l4_core__mcbsp2,
2095 };
2096
2097 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
2098         .name           = "mcbsp2",
2099         .class          = &omap2430_mcbsp_hwmod_class,
2100         .mpu_irqs       = omap2430_mcbsp2_irqs,
2101         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp2_irqs),
2102         .sdma_reqs      = omap2430_mcbsp2_sdma_chs,
2103         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
2104         .main_clk       = "mcbsp2_fck",
2105         .prcm           = {
2106                 .omap2 = {
2107                         .prcm_reg_id = 1,
2108                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2109                         .module_offs = CORE_MOD,
2110                         .idlest_reg_id = 1,
2111                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2112                 },
2113         },
2114         .slaves         = omap2430_mcbsp2_slaves,
2115         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
2116         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2117 };
2118
2119 /* mcbsp3 */
2120 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
2121         { .name = "tx",         .irq = 89 },
2122         { .name = "rx",         .irq = 90 },
2123         { .name = "common",     .irq = 17 },
2124 };
2125
2126 static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
2127         { .name = "rx", .dma_req = 18 },
2128         { .name = "tx", .dma_req = 17 },
2129 };
2130
2131 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
2132         {
2133                 .name           = "mpu",
2134                 .pa_start       = 0x4808C000,
2135                 .pa_end         = 0x4808C0ff,
2136                 .flags          = ADDR_TYPE_RT
2137         },
2138         { }
2139 };
2140
2141 /* l4_core -> mcbsp3 */
2142 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
2143         .master         = &omap2430_l4_core_hwmod,
2144         .slave          = &omap2430_mcbsp3_hwmod,
2145         .clk            = "mcbsp3_ick",
2146         .addr           = omap2430_mcbsp3_addrs,
2147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2148 };
2149
2150 /* mcbsp3 slave ports */
2151 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
2152         &omap2430_l4_core__mcbsp3,
2153 };
2154
2155 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
2156         .name           = "mcbsp3",
2157         .class          = &omap2430_mcbsp_hwmod_class,
2158         .mpu_irqs       = omap2430_mcbsp3_irqs,
2159         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp3_irqs),
2160         .sdma_reqs      = omap2430_mcbsp3_sdma_chs,
2161         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
2162         .main_clk       = "mcbsp3_fck",
2163         .prcm           = {
2164                 .omap2 = {
2165                         .prcm_reg_id = 1,
2166                         .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
2167                         .module_offs = CORE_MOD,
2168                         .idlest_reg_id = 2,
2169                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
2170                 },
2171         },
2172         .slaves         = omap2430_mcbsp3_slaves,
2173         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
2174         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2175 };
2176
2177 /* mcbsp4 */
2178 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
2179         { .name = "tx",         .irq = 54 },
2180         { .name = "rx",         .irq = 55 },
2181         { .name = "common",     .irq = 18 },
2182 };
2183
2184 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
2185         { .name = "rx", .dma_req = 20 },
2186         { .name = "tx", .dma_req = 19 },
2187 };
2188
2189 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
2190         {
2191                 .name           = "mpu",
2192                 .pa_start       = 0x4808E000,
2193                 .pa_end         = 0x4808E0ff,
2194                 .flags          = ADDR_TYPE_RT
2195         },
2196         { }
2197 };
2198
2199 /* l4_core -> mcbsp4 */
2200 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
2201         .master         = &omap2430_l4_core_hwmod,
2202         .slave          = &omap2430_mcbsp4_hwmod,
2203         .clk            = "mcbsp4_ick",
2204         .addr           = omap2430_mcbsp4_addrs,
2205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2206 };
2207
2208 /* mcbsp4 slave ports */
2209 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
2210         &omap2430_l4_core__mcbsp4,
2211 };
2212
2213 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
2214         .name           = "mcbsp4",
2215         .class          = &omap2430_mcbsp_hwmod_class,
2216         .mpu_irqs       = omap2430_mcbsp4_irqs,
2217         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp4_irqs),
2218         .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
2219         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
2220         .main_clk       = "mcbsp4_fck",
2221         .prcm           = {
2222                 .omap2 = {
2223                         .prcm_reg_id = 1,
2224                         .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
2225                         .module_offs = CORE_MOD,
2226                         .idlest_reg_id = 2,
2227                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
2228                 },
2229         },
2230         .slaves         = omap2430_mcbsp4_slaves,
2231         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
2232         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2233 };
2234
2235 /* mcbsp5 */
2236 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
2237         { .name = "tx",         .irq = 81 },
2238         { .name = "rx",         .irq = 82 },
2239         { .name = "common",     .irq = 19 },
2240 };
2241
2242 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
2243         { .name = "rx", .dma_req = 22 },
2244         { .name = "tx", .dma_req = 21 },
2245 };
2246
2247 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
2248         {
2249                 .name           = "mpu",
2250                 .pa_start       = 0x48096000,
2251                 .pa_end         = 0x480960ff,
2252                 .flags          = ADDR_TYPE_RT
2253         },
2254         { }
2255 };
2256
2257 /* l4_core -> mcbsp5 */
2258 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
2259         .master         = &omap2430_l4_core_hwmod,
2260         .slave          = &omap2430_mcbsp5_hwmod,
2261         .clk            = "mcbsp5_ick",
2262         .addr           = omap2430_mcbsp5_addrs,
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 /* mcbsp5 slave ports */
2267 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
2268         &omap2430_l4_core__mcbsp5,
2269 };
2270
2271 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
2272         .name           = "mcbsp5",
2273         .class          = &omap2430_mcbsp_hwmod_class,
2274         .mpu_irqs       = omap2430_mcbsp5_irqs,
2275         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp5_irqs),
2276         .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
2277         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
2278         .main_clk       = "mcbsp5_fck",
2279         .prcm           = {
2280                 .omap2 = {
2281                         .prcm_reg_id = 1,
2282                         .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
2283                         .module_offs = CORE_MOD,
2284                         .idlest_reg_id = 2,
2285                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
2286                 },
2287         },
2288         .slaves         = omap2430_mcbsp5_slaves,
2289         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
2290         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2291 };
2292
2293 /* MMC/SD/SDIO common */
2294
2295 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
2296         .rev_offs       = 0x1fc,
2297         .sysc_offs      = 0x10,
2298         .syss_offs      = 0x14,
2299         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2300                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2301                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2302         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2303         .sysc_fields    = &omap_hwmod_sysc_type1,
2304 };
2305
2306 static struct omap_hwmod_class omap2430_mmc_class = {
2307         .name = "mmc",
2308         .sysc = &omap2430_mmc_sysc,
2309 };
2310
2311 /* MMC/SD/SDIO1 */
2312
2313 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2314         { .irq = 83 },
2315 };
2316
2317 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2318         { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2319         { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
2320 };
2321
2322 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
2323         { .role = "dbck", .clk = "mmchsdb1_fck" },
2324 };
2325
2326 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
2327         &omap2430_l4_core__mmc1,
2328 };
2329
2330 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2331         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2332 };
2333
2334 static struct omap_hwmod omap2430_mmc1_hwmod = {
2335         .name           = "mmc1",
2336         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2337         .mpu_irqs       = omap2430_mmc1_mpu_irqs,
2338         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2339         .sdma_reqs      = omap2430_mmc1_sdma_reqs,
2340         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2341         .opt_clks       = omap2430_mmc1_opt_clks,
2342         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2343         .main_clk       = "mmchs1_fck",
2344         .prcm           = {
2345                 .omap2 = {
2346                         .module_offs = CORE_MOD,
2347                         .prcm_reg_id = 2,
2348                         .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
2349                         .idlest_reg_id = 2,
2350                         .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
2351                 },
2352         },
2353         .dev_attr       = &mmc1_dev_attr,
2354         .slaves         = omap2430_mmc1_slaves,
2355         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
2356         .class          = &omap2430_mmc_class,
2357         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2358 };
2359
2360 /* MMC/SD/SDIO2 */
2361
2362 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2363         { .irq = 86 },
2364 };
2365
2366 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2367         { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2368         { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
2369 };
2370
2371 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
2372         { .role = "dbck", .clk = "mmchsdb2_fck" },
2373 };
2374
2375 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
2376         &omap2430_l4_core__mmc2,
2377 };
2378
2379 static struct omap_hwmod omap2430_mmc2_hwmod = {
2380         .name           = "mmc2",
2381         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2382         .mpu_irqs       = omap2430_mmc2_mpu_irqs,
2383         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2384         .sdma_reqs      = omap2430_mmc2_sdma_reqs,
2385         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2386         .opt_clks       = omap2430_mmc2_opt_clks,
2387         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2388         .main_clk       = "mmchs2_fck",
2389         .prcm           = {
2390                 .omap2 = {
2391                         .module_offs = CORE_MOD,
2392                         .prcm_reg_id = 2,
2393                         .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
2394                         .idlest_reg_id = 2,
2395                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2396                 },
2397         },
2398         .slaves         = omap2430_mmc2_slaves,
2399         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
2400         .class          = &omap2430_mmc_class,
2401         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2402 };
2403
2404 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2405         &omap2430_l3_main_hwmod,
2406         &omap2430_l4_core_hwmod,
2407         &omap2430_l4_wkup_hwmod,
2408         &omap2430_mpu_hwmod,
2409         &omap2430_iva_hwmod,
2410
2411         &omap2430_timer1_hwmod,
2412         &omap2430_timer2_hwmod,
2413         &omap2430_timer3_hwmod,
2414         &omap2430_timer4_hwmod,
2415         &omap2430_timer5_hwmod,
2416         &omap2430_timer6_hwmod,
2417         &omap2430_timer7_hwmod,
2418         &omap2430_timer8_hwmod,
2419         &omap2430_timer9_hwmod,
2420         &omap2430_timer10_hwmod,
2421         &omap2430_timer11_hwmod,
2422         &omap2430_timer12_hwmod,
2423
2424         &omap2430_wd_timer2_hwmod,
2425         &omap2430_uart1_hwmod,
2426         &omap2430_uart2_hwmod,
2427         &omap2430_uart3_hwmod,
2428         /* dss class */
2429         &omap2430_dss_core_hwmod,
2430         &omap2430_dss_dispc_hwmod,
2431         &omap2430_dss_rfbi_hwmod,
2432         &omap2430_dss_venc_hwmod,
2433         /* i2c class */
2434         &omap2430_i2c1_hwmod,
2435         &omap2430_i2c2_hwmod,
2436         &omap2430_mmc1_hwmod,
2437         &omap2430_mmc2_hwmod,
2438
2439         /* gpio class */
2440         &omap2430_gpio1_hwmod,
2441         &omap2430_gpio2_hwmod,
2442         &omap2430_gpio3_hwmod,
2443         &omap2430_gpio4_hwmod,
2444         &omap2430_gpio5_hwmod,
2445
2446         /* dma_system class*/
2447         &omap2430_dma_system_hwmod,
2448
2449         /* mcbsp class */
2450         &omap2430_mcbsp1_hwmod,
2451         &omap2430_mcbsp2_hwmod,
2452         &omap2430_mcbsp3_hwmod,
2453         &omap2430_mcbsp4_hwmod,
2454         &omap2430_mcbsp5_hwmod,
2455
2456         /* mailbox class */
2457         &omap2430_mailbox_hwmod,
2458
2459         /* mcspi class */
2460         &omap2430_mcspi1_hwmod,
2461         &omap2430_mcspi2_hwmod,
2462         &omap2430_mcspi3_hwmod,
2463
2464         /* usbotg class*/
2465         &omap2430_usbhsotg_hwmod,
2466
2467         NULL,
2468 };
2469
2470 int __init omap2430_hwmod_init(void)
2471 {
2472         return omap_hwmod_register(omap2430_hwmods);
2473 }