Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcbsp.h>
  22 #include <plat/mcspi.h>
  23 #include <plat/dmtimer.h>
  24 #include <plat/mmc.h>
  25 #include <plat/l3_2xxx.h>
  26
  27 #include "omap_hwmod_common_data.h"
  28
  29 #include "prm-regbits-24xx.h"
  30 #include "cm-regbits-24xx.h"
  31 #include "wd_timer.h"
  32
  33 /*
  34  * OMAP2430 hardware module integration data
  35  *
  36  * ALl of the data in this section should be autogeneratable from the
  37  * TI hardware database or other technical documentation.  Data that
  38  * is driver-specific or driver-kernel integration-specific belongs
  39  * elsewhere.
  40  */
  41
  42 static struct omap_hwmod omap2430_mpu_hwmod;
  43 static struct omap_hwmod omap2430_iva_hwmod;
  44 static struct omap_hwmod omap2430_l3_main_hwmod;
  45 static struct omap_hwmod omap2430_l4_core_hwmod;
  46 static struct omap_hwmod omap2430_dss_core_hwmod;
  47 static struct omap_hwmod omap2430_dss_dispc_hwmod;
  48 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
  49 static struct omap_hwmod omap2430_dss_venc_hwmod;
  50 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  51 static struct omap_hwmod omap2430_gpio1_hwmod;
  52 static struct omap_hwmod omap2430_gpio2_hwmod;
  53 static struct omap_hwmod omap2430_gpio3_hwmod;
  54 static struct omap_hwmod omap2430_gpio4_hwmod;
  55 static struct omap_hwmod omap2430_gpio5_hwmod;
  56 static struct omap_hwmod omap2430_dma_system_hwmod;
  57 static struct omap_hwmod omap2430_mcbsp1_hwmod;
  58 static struct omap_hwmod omap2430_mcbsp2_hwmod;
  59 static struct omap_hwmod omap2430_mcbsp3_hwmod;
  60 static struct omap_hwmod omap2430_mcbsp4_hwmod;
  61 static struct omap_hwmod omap2430_mcbsp5_hwmod;
  62 static struct omap_hwmod omap2430_mcspi1_hwmod;
  63 static struct omap_hwmod omap2430_mcspi2_hwmod;
  64 static struct omap_hwmod omap2430_mcspi3_hwmod;
  65 static struct omap_hwmod omap2430_mmc1_hwmod;
  66 static struct omap_hwmod omap2430_mmc2_hwmod;
  67
  68 /* L3 -> L4_CORE interface */
  69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  70         .master = &omap2430_l3_main_hwmod,
  71         .slave  = &omap2430_l4_core_hwmod,
  72         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  73 };
  74
  75 /* MPU -> L3 interface */
  76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  77         .master = &omap2430_mpu_hwmod,
  78         .slave  = &omap2430_l3_main_hwmod,
  79         .user   = OCP_USER_MPU,
  80 };
  81
  82 /* Slave interfaces on the L3 interconnect */
  83 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  84         &omap2430_mpu__l3_main,
  85 };
  86
  87 /* DSS -> l3 */
  88 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
  89         .master         = &omap2430_dss_core_hwmod,
  90         .slave          = &omap2430_l3_main_hwmod,
  91         .fw = {
  92                 .omap2 = {
  93                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  94                         .flags  = OMAP_FIREWALL_L3,
  95                 }
  96         },
  97         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  98 };
  99
 100 /* Master interfaces on the L3 interconnect */
 101 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
 102         &omap2430_l3_main__l4_core,
 103 };
 104
 105 /* L3 */
 106 static struct omap_hwmod omap2430_l3_main_hwmod = {
 107         .name           = "l3_main",
 108         .class          = &l3_hwmod_class,
 109         .masters        = omap2430_l3_main_masters,
 110         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
 111         .slaves         = omap2430_l3_main_slaves,
 112         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
 113         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 114         .flags          = HWMOD_NO_IDLEST,
 115 };
 116
 117 static struct omap_hwmod omap2430_l4_wkup_hwmod;
 118 static struct omap_hwmod omap2430_uart1_hwmod;
 119 static struct omap_hwmod omap2430_uart2_hwmod;
 120 static struct omap_hwmod omap2430_uart3_hwmod;
 121 static struct omap_hwmod omap2430_i2c1_hwmod;
 122 static struct omap_hwmod omap2430_i2c2_hwmod;
 123
 124 static struct omap_hwmod omap2430_usbhsotg_hwmod;
 125
 126 /* l3_core -> usbhsotg  interface */
 127 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 128         .master         = &omap2430_usbhsotg_hwmod,
 129         .slave          = &omap2430_l3_main_hwmod,
 130         .clk            = "core_l3_ck",
 131         .user           = OCP_USER_MPU,
 132 };
 133
 134 /* I2C IP block address space length (in bytes) */
 135 #define OMAP2_I2C_AS_LEN                128
 136
 137 /* L4 CORE -> I2C1 interface */
 138 static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
 139         {
 140                 .pa_start       = 0x48070000,
 141                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 142                 .flags          = ADDR_TYPE_RT,
 143         },
 144         { }
 145 };
 146
 147 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 148         .master         = &omap2430_l4_core_hwmod,
 149         .slave          = &omap2430_i2c1_hwmod,
 150         .clk            = "i2c1_ick",
 151         .addr           = omap2430_i2c1_addr_space,
 152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 153 };
 154
 155 /* L4 CORE -> I2C2 interface */
 156 static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
 157         {
 158                 .pa_start       = 0x48072000,
 159                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 160                 .flags          = ADDR_TYPE_RT,
 161         },
 162         { }
 163 };
 164
 165 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 166         .master         = &omap2430_l4_core_hwmod,
 167         .slave          = &omap2430_i2c2_hwmod,
 168         .clk            = "i2c2_ick",
 169         .addr           = omap2430_i2c2_addr_space,
 170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 171 };
 172
 173 /* L4_CORE -> L4_WKUP interface */
 174 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 175         .master = &omap2430_l4_core_hwmod,
 176         .slave  = &omap2430_l4_wkup_hwmod,
 177         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 178 };
 179
 180 /* L4 CORE -> UART1 interface */
 181 static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
 182         {
 183                 .pa_start       = OMAP2_UART1_BASE,
 184                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
 185                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 186         },
 187         { }
 188 };
 189
 190 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 191         .master         = &omap2430_l4_core_hwmod,
 192         .slave          = &omap2430_uart1_hwmod,
 193         .clk            = "uart1_ick",
 194         .addr           = omap2430_uart1_addr_space,
 195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 196 };
 197
 198 /* L4 CORE -> UART2 interface */
 199 static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
 200         {
 201                 .pa_start       = OMAP2_UART2_BASE,
 202                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 203                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 204         },
 205         { }
 206 };
 207
 208 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 209         .master         = &omap2430_l4_core_hwmod,
 210         .slave          = &omap2430_uart2_hwmod,
 211         .clk            = "uart2_ick",
 212         .addr           = omap2430_uart2_addr_space,
 213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 214 };
 215
 216 /* L4 PER -> UART3 interface */
 217 static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
 218         {
 219                 .pa_start       = OMAP2_UART3_BASE,
 220                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 221                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 222         },
 223         { }
 224 };
 225
 226 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 227         .master         = &omap2430_l4_core_hwmod,
 228         .slave          = &omap2430_uart3_hwmod,
 229         .clk            = "uart3_ick",
 230         .addr           = omap2430_uart3_addr_space,
 231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 232 };
 233
 234 /*
 235 * usbhsotg interface data
 236 */
 237 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 238         {
 239                 .pa_start       = OMAP243X_HS_BASE,
 240                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 241                 .flags          = ADDR_TYPE_RT
 242         },
 243 };
 244
 245 /*  l4_core ->usbhsotg  interface */
 246 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 247         .master         = &omap2430_l4_core_hwmod,
 248         .slave          = &omap2430_usbhsotg_hwmod,
 249         .clk            = "usb_l4_ick",
 250         .addr           = omap2430_usbhsotg_addrs,
 251         .user           = OCP_USER_MPU,
 252 };
 253
 254 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
 255         &omap2430_usbhsotg__l3,
 256 };
 257
 258 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 259         &omap2430_l4_core__usbhsotg,
 260 };
 261
 262 /* L4 CORE -> MMC1 interface */
 263 static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
 264         {
 265                 .pa_start       = 0x4809c000,
 266                 .pa_end         = 0x4809c1ff,
 267                 .flags          = ADDR_TYPE_RT,
 268         },
 269         { }
 270 };
 271
 272 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
 273         .master         = &omap2430_l4_core_hwmod,
 274         .slave          = &omap2430_mmc1_hwmod,
 275         .clk            = "mmchs1_ick",
 276         .addr           = omap2430_mmc1_addr_space,
 277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 278 };
 279
 280 /* L4 CORE -> MMC2 interface */
 281 static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
 282         {
 283                 .pa_start       = 0x480b4000,
 284                 .pa_end         = 0x480b41ff,
 285                 .flags          = ADDR_TYPE_RT,
 286         },
 287         { }
 288 };
 289
 290 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 291         .master         = &omap2430_l4_core_hwmod,
 292         .slave          = &omap2430_mmc2_hwmod,
 293         .clk            = "mmchs2_ick",
 294         .addr           = omap2430_mmc2_addr_space,
 295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 296 };
 297
 298 /* Slave interfaces on the L4_CORE interconnect */
 299 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 300         &omap2430_l3_main__l4_core,
 301 };
 302
 303 /* Master interfaces on the L4_CORE interconnect */
 304 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 305         &omap2430_l4_core__l4_wkup,
 306         &omap2430_l4_core__mmc1,
 307         &omap2430_l4_core__mmc2,
 308 };
 309
 310 /* L4 CORE */
 311 static struct omap_hwmod omap2430_l4_core_hwmod = {
 312         .name           = "l4_core",
 313         .class          = &l4_hwmod_class,
 314         .masters        = omap2430_l4_core_masters,
 315         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 316         .slaves         = omap2430_l4_core_slaves,
 317         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 318         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 319         .flags          = HWMOD_NO_IDLEST,
 320 };
 321
 322 /* Slave interfaces on the L4_WKUP interconnect */
 323 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 324         &omap2430_l4_core__l4_wkup,
 325         &omap2_l4_core__uart1,
 326         &omap2_l4_core__uart2,
 327         &omap2_l4_core__uart3,
 328 };
 329
 330 /* Master interfaces on the L4_WKUP interconnect */
 331 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 332 };
 333
 334 /* l4 core -> mcspi1 interface */
 335 static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
 336         {
 337                 .pa_start       = 0x48098000,
 338                 .pa_end         = 0x480980ff,
 339                 .flags          = ADDR_TYPE_RT,
 340         },
 341         { }
 342 };
 343
 344 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 345         .master         = &omap2430_l4_core_hwmod,
 346         .slave          = &omap2430_mcspi1_hwmod,
 347         .clk            = "mcspi1_ick",
 348         .addr           = omap2430_mcspi1_addr_space,
 349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 350 };
 351
 352 /* l4 core -> mcspi2 interface */
 353 static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
 354         {
 355                 .pa_start       = 0x4809a000,
 356                 .pa_end         = 0x4809a0ff,
 357                 .flags          = ADDR_TYPE_RT,
 358         },
 359         { }
 360 };
 361
 362 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 363         .master         = &omap2430_l4_core_hwmod,
 364         .slave          = &omap2430_mcspi2_hwmod,
 365         .clk            = "mcspi2_ick",
 366         .addr           = omap2430_mcspi2_addr_space,
 367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 368 };
 369
 370 /* l4 core -> mcspi3 interface */
 371 static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
 372         {
 373                 .pa_start       = 0x480b8000,
 374                 .pa_end         = 0x480b80ff,
 375                 .flags          = ADDR_TYPE_RT,
 376         },
 377         { }
 378 };
 379
 380 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 381         .master         = &omap2430_l4_core_hwmod,
 382         .slave          = &omap2430_mcspi3_hwmod,
 383         .clk            = "mcspi3_ick",
 384         .addr           = omap2430_mcspi3_addr_space,
 385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 386 };
 387
 388 /* L4 WKUP */
 389 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 390         .name           = "l4_wkup",
 391         .class          = &l4_hwmod_class,
 392         .masters        = omap2430_l4_wkup_masters,
 393         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 394         .slaves         = omap2430_l4_wkup_slaves,
 395         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 396         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 397         .flags          = HWMOD_NO_IDLEST,
 398 };
 399
 400 /* Master interfaces on the MPU device */
 401 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 402         &omap2430_mpu__l3_main,
 403 };
 404
 405 /* MPU */
 406 static struct omap_hwmod omap2430_mpu_hwmod = {
 407         .name           = "mpu",
 408         .class          = &mpu_hwmod_class,
 409         .main_clk       = "mpu_ck",
 410         .masters        = omap2430_mpu_masters,
 411         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 412         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 413 };
 414
 415 /*
 416  * IVA2_1 interface data
 417  */
 418
 419 /* IVA2 <- L3 interface */
 420 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 421         .master         = &omap2430_l3_main_hwmod,
 422         .slave          = &omap2430_iva_hwmod,
 423         .clk            = "dsp_fck",
 424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 425 };
 426
 427 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 428         &omap2430_l3__iva,
 429 };
 430
 431 /*
 432  * IVA2 (IVA2)
 433  */
 434
 435 static struct omap_hwmod omap2430_iva_hwmod = {
 436         .name           = "iva",
 437         .class          = &iva_hwmod_class,
 438         .masters        = omap2430_iva_masters,
 439         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 440         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 441 };
 442
 443 /* Timer Common */
 444 static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
 445         .rev_offs       = 0x0000,
 446         .sysc_offs      = 0x0010,
 447         .syss_offs      = 0x0014,
 448         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 449                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 450                            SYSC_HAS_AUTOIDLE),
 451         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 452         .sysc_fields    = &omap_hwmod_sysc_type1,
 453 };
 454
 455 static struct omap_hwmod_class omap2430_timer_hwmod_class = {
 456         .name = "timer",
 457         .sysc = &omap2430_timer_sysc,
 458         .rev = OMAP_TIMER_IP_VERSION_1,
 459 };
 460
 461 /* timer1 */
 462 static struct omap_hwmod omap2430_timer1_hwmod;
 463 static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
 464         { .irq = 37, },
 465 };
 466
 467 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 468         {
 469                 .pa_start       = 0x49018000,
 470                 .pa_end         = 0x49018000 + SZ_1K - 1,
 471                 .flags          = ADDR_TYPE_RT
 472         },
 473         { }
 474 };
 475
 476 /* l4_wkup -> timer1 */
 477 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 478         .master         = &omap2430_l4_wkup_hwmod,
 479         .slave          = &omap2430_timer1_hwmod,
 480         .clk            = "gpt1_ick",
 481         .addr           = omap2430_timer1_addrs,
 482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 483 };
 484
 485 /* timer1 slave port */
 486 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 487         &omap2430_l4_wkup__timer1,
 488 };
 489
 490 /* timer1 hwmod */
 491 static struct omap_hwmod omap2430_timer1_hwmod = {
 492         .name           = "timer1",
 493         .mpu_irqs       = omap2430_timer1_mpu_irqs,
 494         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
 495         .main_clk       = "gpt1_fck",
 496         .prcm           = {
 497                 .omap2 = {
 498                         .prcm_reg_id = 1,
 499                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 500                         .module_offs = WKUP_MOD,
 501                         .idlest_reg_id = 1,
 502                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 503                 },
 504         },
 505         .slaves         = omap2430_timer1_slaves,
 506         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
 507         .class          = &omap2430_timer_hwmod_class,
 508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 509 };
 510
 511 /* timer2 */
 512 static struct omap_hwmod omap2430_timer2_hwmod;
 513 static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
 514         { .irq = 38, },
 515 };
 516
 517 static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
 518         {
 519                 .pa_start       = 0x4802a000,
 520                 .pa_end         = 0x4802a000 + SZ_1K - 1,
 521                 .flags          = ADDR_TYPE_RT
 522         },
 523         { }
 524 };
 525
 526 /* l4_core -> timer2 */
 527 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 528         .master         = &omap2430_l4_core_hwmod,
 529         .slave          = &omap2430_timer2_hwmod,
 530         .clk            = "gpt2_ick",
 531         .addr           = omap2430_timer2_addrs,
 532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 533 };
 534
 535 /* timer2 slave port */
 536 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 537         &omap2430_l4_core__timer2,
 538 };
 539
 540 /* timer2 hwmod */
 541 static struct omap_hwmod omap2430_timer2_hwmod = {
 542         .name           = "timer2",
 543         .mpu_irqs       = omap2430_timer2_mpu_irqs,
 544         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
 545         .main_clk       = "gpt2_fck",
 546         .prcm           = {
 547                 .omap2 = {
 548                         .prcm_reg_id = 1,
 549                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 550                         .module_offs = CORE_MOD,
 551                         .idlest_reg_id = 1,
 552                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 553                 },
 554         },
 555         .slaves         = omap2430_timer2_slaves,
 556         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
 557         .class          = &omap2430_timer_hwmod_class,
 558         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 559 };
 560
 561 /* timer3 */
 562 static struct omap_hwmod omap2430_timer3_hwmod;
 563 static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
 564         { .irq = 39, },
 565 };
 566
 567 static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
 568         {
 569                 .pa_start       = 0x48078000,
 570                 .pa_end         = 0x48078000 + SZ_1K - 1,
 571                 .flags          = ADDR_TYPE_RT
 572         },
 573         { }
 574 };
 575
 576 /* l4_core -> timer3 */
 577 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 578         .master         = &omap2430_l4_core_hwmod,
 579         .slave          = &omap2430_timer3_hwmod,
 580         .clk            = "gpt3_ick",
 581         .addr           = omap2430_timer3_addrs,
 582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 583 };
 584
 585 /* timer3 slave port */
 586 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 587         &omap2430_l4_core__timer3,
 588 };
 589
 590 /* timer3 hwmod */
 591 static struct omap_hwmod omap2430_timer3_hwmod = {
 592         .name           = "timer3",
 593         .mpu_irqs       = omap2430_timer3_mpu_irqs,
 594         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
 595         .main_clk       = "gpt3_fck",
 596         .prcm           = {
 597                 .omap2 = {
 598                         .prcm_reg_id = 1,
 599                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 600                         .module_offs = CORE_MOD,
 601                         .idlest_reg_id = 1,
 602                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 603                 },
 604         },
 605         .slaves         = omap2430_timer3_slaves,
 606         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
 607         .class          = &omap2430_timer_hwmod_class,
 608         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 609 };
 610
 611 /* timer4 */
 612 static struct omap_hwmod omap2430_timer4_hwmod;
 613 static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
 614         { .irq = 40, },
 615 };
 616
 617 static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
 618         {
 619                 .pa_start       = 0x4807a000,
 620                 .pa_end         = 0x4807a000 + SZ_1K - 1,
 621                 .flags          = ADDR_TYPE_RT
 622         },
 623         { }
 624 };
 625
 626 /* l4_core -> timer4 */
 627 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 628         .master         = &omap2430_l4_core_hwmod,
 629         .slave          = &omap2430_timer4_hwmod,
 630         .clk            = "gpt4_ick",
 631         .addr           = omap2430_timer4_addrs,
 632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 633 };
 634
 635 /* timer4 slave port */
 636 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 637         &omap2430_l4_core__timer4,
 638 };
 639
 640 /* timer4 hwmod */
 641 static struct omap_hwmod omap2430_timer4_hwmod = {
 642         .name           = "timer4",
 643         .mpu_irqs       = omap2430_timer4_mpu_irqs,
 644         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
 645         .main_clk       = "gpt4_fck",
 646         .prcm           = {
 647                 .omap2 = {
 648                         .prcm_reg_id = 1,
 649                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 650                         .module_offs = CORE_MOD,
 651                         .idlest_reg_id = 1,
 652                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 653                 },
 654         },
 655         .slaves         = omap2430_timer4_slaves,
 656         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
 657         .class          = &omap2430_timer_hwmod_class,
 658         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 659 };
 660
 661 /* timer5 */
 662 static struct omap_hwmod omap2430_timer5_hwmod;
 663 static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
 664         { .irq = 41, },
 665 };
 666
 667 static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
 668         {
 669                 .pa_start       = 0x4807c000,
 670                 .pa_end         = 0x4807c000 + SZ_1K - 1,
 671                 .flags          = ADDR_TYPE_RT
 672         },
 673         { }
 674 };
 675
 676 /* l4_core -> timer5 */
 677 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 678         .master         = &omap2430_l4_core_hwmod,
 679         .slave          = &omap2430_timer5_hwmod,
 680         .clk            = "gpt5_ick",
 681         .addr           = omap2430_timer5_addrs,
 682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 683 };
 684
 685 /* timer5 slave port */
 686 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 687         &omap2430_l4_core__timer5,
 688 };
 689
 690 /* timer5 hwmod */
 691 static struct omap_hwmod omap2430_timer5_hwmod = {
 692         .name           = "timer5",
 693         .mpu_irqs       = omap2430_timer5_mpu_irqs,
 694         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
 695         .main_clk       = "gpt5_fck",
 696         .prcm           = {
 697                 .omap2 = {
 698                         .prcm_reg_id = 1,
 699                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 700                         .module_offs = CORE_MOD,
 701                         .idlest_reg_id = 1,
 702                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 703                 },
 704         },
 705         .slaves         = omap2430_timer5_slaves,
 706         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
 707         .class          = &omap2430_timer_hwmod_class,
 708         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 709 };
 710
 711 /* timer6 */
 712 static struct omap_hwmod omap2430_timer6_hwmod;
 713 static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
 714         { .irq = 42, },
 715 };
 716
 717 static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
 718         {
 719                 .pa_start       = 0x4807e000,
 720                 .pa_end         = 0x4807e000 + SZ_1K - 1,
 721                 .flags          = ADDR_TYPE_RT
 722         },
 723         { }
 724 };
 725
 726 /* l4_core -> timer6 */
 727 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 728         .master         = &omap2430_l4_core_hwmod,
 729         .slave          = &omap2430_timer6_hwmod,
 730         .clk            = "gpt6_ick",
 731         .addr           = omap2430_timer6_addrs,
 732         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 733 };
 734
 735 /* timer6 slave port */
 736 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 737         &omap2430_l4_core__timer6,
 738 };
 739
 740 /* timer6 hwmod */
 741 static struct omap_hwmod omap2430_timer6_hwmod = {
 742         .name           = "timer6",
 743         .mpu_irqs       = omap2430_timer6_mpu_irqs,
 744         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
 745         .main_clk       = "gpt6_fck",
 746         .prcm           = {
 747                 .omap2 = {
 748                         .prcm_reg_id = 1,
 749                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 750                         .module_offs = CORE_MOD,
 751                         .idlest_reg_id = 1,
 752                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 753                 },
 754         },
 755         .slaves         = omap2430_timer6_slaves,
 756         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
 757         .class          = &omap2430_timer_hwmod_class,
 758         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 759 };
 760
 761 /* timer7 */
 762 static struct omap_hwmod omap2430_timer7_hwmod;
 763 static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
 764         { .irq = 43, },
 765 };
 766
 767 static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
 768         {
 769                 .pa_start       = 0x48080000,
 770                 .pa_end         = 0x48080000 + SZ_1K - 1,
 771                 .flags          = ADDR_TYPE_RT
 772         },
 773         { }
 774 };
 775
 776 /* l4_core -> timer7 */
 777 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 778         .master         = &omap2430_l4_core_hwmod,
 779         .slave          = &omap2430_timer7_hwmod,
 780         .clk            = "gpt7_ick",
 781         .addr           = omap2430_timer7_addrs,
 782         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 783 };
 784
 785 /* timer7 slave port */
 786 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 787         &omap2430_l4_core__timer7,
 788 };
 789
 790 /* timer7 hwmod */
 791 static struct omap_hwmod omap2430_timer7_hwmod = {
 792         .name           = "timer7",
 793         .mpu_irqs       = omap2430_timer7_mpu_irqs,
 794         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
 795         .main_clk       = "gpt7_fck",
 796         .prcm           = {
 797                 .omap2 = {
 798                         .prcm_reg_id = 1,
 799                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 800                         .module_offs = CORE_MOD,
 801                         .idlest_reg_id = 1,
 802                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 803                 },
 804         },
 805         .slaves         = omap2430_timer7_slaves,
 806         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
 807         .class          = &omap2430_timer_hwmod_class,
 808         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 809 };
 810
 811 /* timer8 */
 812 static struct omap_hwmod omap2430_timer8_hwmod;
 813 static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
 814         { .irq = 44, },
 815 };
 816
 817 static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
 818         {
 819                 .pa_start       = 0x48082000,
 820                 .pa_end         = 0x48082000 + SZ_1K - 1,
 821                 .flags          = ADDR_TYPE_RT
 822         },
 823         { }
 824 };
 825
 826 /* l4_core -> timer8 */
 827 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 828         .master         = &omap2430_l4_core_hwmod,
 829         .slave          = &omap2430_timer8_hwmod,
 830         .clk            = "gpt8_ick",
 831         .addr           = omap2430_timer8_addrs,
 832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 833 };
 834
 835 /* timer8 slave port */
 836 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 837         &omap2430_l4_core__timer8,
 838 };
 839
 840 /* timer8 hwmod */
 841 static struct omap_hwmod omap2430_timer8_hwmod = {
 842         .name           = "timer8",
 843         .mpu_irqs       = omap2430_timer8_mpu_irqs,
 844         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
 845         .main_clk       = "gpt8_fck",
 846         .prcm           = {
 847                 .omap2 = {
 848                         .prcm_reg_id = 1,
 849                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 850                         .module_offs = CORE_MOD,
 851                         .idlest_reg_id = 1,
 852                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 853                 },
 854         },
 855         .slaves         = omap2430_timer8_slaves,
 856         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
 857         .class          = &omap2430_timer_hwmod_class,
 858         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 859 };
 860
 861 /* timer9 */
 862 static struct omap_hwmod omap2430_timer9_hwmod;
 863 static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
 864         { .irq = 45, },
 865 };
 866
 867 static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
 868         {
 869                 .pa_start       = 0x48084000,
 870                 .pa_end         = 0x48084000 + SZ_1K - 1,
 871                 .flags          = ADDR_TYPE_RT
 872         },
 873         { }
 874 };
 875
 876 /* l4_core -> timer9 */
 877 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 878         .master         = &omap2430_l4_core_hwmod,
 879         .slave          = &omap2430_timer9_hwmod,
 880         .clk            = "gpt9_ick",
 881         .addr           = omap2430_timer9_addrs,
 882         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 883 };
 884
 885 /* timer9 slave port */
 886 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 887         &omap2430_l4_core__timer9,
 888 };
 889
 890 /* timer9 hwmod */
 891 static struct omap_hwmod omap2430_timer9_hwmod = {
 892         .name           = "timer9",
 893         .mpu_irqs       = omap2430_timer9_mpu_irqs,
 894         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
 895         .main_clk       = "gpt9_fck",
 896         .prcm           = {
 897                 .omap2 = {
 898                         .prcm_reg_id = 1,
 899                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 900                         .module_offs = CORE_MOD,
 901                         .idlest_reg_id = 1,
 902                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 903                 },
 904         },
 905         .slaves         = omap2430_timer9_slaves,
 906         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
 907         .class          = &omap2430_timer_hwmod_class,
 908         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 909 };
 910
 911 /* timer10 */
 912 static struct omap_hwmod omap2430_timer10_hwmod;
 913 static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
 914         { .irq = 46, },
 915 };
 916
 917 static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
 918         {
 919                 .pa_start       = 0x48086000,
 920                 .pa_end         = 0x48086000 + SZ_1K - 1,
 921                 .flags          = ADDR_TYPE_RT
 922         },
 923         { }
 924 };
 925
 926 /* l4_core -> timer10 */
 927 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 928         .master         = &omap2430_l4_core_hwmod,
 929         .slave          = &omap2430_timer10_hwmod,
 930         .clk            = "gpt10_ick",
 931         .addr           = omap2430_timer10_addrs,
 932         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 933 };
 934
 935 /* timer10 slave port */
 936 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 937         &omap2430_l4_core__timer10,
 938 };
 939
 940 /* timer10 hwmod */
 941 static struct omap_hwmod omap2430_timer10_hwmod = {
 942         .name           = "timer10",
 943         .mpu_irqs       = omap2430_timer10_mpu_irqs,
 944         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
 945         .main_clk       = "gpt10_fck",
 946         .prcm           = {
 947                 .omap2 = {
 948                         .prcm_reg_id = 1,
 949                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 950                         .module_offs = CORE_MOD,
 951                         .idlest_reg_id = 1,
 952                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 953                 },
 954         },
 955         .slaves         = omap2430_timer10_slaves,
 956         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
 957         .class          = &omap2430_timer_hwmod_class,
 958         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 959 };
 960
 961 /* timer11 */
 962 static struct omap_hwmod omap2430_timer11_hwmod;
 963 static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
 964         { .irq = 47, },
 965 };
 966
 967 static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
 968         {
 969                 .pa_start       = 0x48088000,
 970                 .pa_end         = 0x48088000 + SZ_1K - 1,
 971                 .flags          = ADDR_TYPE_RT
 972         },
 973         { }
 974 };
 975
 976 /* l4_core -> timer11 */
 977 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 978         .master         = &omap2430_l4_core_hwmod,
 979         .slave          = &omap2430_timer11_hwmod,
 980         .clk            = "gpt11_ick",
 981         .addr           = omap2430_timer11_addrs,
 982         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 983 };
 984
 985 /* timer11 slave port */
 986 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 987         &omap2430_l4_core__timer11,
 988 };
 989
 990 /* timer11 hwmod */
 991 static struct omap_hwmod omap2430_timer11_hwmod = {
 992         .name           = "timer11",
 993         .mpu_irqs       = omap2430_timer11_mpu_irqs,
 994         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
 995         .main_clk       = "gpt11_fck",
 996         .prcm           = {
 997                 .omap2 = {
 998                         .prcm_reg_id = 1,
 999                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
1000                         .module_offs = CORE_MOD,
1001                         .idlest_reg_id = 1,
1002                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
1003                 },
1004         },
1005         .slaves         = omap2430_timer11_slaves,
1006         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
1007         .class          = &omap2430_timer_hwmod_class,
1008         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1009 };
1010
1011 /* timer12 */
1012 static struct omap_hwmod omap2430_timer12_hwmod;
1013 static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
1014         { .irq = 48, },
1015 };
1016
1017 static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
1018         {
1019                 .pa_start       = 0x4808a000,
1020                 .pa_end         = 0x4808a000 + SZ_1K - 1,
1021                 .flags          = ADDR_TYPE_RT
1022         },
1023         { }
1024 };
1025
1026 /* l4_core -> timer12 */
1027 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
1028         .master         = &omap2430_l4_core_hwmod,
1029         .slave          = &omap2430_timer12_hwmod,
1030         .clk            = "gpt12_ick",
1031         .addr           = omap2430_timer12_addrs,
1032         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1033 };
1034
1035 /* timer12 slave port */
1036 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
1037         &omap2430_l4_core__timer12,
1038 };
1039
1040 /* timer12 hwmod */
1041 static struct omap_hwmod omap2430_timer12_hwmod = {
1042         .name           = "timer12",
1043         .mpu_irqs       = omap2430_timer12_mpu_irqs,
1044         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
1045         .main_clk       = "gpt12_fck",
1046         .prcm           = {
1047                 .omap2 = {
1048                         .prcm_reg_id = 1,
1049                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
1050                         .module_offs = CORE_MOD,
1051                         .idlest_reg_id = 1,
1052                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
1053                 },
1054         },
1055         .slaves         = omap2430_timer12_slaves,
1056         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
1057         .class          = &omap2430_timer_hwmod_class,
1058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1059 };
1060
1061 /* l4_wkup -> wd_timer2 */
1062 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
1063         {
1064                 .pa_start       = 0x49016000,
1065                 .pa_end         = 0x4901607f,
1066                 .flags          = ADDR_TYPE_RT
1067         },
1068         { }
1069 };
1070
1071 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
1072         .master         = &omap2430_l4_wkup_hwmod,
1073         .slave          = &omap2430_wd_timer2_hwmod,
1074         .clk            = "mpu_wdt_ick",
1075         .addr           = omap2430_wd_timer2_addrs,
1076         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1077 };
1078
1079 /*
1080  * 'wd_timer' class
1081  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1082  * overflow condition
1083  */
1084
1085 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
1086         .rev_offs       = 0x0,
1087         .sysc_offs      = 0x0010,
1088         .syss_offs      = 0x0014,
1089         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
1090                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1091         .sysc_fields    = &omap_hwmod_sysc_type1,
1092 };
1093
1094 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
1095         .name           = "wd_timer",
1096         .sysc           = &omap2430_wd_timer_sysc,
1097         .pre_shutdown   = &omap2_wd_timer_disable
1098 };
1099
1100 /* wd_timer2 */
1101 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
1102         &omap2430_l4_wkup__wd_timer2,
1103 };
1104
1105 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
1106         .name           = "wd_timer2",
1107         .class          = &omap2430_wd_timer_hwmod_class,
1108         .main_clk       = "mpu_wdt_fck",
1109         .prcm           = {
1110                 .omap2 = {
1111                         .prcm_reg_id = 1,
1112                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1113                         .module_offs = WKUP_MOD,
1114                         .idlest_reg_id = 1,
1115                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
1116                 },
1117         },
1118         .slaves         = omap2430_wd_timer2_slaves,
1119         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
1120         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1121 };
1122
1123 /* UART */
1124
1125 static struct omap_hwmod_class_sysconfig uart_sysc = {
1126         .rev_offs       = 0x50,
1127         .sysc_offs      = 0x54,
1128         .syss_offs      = 0x58,
1129         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1130                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1131                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1132         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1133         .sysc_fields    = &omap_hwmod_sysc_type1,
1134 };
1135
1136 static struct omap_hwmod_class uart_class = {
1137         .name = "uart",
1138         .sysc = &uart_sysc,
1139 };
1140
1141 /* UART1 */
1142
1143 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1144         { .irq = INT_24XX_UART1_IRQ, },
1145 };
1146
1147 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1148         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1149         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1150 };
1151
1152 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
1153         &omap2_l4_core__uart1,
1154 };
1155
1156 static struct omap_hwmod omap2430_uart1_hwmod = {
1157         .name           = "uart1",
1158         .mpu_irqs       = uart1_mpu_irqs,
1159         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1160         .sdma_reqs      = uart1_sdma_reqs,
1161         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1162         .main_clk       = "uart1_fck",
1163         .prcm           = {
1164                 .omap2 = {
1165                         .module_offs = CORE_MOD,
1166                         .prcm_reg_id = 1,
1167                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
1168                         .idlest_reg_id = 1,
1169                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
1170                 },
1171         },
1172         .slaves         = omap2430_uart1_slaves,
1173         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
1174         .class          = &uart_class,
1175         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1176 };
1177
1178 /* UART2 */
1179
1180 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1181         { .irq = INT_24XX_UART2_IRQ, },
1182 };
1183
1184 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1185         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1186         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1187 };
1188
1189 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
1190         &omap2_l4_core__uart2,
1191 };
1192
1193 static struct omap_hwmod omap2430_uart2_hwmod = {
1194         .name           = "uart2",
1195         .mpu_irqs       = uart2_mpu_irqs,
1196         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1197         .sdma_reqs      = uart2_sdma_reqs,
1198         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1199         .main_clk       = "uart2_fck",
1200         .prcm           = {
1201                 .omap2 = {
1202                         .module_offs = CORE_MOD,
1203                         .prcm_reg_id = 1,
1204                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
1205                         .idlest_reg_id = 1,
1206                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
1207                 },
1208         },
1209         .slaves         = omap2430_uart2_slaves,
1210         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
1211         .class          = &uart_class,
1212         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1213 };
1214
1215 /* UART3 */
1216
1217 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1218         { .irq = INT_24XX_UART3_IRQ, },
1219 };
1220
1221 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1222         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1223         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1224 };
1225
1226 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
1227         &omap2_l4_core__uart3,
1228 };
1229
1230 static struct omap_hwmod omap2430_uart3_hwmod = {
1231         .name           = "uart3",
1232         .mpu_irqs       = uart3_mpu_irqs,
1233         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1234         .sdma_reqs      = uart3_sdma_reqs,
1235         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1236         .main_clk       = "uart3_fck",
1237         .prcm           = {
1238                 .omap2 = {
1239                         .module_offs = CORE_MOD,
1240                         .prcm_reg_id = 2,
1241                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
1242                         .idlest_reg_id = 2,
1243                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
1244                 },
1245         },
1246         .slaves         = omap2430_uart3_slaves,
1247         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
1248         .class          = &uart_class,
1249         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1250 };
1251
1252 /*
1253  * 'dss' class
1254  * display sub-system
1255  */
1256
1257 static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
1258         .rev_offs       = 0x0000,
1259         .sysc_offs      = 0x0010,
1260         .syss_offs      = 0x0014,
1261         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1262         .sysc_fields    = &omap_hwmod_sysc_type1,
1263 };
1264
1265 static struct omap_hwmod_class omap2430_dss_hwmod_class = {
1266         .name = "dss",
1267         .sysc = &omap2430_dss_sysc,
1268 };
1269
1270 static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
1271         { .name = "dispc", .dma_req = 5 },
1272 };
1273
1274 /* dss */
1275 /* dss master ports */
1276 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
1277         &omap2430_dss__l3,
1278 };
1279
1280 static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
1281         {
1282                 .pa_start       = 0x48050000,
1283                 .pa_end         = 0x480503FF,
1284                 .flags          = ADDR_TYPE_RT
1285         },
1286         { }
1287 };
1288
1289 /* l4_core -> dss */
1290 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
1291         .master         = &omap2430_l4_core_hwmod,
1292         .slave          = &omap2430_dss_core_hwmod,
1293         .clk            = "dss_ick",
1294         .addr           = omap2430_dss_addrs,
1295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1296 };
1297
1298 /* dss slave ports */
1299 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
1300         &omap2430_l4_core__dss,
1301 };
1302
1303 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1304         { .role = "tv_clk", .clk = "dss_54m_fck" },
1305         { .role = "sys_clk", .clk = "dss2_fck" },
1306 };
1307
1308 static struct omap_hwmod omap2430_dss_core_hwmod = {
1309         .name           = "dss_core",
1310         .class          = &omap2430_dss_hwmod_class,
1311         .main_clk       = "dss1_fck", /* instead of dss_fck */
1312         .sdma_reqs      = omap2430_dss_sdma_chs,
1313         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
1314         .prcm           = {
1315                 .omap2 = {
1316                         .prcm_reg_id = 1,
1317                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1318                         .module_offs = CORE_MOD,
1319                         .idlest_reg_id = 1,
1320                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1321                 },
1322         },
1323         .opt_clks       = dss_opt_clks,
1324         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1325         .slaves         = omap2430_dss_slaves,
1326         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
1327         .masters        = omap2430_dss_masters,
1328         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
1329         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1330         .flags          = HWMOD_NO_IDLEST,
1331 };
1332
1333 /*
1334  * 'dispc' class
1335  * display controller
1336  */
1337
1338 static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1339         .rev_offs       = 0x0000,
1340         .sysc_offs      = 0x0010,
1341         .syss_offs      = 0x0014,
1342         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1343                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1344         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1345                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1346         .sysc_fields    = &omap_hwmod_sysc_type1,
1347 };
1348
1349 static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1350         .name = "dispc",
1351         .sysc = &omap2430_dispc_sysc,
1352 };
1353
1354 static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
1355         { .irq = 25 },
1356 };
1357
1358 static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
1359         {
1360                 .pa_start       = 0x48050400,
1361                 .pa_end         = 0x480507FF,
1362                 .flags          = ADDR_TYPE_RT
1363         },
1364         { }
1365 };
1366
1367 /* l4_core -> dss_dispc */
1368 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1369         .master         = &omap2430_l4_core_hwmod,
1370         .slave          = &omap2430_dss_dispc_hwmod,
1371         .clk            = "dss_ick",
1372         .addr           = omap2430_dss_dispc_addrs,
1373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1374 };
1375
1376 /* dss_dispc slave ports */
1377 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1378         &omap2430_l4_core__dss_dispc,
1379 };
1380
1381 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1382         .name           = "dss_dispc",
1383         .class          = &omap2430_dispc_hwmod_class,
1384         .mpu_irqs       = omap2430_dispc_irqs,
1385         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dispc_irqs),
1386         .main_clk       = "dss1_fck",
1387         .prcm           = {
1388                 .omap2 = {
1389                         .prcm_reg_id = 1,
1390                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1391                         .module_offs = CORE_MOD,
1392                         .idlest_reg_id = 1,
1393                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1394                 },
1395         },
1396         .slaves         = omap2430_dss_dispc_slaves,
1397         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1398         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1399         .flags          = HWMOD_NO_IDLEST,
1400 };
1401
1402 /*
1403  * 'rfbi' class
1404  * remote frame buffer interface
1405  */
1406
1407 static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1408         .rev_offs       = 0x0000,
1409         .sysc_offs      = 0x0010,
1410         .syss_offs      = 0x0014,
1411         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1412                            SYSC_HAS_AUTOIDLE),
1413         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1414         .sysc_fields    = &omap_hwmod_sysc_type1,
1415 };
1416
1417 static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1418         .name = "rfbi",
1419         .sysc = &omap2430_rfbi_sysc,
1420 };
1421
1422 static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
1423         {
1424                 .pa_start       = 0x48050800,
1425                 .pa_end         = 0x48050BFF,
1426                 .flags          = ADDR_TYPE_RT
1427         },
1428         { }
1429 };
1430
1431 /* l4_core -> dss_rfbi */
1432 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1433         .master         = &omap2430_l4_core_hwmod,
1434         .slave          = &omap2430_dss_rfbi_hwmod,
1435         .clk            = "dss_ick",
1436         .addr           = omap2430_dss_rfbi_addrs,
1437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1438 };
1439
1440 /* dss_rfbi slave ports */
1441 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1442         &omap2430_l4_core__dss_rfbi,
1443 };
1444
1445 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1446         .name           = "dss_rfbi",
1447         .class          = &omap2430_rfbi_hwmod_class,
1448         .main_clk       = "dss1_fck",
1449         .prcm           = {
1450                 .omap2 = {
1451                         .prcm_reg_id = 1,
1452                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1453                         .module_offs = CORE_MOD,
1454                 },
1455         },
1456         .slaves         = omap2430_dss_rfbi_slaves,
1457         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1458         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1459         .flags          = HWMOD_NO_IDLEST,
1460 };
1461
1462 /*
1463  * 'venc' class
1464  * video encoder
1465  */
1466
1467 static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1468         .name = "venc",
1469 };
1470
1471 /* dss_venc */
1472 static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
1473         {
1474                 .pa_start       = 0x48050C00,
1475                 .pa_end         = 0x48050FFF,
1476                 .flags          = ADDR_TYPE_RT
1477         },
1478         { }
1479 };
1480
1481 /* l4_core -> dss_venc */
1482 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1483         .master         = &omap2430_l4_core_hwmod,
1484         .slave          = &omap2430_dss_venc_hwmod,
1485         .clk            = "dss_54m_fck",
1486         .addr           = omap2430_dss_venc_addrs,
1487         .flags          = OCPIF_SWSUP_IDLE,
1488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1489 };
1490
1491 /* dss_venc slave ports */
1492 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1493         &omap2430_l4_core__dss_venc,
1494 };
1495
1496 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1497         .name           = "dss_venc",
1498         .class          = &omap2430_venc_hwmod_class,
1499         .main_clk       = "dss1_fck",
1500         .prcm           = {
1501                 .omap2 = {
1502                         .prcm_reg_id = 1,
1503                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1504                         .module_offs = CORE_MOD,
1505                 },
1506         },
1507         .slaves         = omap2430_dss_venc_slaves,
1508         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
1509         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1510         .flags          = HWMOD_NO_IDLEST,
1511 };
1512
1513 /* I2C common */
1514 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1515         .rev_offs       = 0x00,
1516         .sysc_offs      = 0x20,
1517         .syss_offs      = 0x10,
1518         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1519                            SYSS_HAS_RESET_STATUS),
1520         .sysc_fields    = &omap_hwmod_sysc_type1,
1521 };
1522
1523 static struct omap_hwmod_class i2c_class = {
1524         .name           = "i2c",
1525         .sysc           = &i2c_sysc,
1526 };
1527
1528 static struct omap_i2c_dev_attr i2c_dev_attr = {
1529         .fifo_depth     = 8, /* bytes */
1530 };
1531
1532 /* I2C1 */
1533
1534 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1535         { .irq = INT_24XX_I2C1_IRQ, },
1536 };
1537
1538 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1539         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1540         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1541 };
1542
1543 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1544         &omap2430_l4_core__i2c1,
1545 };
1546
1547 static struct omap_hwmod omap2430_i2c1_hwmod = {
1548         .name           = "i2c1",
1549         .mpu_irqs       = i2c1_mpu_irqs,
1550         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1551         .sdma_reqs      = i2c1_sdma_reqs,
1552         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1553         .main_clk       = "i2chs1_fck",
1554         .prcm           = {
1555                 .omap2 = {
1556                         /*
1557                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1558                          * I2CHS IP's do not follow the usual pattern.
1559                          * prcm_reg_id alone cannot be used to program
1560                          * the iclk and fclk. Needs to be handled using
1561                          * additional flags when clk handling is moved
1562                          * to hwmod framework.
1563                          */
1564                         .module_offs = CORE_MOD,
1565                         .prcm_reg_id = 1,
1566                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1567                         .idlest_reg_id = 1,
1568                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1569                 },
1570         },
1571         .slaves         = omap2430_i2c1_slaves,
1572         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
1573         .class          = &i2c_class,
1574         .dev_attr       = &i2c_dev_attr,
1575         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1576 };
1577
1578 /* I2C2 */
1579
1580 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1581         { .irq = INT_24XX_I2C2_IRQ, },
1582 };
1583
1584 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1585         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1586         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1587 };
1588
1589 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1590         &omap2430_l4_core__i2c2,
1591 };
1592
1593 static struct omap_hwmod omap2430_i2c2_hwmod = {
1594         .name           = "i2c2",
1595         .mpu_irqs       = i2c2_mpu_irqs,
1596         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1597         .sdma_reqs      = i2c2_sdma_reqs,
1598         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1599         .main_clk       = "i2chs2_fck",
1600         .prcm           = {
1601                 .omap2 = {
1602                         .module_offs = CORE_MOD,
1603                         .prcm_reg_id = 1,
1604                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1605                         .idlest_reg_id = 1,
1606                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1607                 },
1608         },
1609         .slaves         = omap2430_i2c2_slaves,
1610         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
1611         .class          = &i2c_class,
1612         .dev_attr       = &i2c_dev_attr,
1613         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1614 };
1615
1616 /* l4_wkup -> gpio1 */
1617 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1618         {
1619                 .pa_start       = 0x4900C000,
1620                 .pa_end         = 0x4900C1ff,
1621                 .flags          = ADDR_TYPE_RT
1622         },
1623         { }
1624 };
1625
1626 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1627         .master         = &omap2430_l4_wkup_hwmod,
1628         .slave          = &omap2430_gpio1_hwmod,
1629         .clk            = "gpios_ick",
1630         .addr           = omap2430_gpio1_addr_space,
1631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1632 };
1633
1634 /* l4_wkup -> gpio2 */
1635 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1636         {
1637                 .pa_start       = 0x4900E000,
1638                 .pa_end         = 0x4900E1ff,
1639                 .flags          = ADDR_TYPE_RT
1640         },
1641         { }
1642 };
1643
1644 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1645         .master         = &omap2430_l4_wkup_hwmod,
1646         .slave          = &omap2430_gpio2_hwmod,
1647         .clk            = "gpios_ick",
1648         .addr           = omap2430_gpio2_addr_space,
1649         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1650 };
1651
1652 /* l4_wkup -> gpio3 */
1653 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1654         {
1655                 .pa_start       = 0x49010000,
1656                 .pa_end         = 0x490101ff,
1657                 .flags          = ADDR_TYPE_RT
1658         },
1659         { }
1660 };
1661
1662 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1663         .master         = &omap2430_l4_wkup_hwmod,
1664         .slave          = &omap2430_gpio3_hwmod,
1665         .clk            = "gpios_ick",
1666         .addr           = omap2430_gpio3_addr_space,
1667         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1668 };
1669
1670 /* l4_wkup -> gpio4 */
1671 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1672         {
1673                 .pa_start       = 0x49012000,
1674                 .pa_end         = 0x490121ff,
1675                 .flags          = ADDR_TYPE_RT
1676         },
1677         { }
1678 };
1679
1680 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1681         .master         = &omap2430_l4_wkup_hwmod,
1682         .slave          = &omap2430_gpio4_hwmod,
1683         .clk            = "gpios_ick",
1684         .addr           = omap2430_gpio4_addr_space,
1685         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1686 };
1687
1688 /* l4_core -> gpio5 */
1689 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1690         {
1691                 .pa_start       = 0x480B6000,
1692                 .pa_end         = 0x480B61ff,
1693                 .flags          = ADDR_TYPE_RT
1694         },
1695         { }
1696 };
1697
1698 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1699         .master         = &omap2430_l4_core_hwmod,
1700         .slave          = &omap2430_gpio5_hwmod,
1701         .clk            = "gpio5_ick",
1702         .addr           = omap2430_gpio5_addr_space,
1703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1704 };
1705
1706 /* gpio dev_attr */
1707 static struct omap_gpio_dev_attr gpio_dev_attr = {
1708         .bank_width = 32,
1709         .dbck_flag = false,
1710 };
1711
1712 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1713         .rev_offs       = 0x0000,
1714         .sysc_offs      = 0x0010,
1715         .syss_offs      = 0x0014,
1716         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1717                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1718                            SYSS_HAS_RESET_STATUS),
1719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1720         .sysc_fields    = &omap_hwmod_sysc_type1,
1721 };
1722
1723 /*
1724  * 'gpio' class
1725  * general purpose io module
1726  */
1727 static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1728         .name = "gpio",
1729         .sysc = &omap243x_gpio_sysc,
1730         .rev = 0,
1731 };
1732
1733 /* gpio1 */
1734 static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
1735         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1736 };
1737
1738 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1739         &omap2430_l4_wkup__gpio1,
1740 };
1741
1742 static struct omap_hwmod omap2430_gpio1_hwmod = {
1743         .name           = "gpio1",
1744         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1745         .mpu_irqs       = omap243x_gpio1_irqs,
1746         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
1747         .main_clk       = "gpios_fck",
1748         .prcm           = {
1749                 .omap2 = {
1750                         .prcm_reg_id = 1,
1751                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1752                         .module_offs = WKUP_MOD,
1753                         .idlest_reg_id = 1,
1754                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1755                 },
1756         },
1757         .slaves         = omap2430_gpio1_slaves,
1758         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
1759         .class          = &omap243x_gpio_hwmod_class,
1760         .dev_attr       = &gpio_dev_attr,
1761         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1762 };
1763
1764 /* gpio2 */
1765 static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
1766         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1767 };
1768
1769 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1770         &omap2430_l4_wkup__gpio2,
1771 };
1772
1773 static struct omap_hwmod omap2430_gpio2_hwmod = {
1774         .name           = "gpio2",
1775         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1776         .mpu_irqs       = omap243x_gpio2_irqs,
1777         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
1778         .main_clk       = "gpios_fck",
1779         .prcm           = {
1780                 .omap2 = {
1781                         .prcm_reg_id = 1,
1782                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1783                         .module_offs = WKUP_MOD,
1784                         .idlest_reg_id = 1,
1785                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1786                 },
1787         },
1788         .slaves         = omap2430_gpio2_slaves,
1789         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
1790         .class          = &omap243x_gpio_hwmod_class,
1791         .dev_attr       = &gpio_dev_attr,
1792         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1793 };
1794
1795 /* gpio3 */
1796 static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
1797         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1798 };
1799
1800 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1801         &omap2430_l4_wkup__gpio3,
1802 };
1803
1804 static struct omap_hwmod omap2430_gpio3_hwmod = {
1805         .name           = "gpio3",
1806         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1807         .mpu_irqs       = omap243x_gpio3_irqs,
1808         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
1809         .main_clk       = "gpios_fck",
1810         .prcm           = {
1811                 .omap2 = {
1812                         .prcm_reg_id = 1,
1813                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1814                         .module_offs = WKUP_MOD,
1815                         .idlest_reg_id = 1,
1816                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1817                 },
1818         },
1819         .slaves         = omap2430_gpio3_slaves,
1820         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
1821         .class          = &omap243x_gpio_hwmod_class,
1822         .dev_attr       = &gpio_dev_attr,
1823         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1824 };
1825
1826 /* gpio4 */
1827 static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
1828         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1829 };
1830
1831 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1832         &omap2430_l4_wkup__gpio4,
1833 };
1834
1835 static struct omap_hwmod omap2430_gpio4_hwmod = {
1836         .name           = "gpio4",
1837         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1838         .mpu_irqs       = omap243x_gpio4_irqs,
1839         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
1840         .main_clk       = "gpios_fck",
1841         .prcm           = {
1842                 .omap2 = {
1843                         .prcm_reg_id = 1,
1844                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1845                         .module_offs = WKUP_MOD,
1846                         .idlest_reg_id = 1,
1847                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1848                 },
1849         },
1850         .slaves         = omap2430_gpio4_slaves,
1851         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
1852         .class          = &omap243x_gpio_hwmod_class,
1853         .dev_attr       = &gpio_dev_attr,
1854         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1855 };
1856
1857 /* gpio5 */
1858 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1859         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1860 };
1861
1862 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1863         &omap2430_l4_core__gpio5,
1864 };
1865
1866 static struct omap_hwmod omap2430_gpio5_hwmod = {
1867         .name           = "gpio5",
1868         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1869         .mpu_irqs       = omap243x_gpio5_irqs,
1870         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
1871         .main_clk       = "gpio5_fck",
1872         .prcm           = {
1873                 .omap2 = {
1874                         .prcm_reg_id = 2,
1875                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1876                         .module_offs = CORE_MOD,
1877                         .idlest_reg_id = 2,
1878                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1879                 },
1880         },
1881         .slaves         = omap2430_gpio5_slaves,
1882         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
1883         .class          = &omap243x_gpio_hwmod_class,
1884         .dev_attr       = &gpio_dev_attr,
1885         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1886 };
1887
1888 /* dma_system */
1889 static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1890         .rev_offs       = 0x0000,
1891         .sysc_offs      = 0x002c,
1892         .syss_offs      = 0x0028,
1893         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1894                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1895                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1896         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1897         .sysc_fields    = &omap_hwmod_sysc_type1,
1898 };
1899
1900 static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1901         .name = "dma",
1902         .sysc = &omap2430_dma_sysc,
1903 };
1904
1905 /* dma attributes */
1906 static struct omap_dma_dev_attr dma_dev_attr = {
1907         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1908                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1909         .lch_count = 32,
1910 };
1911
1912 static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
1913         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1914         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1915         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1916         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1917 };
1918
1919 static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
1920         {
1921                 .pa_start       = 0x48056000,
1922                 .pa_end         = 0x48056fff,
1923                 .flags          = ADDR_TYPE_RT
1924         },
1925         { }
1926 };
1927
1928 /* dma_system -> L3 */
1929 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1930         .master         = &omap2430_dma_system_hwmod,
1931         .slave          = &omap2430_l3_main_hwmod,
1932         .clk            = "core_l3_ck",
1933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1934 };
1935
1936 /* dma_system master ports */
1937 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1938         &omap2430_dma_system__l3,
1939 };
1940
1941 /* l4_core -> dma_system */
1942 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1943         .master         = &omap2430_l4_core_hwmod,
1944         .slave          = &omap2430_dma_system_hwmod,
1945         .clk            = "sdma_ick",
1946         .addr           = omap2430_dma_system_addrs,
1947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1948 };
1949
1950 /* dma_system slave ports */
1951 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1952         &omap2430_l4_core__dma_system,
1953 };
1954
1955 static struct omap_hwmod omap2430_dma_system_hwmod = {
1956         .name           = "dma",
1957         .class          = &omap2430_dma_hwmod_class,
1958         .mpu_irqs       = omap2430_dma_system_irqs,
1959         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
1960         .main_clk       = "core_l3_ck",
1961         .slaves         = omap2430_dma_system_slaves,
1962         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
1963         .masters        = omap2430_dma_system_masters,
1964         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
1965         .dev_attr       = &dma_dev_attr,
1966         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1967         .flags          = HWMOD_NO_IDLEST,
1968 };
1969
1970 /*
1971  * 'mailbox' class
1972  * mailbox module allowing communication between the on-chip processors
1973  * using a queued mailbox-interrupt mechanism.
1974  */
1975
1976 static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1977         .rev_offs       = 0x000,
1978         .sysc_offs      = 0x010,
1979         .syss_offs      = 0x014,
1980         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1981                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1983         .sysc_fields    = &omap_hwmod_sysc_type1,
1984 };
1985
1986 static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1987         .name = "mailbox",
1988         .sysc = &omap2430_mailbox_sysc,
1989 };
1990
1991 /* mailbox */
1992 static struct omap_hwmod omap2430_mailbox_hwmod;
1993 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1994         { .irq = 26 },
1995 };
1996
1997 static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
1998         {
1999                 .pa_start       = 0x48094000,
2000                 .pa_end         = 0x480941ff,
2001                 .flags          = ADDR_TYPE_RT,
2002         },
2003         { }
2004 };
2005
2006 /* l4_core -> mailbox */
2007 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
2008         .master         = &omap2430_l4_core_hwmod,
2009         .slave          = &omap2430_mailbox_hwmod,
2010         .addr           = omap2430_mailbox_addrs,
2011         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2012 };
2013
2014 /* mailbox slave ports */
2015 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
2016         &omap2430_l4_core__mailbox,
2017 };
2018
2019 static struct omap_hwmod omap2430_mailbox_hwmod = {
2020         .name           = "mailbox",
2021         .class          = &omap2430_mailbox_hwmod_class,
2022         .mpu_irqs       = omap2430_mailbox_irqs,
2023         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mailbox_irqs),
2024         .main_clk       = "mailboxes_ick",
2025         .prcm           = {
2026                 .omap2 = {
2027                         .prcm_reg_id = 1,
2028                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2029                         .module_offs = CORE_MOD,
2030                         .idlest_reg_id = 1,
2031                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
2032                 },
2033         },
2034         .slaves         = omap2430_mailbox_slaves,
2035         .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
2036         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2037 };
2038
2039 /*
2040  * 'mcspi' class
2041  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2042  * bus
2043  */
2044
2045 static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
2046         .rev_offs       = 0x0000,
2047         .sysc_offs      = 0x0010,
2048         .syss_offs      = 0x0014,
2049         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2050                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2051                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2052         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2053         .sysc_fields    = &omap_hwmod_sysc_type1,
2054 };
2055
2056 static struct omap_hwmod_class omap2430_mcspi_class = {
2057         .name = "mcspi",
2058         .sysc = &omap2430_mcspi_sysc,
2059         .rev = OMAP2_MCSPI_REV,
2060 };
2061
2062 /* mcspi1 */
2063 static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
2064         { .irq = 65 },
2065 };
2066
2067 static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
2068         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
2069         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
2070         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
2071         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
2072         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
2073         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
2074         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
2075         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
2076 };
2077
2078 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
2079         &omap2430_l4_core__mcspi1,
2080 };
2081
2082 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2083         .num_chipselect = 4,
2084 };
2085
2086 static struct omap_hwmod omap2430_mcspi1_hwmod = {
2087         .name           = "mcspi1_hwmod",
2088         .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
2089         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
2090         .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
2091         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
2092         .main_clk       = "mcspi1_fck",
2093         .prcm           = {
2094                 .omap2 = {
2095                         .module_offs = CORE_MOD,
2096                         .prcm_reg_id = 1,
2097                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
2098                         .idlest_reg_id = 1,
2099                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
2100                 },
2101         },
2102         .slaves         = omap2430_mcspi1_slaves,
2103         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
2104         .class          = &omap2430_mcspi_class,
2105         .dev_attr       = &omap_mcspi1_dev_attr,
2106         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2107 };
2108
2109 /* mcspi2 */
2110 static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
2111         { .irq = 66 },
2112 };
2113
2114 static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
2115         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
2116         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
2117         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
2118         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
2119 };
2120
2121 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
2122         &omap2430_l4_core__mcspi2,
2123 };
2124
2125 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2126         .num_chipselect = 2,
2127 };
2128
2129 static struct omap_hwmod omap2430_mcspi2_hwmod = {
2130         .name           = "mcspi2_hwmod",
2131         .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
2132         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
2133         .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
2134         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
2135         .main_clk       = "mcspi2_fck",
2136         .prcm           = {
2137                 .omap2 = {
2138                         .module_offs = CORE_MOD,
2139                         .prcm_reg_id = 1,
2140                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2141                         .idlest_reg_id = 1,
2142                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
2143                 },
2144         },
2145         .slaves         = omap2430_mcspi2_slaves,
2146         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
2147         .class          = &omap2430_mcspi_class,
2148         .dev_attr       = &omap_mcspi2_dev_attr,
2149         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2150 };
2151
2152 /* mcspi3 */
2153 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
2154         { .irq = 91 },
2155 };
2156
2157 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
2158         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
2159         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
2160         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
2161         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
2162 };
2163
2164 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
2165         &omap2430_l4_core__mcspi3,
2166 };
2167
2168 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2169         .num_chipselect = 2,
2170 };
2171
2172 static struct omap_hwmod omap2430_mcspi3_hwmod = {
2173         .name           = "mcspi3_hwmod",
2174         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
2175         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
2176         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
2177         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
2178         .main_clk       = "mcspi3_fck",
2179         .prcm           = {
2180                 .omap2 = {
2181                         .module_offs = CORE_MOD,
2182                         .prcm_reg_id = 2,
2183                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
2184                         .idlest_reg_id = 2,
2185                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
2186                 },
2187         },
2188         .slaves         = omap2430_mcspi3_slaves,
2189         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
2190         .class          = &omap2430_mcspi_class,
2191         .dev_attr       = &omap_mcspi3_dev_attr,
2192         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2193 };
2194
2195 /*
2196  * usbhsotg
2197  */
2198 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
2199         .rev_offs       = 0x0400,
2200         .sysc_offs      = 0x0404,
2201         .syss_offs      = 0x0408,
2202         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2203                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2204                           SYSC_HAS_AUTOIDLE),
2205         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2206                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2207         .sysc_fields    = &omap_hwmod_sysc_type1,
2208 };
2209
2210 static struct omap_hwmod_class usbotg_class = {
2211         .name = "usbotg",
2212         .sysc = &omap2430_usbhsotg_sysc,
2213 };
2214
2215 /* usb_otg_hs */
2216 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
2217
2218         { .name = "mc", .irq = 92 },
2219         { .name = "dma", .irq = 93 },
2220 };
2221
2222 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
2223         .name           = "usb_otg_hs",
2224         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
2225         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
2226         .main_clk       = "usbhs_ick",
2227         .prcm           = {
2228                 .omap2 = {
2229                         .prcm_reg_id = 1,
2230                         .module_bit = OMAP2430_EN_USBHS_MASK,
2231                         .module_offs = CORE_MOD,
2232                         .idlest_reg_id = 1,
2233                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
2234                 },
2235         },
2236         .masters        = omap2430_usbhsotg_masters,
2237         .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
2238         .slaves         = omap2430_usbhsotg_slaves,
2239         .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
2240         .class          = &usbotg_class,
2241         /*
2242          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
2243          * broken when autoidle is enabled
2244          * workaround is to disable the autoidle bit at module level.
2245          */
2246         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2247                                 | HWMOD_SWSUP_MSTANDBY,
2248         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
2249 };
2250
2251 /*
2252  * 'mcbsp' class
2253  * multi channel buffered serial port controller
2254  */
2255
2256 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
2257         .rev_offs       = 0x007C,
2258         .sysc_offs      = 0x008C,
2259         .sysc_flags     = (SYSC_HAS_SOFTRESET),
2260         .sysc_fields    = &omap_hwmod_sysc_type1,
2261 };
2262
2263 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
2264         .name = "mcbsp",
2265         .sysc = &omap2430_mcbsp_sysc,
2266         .rev  = MCBSP_CONFIG_TYPE2,
2267 };
2268
2269 /* mcbsp1 */
2270 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
2271         { .name = "tx",         .irq = 59 },
2272         { .name = "rx",         .irq = 60 },
2273         { .name = "ovr",        .irq = 61 },
2274         { .name = "common",     .irq = 64 },
2275 };
2276
2277 static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
2278         { .name = "rx", .dma_req = 32 },
2279         { .name = "tx", .dma_req = 31 },
2280 };
2281
2282 static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
2283         {
2284                 .name           = "mpu",
2285                 .pa_start       = 0x48074000,
2286                 .pa_end         = 0x480740ff,
2287                 .flags          = ADDR_TYPE_RT
2288         },
2289         { }
2290 };
2291
2292 /* l4_core -> mcbsp1 */
2293 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
2294         .master         = &omap2430_l4_core_hwmod,
2295         .slave          = &omap2430_mcbsp1_hwmod,
2296         .clk            = "mcbsp1_ick",
2297         .addr           = omap2430_mcbsp1_addrs,
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300
2301 /* mcbsp1 slave ports */
2302 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
2303         &omap2430_l4_core__mcbsp1,
2304 };
2305
2306 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
2307         .name           = "mcbsp1",
2308         .class          = &omap2430_mcbsp_hwmod_class,
2309         .mpu_irqs       = omap2430_mcbsp1_irqs,
2310         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp1_irqs),
2311         .sdma_reqs      = omap2430_mcbsp1_sdma_chs,
2312         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
2313         .main_clk       = "mcbsp1_fck",
2314         .prcm           = {
2315                 .omap2 = {
2316                         .prcm_reg_id = 1,
2317                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2318                         .module_offs = CORE_MOD,
2319                         .idlest_reg_id = 1,
2320                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2321                 },
2322         },
2323         .slaves         = omap2430_mcbsp1_slaves,
2324         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
2325         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2326 };
2327
2328 /* mcbsp2 */
2329 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
2330         { .name = "tx",         .irq = 62 },
2331         { .name = "rx",         .irq = 63 },
2332         { .name = "common",     .irq = 16 },
2333 };
2334
2335 static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
2336         { .name = "rx", .dma_req = 34 },
2337         { .name = "tx", .dma_req = 33 },
2338 };
2339
2340 static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
2341         {
2342                 .name           = "mpu",
2343                 .pa_start       = 0x48076000,
2344                 .pa_end         = 0x480760ff,
2345                 .flags          = ADDR_TYPE_RT
2346         },
2347         { }
2348 };
2349
2350 /* l4_core -> mcbsp2 */
2351 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
2352         .master         = &omap2430_l4_core_hwmod,
2353         .slave          = &omap2430_mcbsp2_hwmod,
2354         .clk            = "mcbsp2_ick",
2355         .addr           = omap2430_mcbsp2_addrs,
2356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2357 };
2358
2359 /* mcbsp2 slave ports */
2360 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
2361         &omap2430_l4_core__mcbsp2,
2362 };
2363
2364 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
2365         .name           = "mcbsp2",
2366         .class          = &omap2430_mcbsp_hwmod_class,
2367         .mpu_irqs       = omap2430_mcbsp2_irqs,
2368         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp2_irqs),
2369         .sdma_reqs      = omap2430_mcbsp2_sdma_chs,
2370         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
2371         .main_clk       = "mcbsp2_fck",
2372         .prcm           = {
2373                 .omap2 = {
2374                         .prcm_reg_id = 1,
2375                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2376                         .module_offs = CORE_MOD,
2377                         .idlest_reg_id = 1,
2378                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2379                 },
2380         },
2381         .slaves         = omap2430_mcbsp2_slaves,
2382         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
2383         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2384 };
2385
2386 /* mcbsp3 */
2387 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
2388         { .name = "tx",         .irq = 89 },
2389         { .name = "rx",         .irq = 90 },
2390         { .name = "common",     .irq = 17 },
2391 };
2392
2393 static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
2394         { .name = "rx", .dma_req = 18 },
2395         { .name = "tx", .dma_req = 17 },
2396 };
2397
2398 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
2399         {
2400                 .name           = "mpu",
2401                 .pa_start       = 0x4808C000,
2402                 .pa_end         = 0x4808C0ff,
2403                 .flags          = ADDR_TYPE_RT
2404         },
2405         { }
2406 };
2407
2408 /* l4_core -> mcbsp3 */
2409 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
2410         .master         = &omap2430_l4_core_hwmod,
2411         .slave          = &omap2430_mcbsp3_hwmod,
2412         .clk            = "mcbsp3_ick",
2413         .addr           = omap2430_mcbsp3_addrs,
2414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2415 };
2416
2417 /* mcbsp3 slave ports */
2418 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
2419         &omap2430_l4_core__mcbsp3,
2420 };
2421
2422 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
2423         .name           = "mcbsp3",
2424         .class          = &omap2430_mcbsp_hwmod_class,
2425         .mpu_irqs       = omap2430_mcbsp3_irqs,
2426         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp3_irqs),
2427         .sdma_reqs      = omap2430_mcbsp3_sdma_chs,
2428         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
2429         .main_clk       = "mcbsp3_fck",
2430         .prcm           = {
2431                 .omap2 = {
2432                         .prcm_reg_id = 1,
2433                         .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
2434                         .module_offs = CORE_MOD,
2435                         .idlest_reg_id = 2,
2436                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
2437                 },
2438         },
2439         .slaves         = omap2430_mcbsp3_slaves,
2440         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
2441         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2442 };
2443
2444 /* mcbsp4 */
2445 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
2446         { .name = "tx",         .irq = 54 },
2447         { .name = "rx",         .irq = 55 },
2448         { .name = "common",     .irq = 18 },
2449 };
2450
2451 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
2452         { .name = "rx", .dma_req = 20 },
2453         { .name = "tx", .dma_req = 19 },
2454 };
2455
2456 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
2457         {
2458                 .name           = "mpu",
2459                 .pa_start       = 0x4808E000,
2460                 .pa_end         = 0x4808E0ff,
2461                 .flags          = ADDR_TYPE_RT
2462         },
2463         { }
2464 };
2465
2466 /* l4_core -> mcbsp4 */
2467 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
2468         .master         = &omap2430_l4_core_hwmod,
2469         .slave          = &omap2430_mcbsp4_hwmod,
2470         .clk            = "mcbsp4_ick",
2471         .addr           = omap2430_mcbsp4_addrs,
2472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2473 };
2474
2475 /* mcbsp4 slave ports */
2476 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
2477         &omap2430_l4_core__mcbsp4,
2478 };
2479
2480 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
2481         .name           = "mcbsp4",
2482         .class          = &omap2430_mcbsp_hwmod_class,
2483         .mpu_irqs       = omap2430_mcbsp4_irqs,
2484         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp4_irqs),
2485         .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
2486         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
2487         .main_clk       = "mcbsp4_fck",
2488         .prcm           = {
2489                 .omap2 = {
2490                         .prcm_reg_id = 1,
2491                         .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
2492                         .module_offs = CORE_MOD,
2493                         .idlest_reg_id = 2,
2494                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
2495                 },
2496         },
2497         .slaves         = omap2430_mcbsp4_slaves,
2498         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
2499         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2500 };
2501
2502 /* mcbsp5 */
2503 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
2504         { .name = "tx",         .irq = 81 },
2505         { .name = "rx",         .irq = 82 },
2506         { .name = "common",     .irq = 19 },
2507 };
2508
2509 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
2510         { .name = "rx", .dma_req = 22 },
2511         { .name = "tx", .dma_req = 21 },
2512 };
2513
2514 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
2515         {
2516                 .name           = "mpu",
2517                 .pa_start       = 0x48096000,
2518                 .pa_end         = 0x480960ff,
2519                 .flags          = ADDR_TYPE_RT
2520         },
2521         { }
2522 };
2523
2524 /* l4_core -> mcbsp5 */
2525 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
2526         .master         = &omap2430_l4_core_hwmod,
2527         .slave          = &omap2430_mcbsp5_hwmod,
2528         .clk            = "mcbsp5_ick",
2529         .addr           = omap2430_mcbsp5_addrs,
2530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2531 };
2532
2533 /* mcbsp5 slave ports */
2534 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
2535         &omap2430_l4_core__mcbsp5,
2536 };
2537
2538 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
2539         .name           = "mcbsp5",
2540         .class          = &omap2430_mcbsp_hwmod_class,
2541         .mpu_irqs       = omap2430_mcbsp5_irqs,
2542         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp5_irqs),
2543         .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
2544         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
2545         .main_clk       = "mcbsp5_fck",
2546         .prcm           = {
2547                 .omap2 = {
2548                         .prcm_reg_id = 1,
2549                         .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
2550                         .module_offs = CORE_MOD,
2551                         .idlest_reg_id = 2,
2552                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
2553                 },
2554         },
2555         .slaves         = omap2430_mcbsp5_slaves,
2556         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
2557         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2558 };
2559
2560 /* MMC/SD/SDIO common */
2561
2562 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
2563         .rev_offs       = 0x1fc,
2564         .sysc_offs      = 0x10,
2565         .syss_offs      = 0x14,
2566         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2567                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2568                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2569         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2570         .sysc_fields    = &omap_hwmod_sysc_type1,
2571 };
2572
2573 static struct omap_hwmod_class omap2430_mmc_class = {
2574         .name = "mmc",
2575         .sysc = &omap2430_mmc_sysc,
2576 };
2577
2578 /* MMC/SD/SDIO1 */
2579
2580 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2581         { .irq = 83 },
2582 };
2583
2584 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2585         { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2586         { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
2587 };
2588
2589 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
2590         { .role = "dbck", .clk = "mmchsdb1_fck" },
2591 };
2592
2593 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
2594         &omap2430_l4_core__mmc1,
2595 };
2596
2597 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2598         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2599 };
2600
2601 static struct omap_hwmod omap2430_mmc1_hwmod = {
2602         .name           = "mmc1",
2603         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2604         .mpu_irqs       = omap2430_mmc1_mpu_irqs,
2605         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2606         .sdma_reqs      = omap2430_mmc1_sdma_reqs,
2607         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2608         .opt_clks       = omap2430_mmc1_opt_clks,
2609         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2610         .main_clk       = "mmchs1_fck",
2611         .prcm           = {
2612                 .omap2 = {
2613                         .module_offs = CORE_MOD,
2614                         .prcm_reg_id = 2,
2615                         .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
2616                         .idlest_reg_id = 2,
2617                         .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
2618                 },
2619         },
2620         .dev_attr       = &mmc1_dev_attr,
2621         .slaves         = omap2430_mmc1_slaves,
2622         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
2623         .class          = &omap2430_mmc_class,
2624         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2625 };
2626
2627 /* MMC/SD/SDIO2 */
2628
2629 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2630         { .irq = 86 },
2631 };
2632
2633 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2634         { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2635         { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
2636 };
2637
2638 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
2639         { .role = "dbck", .clk = "mmchsdb2_fck" },
2640 };
2641
2642 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
2643         &omap2430_l4_core__mmc2,
2644 };
2645
2646 static struct omap_hwmod omap2430_mmc2_hwmod = {
2647         .name           = "mmc2",
2648         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2649         .mpu_irqs       = omap2430_mmc2_mpu_irqs,
2650         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2651         .sdma_reqs      = omap2430_mmc2_sdma_reqs,
2652         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2653         .opt_clks       = omap2430_mmc2_opt_clks,
2654         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2655         .main_clk       = "mmchs2_fck",
2656         .prcm           = {
2657                 .omap2 = {
2658                         .module_offs = CORE_MOD,
2659                         .prcm_reg_id = 2,
2660                         .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
2661                         .idlest_reg_id = 2,
2662                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2663                 },
2664         },
2665         .slaves         = omap2430_mmc2_slaves,
2666         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
2667         .class          = &omap2430_mmc_class,
2668         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2669 };
2670
2671 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2672         &omap2430_l3_main_hwmod,
2673         &omap2430_l4_core_hwmod,
2674         &omap2430_l4_wkup_hwmod,
2675         &omap2430_mpu_hwmod,
2676         &omap2430_iva_hwmod,
2677
2678         &omap2430_timer1_hwmod,
2679         &omap2430_timer2_hwmod,
2680         &omap2430_timer3_hwmod,
2681         &omap2430_timer4_hwmod,
2682         &omap2430_timer5_hwmod,
2683         &omap2430_timer6_hwmod,
2684         &omap2430_timer7_hwmod,
2685         &omap2430_timer8_hwmod,
2686         &omap2430_timer9_hwmod,
2687         &omap2430_timer10_hwmod,
2688         &omap2430_timer11_hwmod,
2689         &omap2430_timer12_hwmod,
2690
2691         &omap2430_wd_timer2_hwmod,
2692         &omap2430_uart1_hwmod,
2693         &omap2430_uart2_hwmod,
2694         &omap2430_uart3_hwmod,
2695         /* dss class */
2696         &omap2430_dss_core_hwmod,
2697         &omap2430_dss_dispc_hwmod,
2698         &omap2430_dss_rfbi_hwmod,
2699         &omap2430_dss_venc_hwmod,
2700         /* i2c class */
2701         &omap2430_i2c1_hwmod,
2702         &omap2430_i2c2_hwmod,
2703         &omap2430_mmc1_hwmod,
2704         &omap2430_mmc2_hwmod,
2705
2706         /* gpio class */
2707         &omap2430_gpio1_hwmod,
2708         &omap2430_gpio2_hwmod,
2709         &omap2430_gpio3_hwmod,
2710         &omap2430_gpio4_hwmod,
2711         &omap2430_gpio5_hwmod,
2712
2713         /* dma_system class*/
2714         &omap2430_dma_system_hwmod,
2715
2716         /* mcbsp class */
2717         &omap2430_mcbsp1_hwmod,
2718         &omap2430_mcbsp2_hwmod,
2719         &omap2430_mcbsp3_hwmod,
2720         &omap2430_mcbsp4_hwmod,
2721         &omap2430_mcbsp5_hwmod,
2722
2723         /* mailbox class */
2724         &omap2430_mailbox_hwmod,
2725
2726         /* mcspi class */
2727         &omap2430_mcspi1_hwmod,
2728         &omap2430_mcspi2_hwmod,
2729         &omap2430_mcspi3_hwmod,
2730
2731         /* usbotg class*/
2732         &omap2430_usbhsotg_hwmod,
2733
2734         NULL,
2735 };
2736
2737 int __init omap2430_hwmod_init(void)
2738 {
2739         return omap_hwmod_register(omap2430_hwmods);
2740 }